1SimpleLTInitiator1/SimpleLTTarget1 2---------------------------------- 3 4- LT Initiator/Target model using the base (standard) tlm socket 5- Added support for DMI in SimpleLTTarget1 6 7SimpleLTInitiator1_DMI 8---------------------- 9 10- uses DMI transactions, the DMI structure is using the DMI-hint 11 to check if a DMI request would make sense. 12- uses a single transport_dbg transaction at end_of_simulation() 13 14SimpleLTInitiator2/SimpleLTTarget2 15---------------------------------- 16 17- LT Initiator/Target model using the convenience tlm socket 18- Target and Initiator model use the REGISTER_DEBUGTRANSPORT macro to register 19 a transport callback to the socket 20- Added support for DMI handling, callback registration with 21 REGISTER_DMI 22- SimpleLTTarget2 does not register the transport_dbg callback, so that 23 we are able to test this case in bus_dmi. 24 25SimpleLTInitiator2_DMI 26---------------------- 27 28- uses DMI transactions, but ignoring the DMI hint 29- uses a single transport_dbg transaction at end_of_simulation() 30 31SimpleLTInitiator3 32------------------ 33 34- LT Initiator model using the convenience tlm socket 35- Initiator model uses the endEvent of the socket to wait until the 36 transaction is finished 37 38SimpleLTInitiator3_DMI 39---------------------- 40 41- based on SimpleInitiator3, uses DMI (without DMI hint) 42 43SimpleATInitiator1/SimpleATTarget1 44---------------------------------- 45 46- AT Initiator/Target model implementing the AT protocol 47- one call of nb_transport for each timing point in the protocol (BEGIN_REQ, 48 END_REQ, BEGIN_RESP and END_RESP) 49 50SimpleATInitiator2/SimpleATTarget2 51---------------------------------- 52 53- AT Initiator/Target model implementing the AT protocol with timing annotation 54- only a call of nb_transport for the start of a phase (BEGIN_REQ and 55 BEGIN_RESP) 56- end of a phase is notified via timing annotation (t argument) 57 58CoreDecouplingLTInitiator 59------------------------- 60 61- LT Initiator using 'Core Decoupling' 62 63ExplicitLTTarget 64---------------- 65 66- LT Target that uses explicit timing (calls wait) 67- added support for debug transactions 68 69ExplicitLTTarget 70---------------- 71 72- AT Target, only registers nb_transport 73 74SimpleBus 75--------- 76 77- Simple bus model 78- Runtime switcheable between LT and AT (can only switch if no transactions 79 are pending) 80- No limitation on number of pending transactions (all targets that can return 81 false must support multiple transactions) 82- added support for DMI and debug transactions 83- LT mode: 84-- Forward nb_transport calls to initiator/targets 85-- Only one active request/response phase 86- AT mode: 87-- Incoming transactions are queued 88-- AT protocol is executed from a different SC_THREAD 89-- A target is notified immediately of the end of a transaction (using timing 90 annotation). This is needed because the initiator can re-use the 91 transaction (and the target may use the transaction pointer to identify the 92 transaction) 93