pseudo_inst.cc revision 3089
1/* 2 * Copyright (c) 2003-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Nathan Binkert 29 */ 30 31#include <errno.h> 32#include <fcntl.h> 33#include <unistd.h> 34 35#include <string> 36 37#include "sim/pseudo_inst.hh" 38#include "arch/vtophys.hh" 39#include "base/annotate.hh" 40#include "cpu/base.hh" 41#include "cpu/thread_context.hh" 42#include "cpu/quiesce_event.hh" 43#include "kern/kernel_stats.hh" 44#include "sim/param.hh" 45#include "sim/serialize.hh" 46#include "sim/sim_exit.hh" 47#include "sim/stat_control.hh" 48#include "sim/stats.hh" 49#include "sim/system.hh" 50#include "sim/debug.hh" 51#include "sim/vptr.hh" 52 53using namespace std; 54 55using namespace Stats; 56using namespace TheISA; 57 58namespace AlphaPseudo 59{ 60 bool doStatisticsInsts; 61 bool doCheckpointInsts; 62 bool doQuiesce; 63 64 void 65 arm(ThreadContext *tc) 66 { 67 if (tc->getKernelStats()) 68 tc->getKernelStats()->arm(); 69 } 70 71 void 72 quiesce(ThreadContext *tc) 73 { 74 if (!doQuiesce) 75 return; 76 77 tc->suspend(); 78 if (tc->getKernelStats()) 79 tc->getKernelStats()->quiesce(); 80 } 81 82 void 83 quiesceNs(ThreadContext *tc, uint64_t ns) 84 { 85 if (!doQuiesce || ns == 0) 86 return; 87 88 EndQuiesceEvent *quiesceEvent = tc->getQuiesceEvent(); 89 90 if (quiesceEvent->scheduled()) 91 quiesceEvent->reschedule(curTick + Clock::Int::ns * ns); 92 else 93 quiesceEvent->schedule(curTick + Clock::Int::ns * ns); 94 95 tc->suspend(); 96 if (tc->getKernelStats()) 97 tc->getKernelStats()->quiesce(); 98 } 99 100 void 101 quiesceCycles(ThreadContext *tc, uint64_t cycles) 102 { 103 if (!doQuiesce || cycles == 0) 104 return; 105 106 EndQuiesceEvent *quiesceEvent = tc->getQuiesceEvent(); 107 108 if (quiesceEvent->scheduled()) 109 quiesceEvent->reschedule(curTick + 110 tc->getCpuPtr()->cycles(cycles)); 111 else 112 quiesceEvent->schedule(curTick + 113 tc->getCpuPtr()->cycles(cycles)); 114 115 tc->suspend(); 116 if (tc->getKernelStats()) 117 tc->getKernelStats()->quiesce(); 118 } 119 120 uint64_t 121 quiesceTime(ThreadContext *tc) 122 { 123 return (tc->readLastActivate() - tc->readLastSuspend()) / Clock::Int::ns; 124 } 125 126 void 127 ivlb(ThreadContext *tc) 128 { 129 if (tc->getKernelStats()) 130 tc->getKernelStats()->ivlb(); 131 } 132 133 void 134 ivle(ThreadContext *tc) 135 { 136 } 137 138 void 139 m5exit_old(ThreadContext *tc) 140 { 141 exitSimLoop(curTick, "m5_exit_old instruction encountered"); 142 } 143 144 void 145 m5exit(ThreadContext *tc, Tick delay) 146 { 147 Tick when = curTick + delay * Clock::Int::ns; 148 exitSimLoop(when, "m5_exit instruction encountered"); 149 } 150 151 void 152 resetstats(ThreadContext *tc, Tick delay, Tick period) 153 { 154 if (!doStatisticsInsts) 155 return; 156 157 158 Tick when = curTick + delay * Clock::Int::ns; 159 Tick repeat = period * Clock::Int::ns; 160 161 using namespace Stats; 162 SetupEvent(Reset, when, repeat); 163 } 164 165 void 166 dumpstats(ThreadContext *tc, Tick delay, Tick period) 167 { 168 if (!doStatisticsInsts) 169 return; 170 171 172 Tick when = curTick + delay * Clock::Int::ns; 173 Tick repeat = period * Clock::Int::ns; 174 175 using namespace Stats; 176 SetupEvent(Dump, when, repeat); 177 } 178 179 void 180 addsymbol(ThreadContext *tc, Addr addr, Addr symbolAddr) 181 { 182 char symb[100]; 183 CopyStringOut(tc, symb, symbolAddr, 100); 184 std::string symbol(symb); 185 186 DPRINTF(Loader, "Loaded symbol: %s @ %#llx\n", symbol, addr); 187 188 tc->getSystemPtr()->kernelSymtab->insert(addr,symbol); 189 } 190 191 void 192 anBegin(ThreadContext *tc, uint64_t cur) 193 { 194 Annotate::annotations.add(tc->getSystemPtr(), 0, cur >> 32, cur & 195 0xFFFFFFFF, 0,0); 196 } 197 198 void 199 anWait(ThreadContext *tc, uint64_t cur, uint64_t wait) 200 { 201 Annotate::annotations.add(tc->getSystemPtr(), 0, cur >> 32, cur & 202 0xFFFFFFFF, wait >> 32, wait & 0xFFFFFFFF); 203 } 204 205 206 void 207 dumpresetstats(ThreadContext *tc, Tick delay, Tick period) 208 { 209 if (!doStatisticsInsts) 210 return; 211 212 213 Tick when = curTick + delay * Clock::Int::ns; 214 Tick repeat = period * Clock::Int::ns; 215 216 using namespace Stats; 217 SetupEvent(Dump|Reset, when, repeat); 218 } 219 220 void 221 m5checkpoint(ThreadContext *tc, Tick delay, Tick period) 222 { 223 if (!doCheckpointInsts) 224 return; 225 exitSimLoop("checkpoint"); 226 } 227 228 uint64_t 229 readfile(ThreadContext *tc, Addr vaddr, uint64_t len, uint64_t offset) 230 { 231 const string &file = tc->getCpuPtr()->system->params()->readfile; 232 if (file.empty()) { 233 return ULL(0); 234 } 235 236 uint64_t result = 0; 237 238 int fd = ::open(file.c_str(), O_RDONLY, 0); 239 if (fd < 0) 240 panic("could not open file %s\n", file); 241 242 if (::lseek(fd, offset, SEEK_SET) < 0) 243 panic("could not seek: %s", strerror(errno)); 244 245 char *buf = new char[len]; 246 char *p = buf; 247 while (len > 0) { 248 int bytes = ::read(fd, p, len); 249 if (bytes <= 0) 250 break; 251 252 p += bytes; 253 result += bytes; 254 len -= bytes; 255 } 256 257 close(fd); 258 CopyIn(tc, vaddr, buf, result); 259 delete [] buf; 260 return result; 261 } 262 263 class Context : public ParamContext 264 { 265 public: 266 Context(const string §ion) : ParamContext(section) {} 267 void checkParams(); 268 }; 269 270 Context context("pseudo_inst"); 271 272 Param<bool> __quiesce(&context, "quiesce", 273 "enable quiesce instructions", 274 true); 275 Param<bool> __statistics(&context, "statistics", 276 "enable statistics pseudo instructions", 277 true); 278 Param<bool> __checkpoint(&context, "checkpoint", 279 "enable checkpoint pseudo instructions", 280 true); 281 282 void 283 Context::checkParams() 284 { 285 doQuiesce = __quiesce; 286 doStatisticsInsts = __statistics; 287 doCheckpointInsts = __checkpoint; 288 } 289 290 void debugbreak(ThreadContext *tc) 291 { 292 debug_break(); 293 } 294 295 void switchcpu(ThreadContext *tc) 296 { 297 exitSimLoop("switchcpu"); 298 } 299} 300