pseudo_inst.cc revision 1070
1/* 2 * Copyright (c) 2003-2004 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29#include <fcntl.h> 30#include <unistd.h> 31#include <cstdio> 32 33#include <string> 34 35#include "arch/alpha/pseudo_inst.hh" 36#include "arch/alpha/vtophys.hh" 37#include "cpu/base_cpu.hh" 38#include "cpu/sampling_cpu/sampling_cpu.hh" 39#include "cpu/exec_context.hh" 40#include "kern/kernel_stats.hh" 41#include "sim/param.hh" 42#include "sim/serialize.hh" 43#include "sim/sim_exit.hh" 44#include "sim/stat_control.hh" 45#include "sim/stats.hh" 46#include "sim/system.hh" 47#include "sim/debug.hh" 48 49using namespace std; 50 51extern SamplingCPU *SampCPU; 52 53using namespace Stats; 54 55namespace AlphaPseudo 56{ 57 bool doStatisticsInsts; 58 bool doCheckpointInsts; 59 bool doQuiesce; 60 61 void 62 arm(ExecContext *xc) 63 { 64 xc->kernelStats->arm(); 65 } 66 67 void 68 quiesce(ExecContext *xc) 69 { 70 if (!doQuiesce) 71 return; 72 73 xc->suspend(); 74 xc->kernelStats->quiesce(); 75 } 76 77 void 78 ivlb(ExecContext *xc) 79 { 80 xc->kernelStats->ivlb(); 81 } 82 83 void 84 ivle(ExecContext *xc) 85 { 86 } 87 88 void 89 m5exit_old(ExecContext *xc) 90 { 91 SimExit(curTick, "m5_exit_old instruction encountered"); 92 } 93 94 void 95 m5exit(ExecContext *xc) 96 { 97 Tick delay = xc->regs.intRegFile[16]; 98 Tick when = curTick + NS2Ticks(delay); 99 SimExit(when, "m5_exit instruction encountered"); 100 } 101 102 void 103 resetstats(ExecContext *xc) 104 { 105 if (!doStatisticsInsts) 106 return; 107 108 Tick delay = xc->regs.intRegFile[16]; 109 Tick period = xc->regs.intRegFile[17]; 110 111 Tick when = curTick + NS2Ticks(delay); 112 Tick repeat = NS2Ticks(period); 113 114 using namespace Stats; 115 SetupEvent(Reset, when, repeat); 116 } 117 118 void 119 dumpstats(ExecContext *xc) 120 { 121 if (!doStatisticsInsts) 122 return; 123 124 Tick delay = xc->regs.intRegFile[16]; 125 Tick period = xc->regs.intRegFile[17]; 126 127 Tick when = curTick + NS2Ticks(delay); 128 Tick repeat = NS2Ticks(period); 129 130 using namespace Stats; 131 SetupEvent(Dump, when, repeat); 132 } 133 134 void 135 dumpresetstats(ExecContext *xc) 136 { 137 if (!doStatisticsInsts) 138 return; 139 140 Tick delay = xc->regs.intRegFile[16]; 141 Tick period = xc->regs.intRegFile[17]; 142 143 Tick when = curTick + NS2Ticks(delay); 144 Tick repeat = NS2Ticks(period); 145 146 using namespace Stats; 147 SetupEvent(Dump|Reset, when, repeat); 148 } 149 150 void 151 m5checkpoint(ExecContext *xc) 152 { 153 if (!doCheckpointInsts) 154 return; 155 156 Tick delay = xc->regs.intRegFile[16]; 157 Tick period = xc->regs.intRegFile[17]; 158 159 Tick when = curTick + NS2Ticks(delay); 160 Tick repeat = NS2Ticks(period); 161 162 Checkpoint::setup(when, repeat); 163 } 164 165 void 166 readfile(ExecContext *xc) 167 { 168 const string &file = xc->cpu->system->params->readfile; 169 if (file.empty()) { 170 xc->regs.intRegFile[0] = ULL(0); 171 return; 172 } 173 174 Addr vaddr = xc->regs.intRegFile[16]; 175 uint64_t len = xc->regs.intRegFile[17]; 176 uint64_t offset = xc->regs.intRegFile[18]; 177 uint64_t result = 0; 178 179 int fd = ::open(file.c_str(), O_RDONLY, 0); 180 if (fd < 0) 181 panic("could not open file %s\n", file); 182 183 char *buf = new char[len]; 184 char *p = buf; 185 while (len > 0) { 186 int bytes = ::pread(fd, p, len, offset); 187 if (bytes <= 0) 188 break; 189 190 p += bytes; 191 offset += bytes; 192 result += bytes; 193 len -= bytes; 194 } 195 196 close(fd); 197 CopyIn(xc, vaddr, buf, result); 198 delete [] buf; 199 xc->regs.intRegFile[0] = result; 200 } 201 202 class Context : public ParamContext 203 { 204 public: 205 Context(const string §ion) : ParamContext(section) {} 206 void checkParams(); 207 }; 208 209 Context context("PseudoInsts"); 210 211 Param<bool> __quiesce(&context, "quiesce", 212 "enable quiesce instructions", 213 true); 214 Param<bool> __statistics(&context, "statistics", 215 "enable statistics pseudo instructions", 216 true); 217 Param<bool> __checkpoint(&context, "checkpoint", 218 "enable checkpoint pseudo instructions", 219 true); 220 221 void 222 Context::checkParams() 223 { 224 doQuiesce = __quiesce; 225 doStatisticsInsts = __statistics; 226 doCheckpointInsts = __checkpoint; 227 } 228 229 void debugbreak(ExecContext *xc) 230 { 231 debug_break(); 232 } 233 234 void switchcpu(ExecContext *xc) 235 { 236 if (SampCPU) 237 SampCPU->switchCPUs(); 238 } 239} 240