pseudo_inst.cc revision 1052 
1/*
2 * Copyright (c) 2003-2004 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#include <fcntl.h>
30#include <unistd.h>
31#include <cstdio>
32
33#include <string>
34
35#include "arch/alpha/pseudo_inst.hh"
36#include "arch/alpha/vtophys.hh"
37#include "cpu/base_cpu.hh"
38#include "cpu/sampling_cpu/sampling_cpu.hh"
39#include "cpu/exec_context.hh"
40#include "sim/param.hh"
41#include "sim/serialize.hh"
42#include "sim/sim_exit.hh"
43#include "sim/stat_control.hh"
44#include "sim/stats.hh"
45#include "sim/system.hh"
46#include "sim/debug.hh"
47
48using namespace std;
49
50extern SamplingCPU *SampCPU;
51
52using namespace Stats;
53
54namespace AlphaPseudo
55{
56    bool doStatisticsInsts;
57    bool doCheckpointInsts;
58    bool doQuiesce;
59
60    void
61    arm(ExecContext *xc)
62    {
63        xc->kernelStats.arm();
64    }
65
66    void
67    quiesce(ExecContext *xc)
68    {
69        if (!doQuiesce)
70            return;
71
72        xc->suspend();
73        xc->kernelStats.quiesce();
74    }
75
76    void
77    ivlb(ExecContext *xc)
78    {
79        xc->kernelStats.ivlb();
80    }
81
82    void
83    ivle(ExecContext *xc)
84    {
85    }
86
87    void
88    m5exit_old(ExecContext *xc)
89    {
90        SimExit(curTick, "m5_exit_old instruction encountered");
91    }
92
93    void
94    m5exit(ExecContext *xc)
95    {
96        Tick delay = xc->regs.intRegFile[16];
97        Tick when = curTick + NS2Ticks(delay);
98        SimExit(when, "m5_exit instruction encountered");
99    }
100
101    void
102    resetstats(ExecContext *xc)
103    {
104        if (!doStatisticsInsts)
105            return;
106
107        Tick delay = xc->regs.intRegFile[16];
108        Tick period = xc->regs.intRegFile[17];
109
110        Tick when = curTick + NS2Ticks(delay);
111        Tick repeat = NS2Ticks(period);
112
113        using namespace Stats;
114        SetupEvent(Reset, when, repeat);
115    }
116
117    void
118    dumpstats(ExecContext *xc)
119    {
120        if (!doStatisticsInsts)
121            return;
122
123        Tick delay = xc->regs.intRegFile[16];
124        Tick period = xc->regs.intRegFile[17];
125
126        Tick when = curTick + NS2Ticks(delay);
127        Tick repeat = NS2Ticks(period);
128
129        using namespace Stats;
130        SetupEvent(Dump, when, repeat);
131    }
132
133    void
134    dumpresetstats(ExecContext *xc)
135    {
136        if (!doStatisticsInsts)
137            return;
138
139        Tick delay = xc->regs.intRegFile[16];
140        Tick period = xc->regs.intRegFile[17];
141
142        Tick when = curTick + NS2Ticks(delay);
143        Tick repeat = NS2Ticks(period);
144
145        using namespace Stats;
146        SetupEvent(Dump|Reset, when, repeat);
147    }
148
149    void
150    m5checkpoint(ExecContext *xc)
151    {
152        if (!doCheckpointInsts)
153            return;
154
155        Tick delay = xc->regs.intRegFile[16];
156        Tick period = xc->regs.intRegFile[17];
157
158        Tick when = curTick + NS2Ticks(delay);
159        Tick repeat = NS2Ticks(period);
160
161        Checkpoint::setup(when, repeat);
162    }
163
164    void
165    readfile(ExecContext *xc)
166    {
167        const string &file = xc->cpu->system->readfile;
168        if (file.empty()) {
169            xc->regs.intRegFile[0] = ULL(0);
170            return;
171        }
172
173        Addr vaddr = xc->regs.intRegFile[16];
174        uint64_t len = xc->regs.intRegFile[17];
175        uint64_t offset = xc->regs.intRegFile[18];
176        uint64_t result = 0;
177
178        int fd = ::open(file.c_str(), O_RDONLY, 0);
179        if (fd < 0)
180            panic("could not open file %s\n", file);
181
182        char *buf = new char[len];
183        char *p = buf;
184        while (len > 0) {
185            int bytes = ::pread(fd, p, len, offset);
186            if (bytes <= 0)
187                break;
188
189            p += bytes;
190            offset += bytes;
191            result += bytes;
192            len -= bytes;
193        }
194
195        close(fd);
196        CopyIn(xc, vaddr, buf, result);
197        delete [] buf;
198        xc->regs.intRegFile[0] = result;
199    }
200
201    class Context : public ParamContext
202    {
203      public:
204        Context(const string &section) : ParamContext(section) {}
205        void checkParams();
206    };
207
208    Context context("PseudoInsts");
209
210    Param<bool> __quiesce(&context, "quiesce",
211                          "enable quiesce instructions",
212                          true);
213    Param<bool> __statistics(&context, "statistics",
214                             "enable statistics pseudo instructions",
215                             true);
216    Param<bool> __checkpoint(&context, "checkpoint",
217                             "enable checkpoint pseudo instructions",
218                             true);
219
220    void
221    Context::checkParams()
222    {
223        doQuiesce = __quiesce;
224        doStatisticsInsts = __statistics;
225        doCheckpointInsts = __checkpoint;
226    }
227
228    void debugbreak(ExecContext *xc)
229    {
230        debug_break();
231    }
232
233    void switchcpu(ExecContext *xc)
234    {
235        if (SampCPU)
236            SampCPU->switchCPUs();
237    }
238}
239