SConscript revision 9983 
111569Sgabor.dozsa@arm.com# -*- mode:python -*-
211348Sandreas.sandberg@arm.com
311348Sandreas.sandberg@arm.com# Copyright (c) 2006 The Regents of The University of Michigan
411348Sandreas.sandberg@arm.com# All rights reserved.
511348Sandreas.sandberg@arm.com#
611348Sandreas.sandberg@arm.com# Redistribution and use in source and binary forms, with or without
711348Sandreas.sandberg@arm.com# modification, are permitted provided that the following conditions are
811348Sandreas.sandberg@arm.com# met: redistributions of source code must retain the above copyright
911348Sandreas.sandberg@arm.com# notice, this list of conditions and the following disclaimer;
1011348Sandreas.sandberg@arm.com# redistributions in binary form must reproduce the above copyright
1111348Sandreas.sandberg@arm.com# notice, this list of conditions and the following disclaimer in the
1211348Sandreas.sandberg@arm.com# documentation and/or other materials provided with the distribution;
1311348Sandreas.sandberg@arm.com# neither the name of the copyright holders nor the names of its
1411348Sandreas.sandberg@arm.com# contributors may be used to endorse or promote products derived from
1511348Sandreas.sandberg@arm.com# this software without specific prior written permission.
1611348Sandreas.sandberg@arm.com#
1711348Sandreas.sandberg@arm.com# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
1811348Sandreas.sandberg@arm.com# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
1911348Sandreas.sandberg@arm.com# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
2011348Sandreas.sandberg@arm.com# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
2111348Sandreas.sandberg@arm.com# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
2211348Sandreas.sandberg@arm.com# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
2311348Sandreas.sandberg@arm.com# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
2411348Sandreas.sandberg@arm.com# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
2511348Sandreas.sandberg@arm.com# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
2611348Sandreas.sandberg@arm.com# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
2711348Sandreas.sandberg@arm.com# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
2811348Sandreas.sandberg@arm.com#
2911348Sandreas.sandberg@arm.com# Authors: Nathan Binkert
3011348Sandreas.sandberg@arm.com
3111348Sandreas.sandberg@arm.comImport('*')
3211348Sandreas.sandberg@arm.com
3311348Sandreas.sandberg@arm.comSimObject('BaseTLB.py')
3411348Sandreas.sandberg@arm.comSimObject('ClockedObject.py')
3511348Sandreas.sandberg@arm.comSimObject('Root.py')
3611348Sandreas.sandberg@arm.comSimObject('ClockDomain.py')
3711348Sandreas.sandberg@arm.comSimObject('VoltageDomain.py')
3811348Sandreas.sandberg@arm.comSimObject('System.py')
3911348Sandreas.sandberg@arm.com
4011569Sgabor.dozsa@arm.comSource('arguments.cc')
4111569Sgabor.dozsa@arm.comSource('async.cc')
4211569Sgabor.dozsa@arm.comSource('core.cc')
4311348Sandreas.sandberg@arm.comSource('debug.cc')
4411348Sandreas.sandberg@arm.comSource('eventq.cc')
4511348Sandreas.sandberg@arm.comSource('global_event.cc')
4611348Sandreas.sandberg@arm.comSource('init.cc')
4711348Sandreas.sandberg@arm.comSource('main.cc', main=True, skip_lib=True)
4811348Sandreas.sandberg@arm.comSource('root.cc')
4911348Sandreas.sandberg@arm.comSource('serialize.cc')
5011348Sandreas.sandberg@arm.comSource('drain.cc')
5111348Sandreas.sandberg@arm.comSource('sim_events.cc')
5211348Sandreas.sandberg@arm.comSource('sim_object.cc')
5311348Sandreas.sandberg@arm.comSource('simulate.cc')
5411348Sandreas.sandberg@arm.comSource('stat_control.cc')
5511348Sandreas.sandberg@arm.comSource('clock_domain.cc')
5611348Sandreas.sandberg@arm.comSource('voltage_domain.cc')
5711348Sandreas.sandberg@arm.comSource('system.cc')
5811348Sandreas.sandberg@arm.com
5911569Sgabor.dozsa@arm.comif env['TARGET_ISA'] != 'null':
6011569Sgabor.dozsa@arm.com    SimObject('InstTracer.py')
6111569Sgabor.dozsa@arm.com    SimObject('Process.py')
6211569Sgabor.dozsa@arm.com    Source('faults.cc')
6311348Sandreas.sandberg@arm.com    Source('process.cc')
6411348Sandreas.sandberg@arm.com    Source('pseudo_inst.cc')
6511348Sandreas.sandberg@arm.com    Source('syscall_emul.cc')
6611348Sandreas.sandberg@arm.com    Source('tlb.cc')
6711348Sandreas.sandberg@arm.com
6811348Sandreas.sandberg@arm.comDebugFlag('Checkpoint')
6911348Sandreas.sandberg@arm.comDebugFlag('Config')
70DebugFlag('Drain')
71DebugFlag('Event')
72DebugFlag('Fault')
73DebugFlag('Flow')
74DebugFlag('IPI')
75DebugFlag('IPR')
76DebugFlag('Interrupt')
77DebugFlag('Loader')
78DebugFlag('PseudoInst')
79DebugFlag('Stack')
80DebugFlag('SyscallVerbose')
81DebugFlag('TimeSync')
82DebugFlag('TLB')
83DebugFlag('Thread')
84DebugFlag('Timer')
85DebugFlag('VtoPhys')
86DebugFlag('WorkItems')
87DebugFlag('ClockDomain')
88DebugFlag('VoltageDomain')
89