SConscript revision 9793
1# -*- mode:python -*- 2 3# Copyright (c) 2006 The Regents of The University of Michigan 4# All rights reserved. 5# 6# Redistribution and use in source and binary forms, with or without 7# modification, are permitted provided that the following conditions are 8# met: redistributions of source code must retain the above copyright 9# notice, this list of conditions and the following disclaimer; 10# redistributions in binary form must reproduce the above copyright 11# notice, this list of conditions and the following disclaimer in the 12# documentation and/or other materials provided with the distribution; 13# neither the name of the copyright holders nor the names of its 14# contributors may be used to endorse or promote products derived from 15# this software without specific prior written permission. 16# 17# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 20# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 21# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 22# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 23# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 27# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28# 29# Authors: Nathan Binkert 30 31Import('*') 32 33SimObject('BaseTLB.py') 34SimObject('ClockedObject.py') 35SimObject('Root.py') 36SimObject('InstTracer.py') 37SimObject('ClockDomain.py') 38 39Source('arguments.cc') 40Source('async.cc') 41Source('core.cc') 42Source('debug.cc') 43Source('eventq.cc') 44Source('init.cc') 45Source('main.cc', main=True, skip_lib=True) 46Source('root.cc') 47Source('serialize.cc') 48Source('drain.cc') 49Source('sim_events.cc') 50Source('sim_object.cc') 51Source('simulate.cc') 52Source('stat_control.cc') 53Source('syscall_emul.cc') 54Source('clock_domain.cc') 55 56if env['TARGET_ISA'] != 'no': 57 SimObject('Process.py') 58 SimObject('System.py') 59 Source('faults.cc') 60 Source('process.cc') 61 Source('pseudo_inst.cc') 62 Source('system.cc') 63 64if env['TARGET_ISA'] != 'no': 65 Source('tlb.cc') 66 67DebugFlag('Checkpoint') 68DebugFlag('Config') 69DebugFlag('Drain') 70DebugFlag('Event') 71DebugFlag('Fault') 72DebugFlag('Flow') 73DebugFlag('IPI') 74DebugFlag('IPR') 75DebugFlag('Interrupt') 76DebugFlag('Loader') 77DebugFlag('PseudoInst') 78DebugFlag('Stack') 79DebugFlag('SyscallVerbose') 80DebugFlag('TimeSync') 81DebugFlag('TLB') 82DebugFlag('Thread') 83DebugFlag('Timer') 84DebugFlag('VtoPhys') 85DebugFlag('WorkItems') 86DebugFlag('ClockDomain') 87