SConscript revision 9152
110185Seric.vanhensbergen@arm.com# -*- mode:python -*- 210185Seric.vanhensbergen@arm.com 310185Seric.vanhensbergen@arm.com# Copyright (c) 2006 The Regents of The University of Michigan 410185Seric.vanhensbergen@arm.com# All rights reserved. 510185Seric.vanhensbergen@arm.com# 610185Seric.vanhensbergen@arm.com# Redistribution and use in source and binary forms, with or without 710185Seric.vanhensbergen@arm.com# modification, are permitted provided that the following conditions are 810185Seric.vanhensbergen@arm.com# met: redistributions of source code must retain the above copyright 910185Seric.vanhensbergen@arm.com# notice, this list of conditions and the following disclaimer; 1010185Seric.vanhensbergen@arm.com# redistributions in binary form must reproduce the above copyright 1110185Seric.vanhensbergen@arm.com# notice, this list of conditions and the following disclaimer in the 1210185Seric.vanhensbergen@arm.com# documentation and/or other materials provided with the distribution; 1310185Seric.vanhensbergen@arm.com# neither the name of the copyright holders nor the names of its 1410185Seric.vanhensbergen@arm.com# contributors may be used to endorse or promote products derived from 1510185Seric.vanhensbergen@arm.com# this software without specific prior written permission. 1610185Seric.vanhensbergen@arm.com# 1710185Seric.vanhensbergen@arm.com# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1810185Seric.vanhensbergen@arm.com# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1910185Seric.vanhensbergen@arm.com# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 2010185Seric.vanhensbergen@arm.com# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2110185Seric.vanhensbergen@arm.com# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2210185Seric.vanhensbergen@arm.com# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2310185Seric.vanhensbergen@arm.com# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2410185Seric.vanhensbergen@arm.com# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2510185Seric.vanhensbergen@arm.com# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2610185Seric.vanhensbergen@arm.com# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2710185Seric.vanhensbergen@arm.com# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2810185Seric.vanhensbergen@arm.com# 2910185Seric.vanhensbergen@arm.com# Authors: Nathan Binkert 3010185Seric.vanhensbergen@arm.com 3110185Seric.vanhensbergen@arm.comImport('*') 3210185Seric.vanhensbergen@arm.com 3310185Seric.vanhensbergen@arm.comSimObject('BaseTLB.py') 3410185Seric.vanhensbergen@arm.comSimObject('Root.py') 3510185Seric.vanhensbergen@arm.comSimObject('InstTracer.py') 3610185Seric.vanhensbergen@arm.com 3710185Seric.vanhensbergen@arm.comSource('arguments.cc') 3810185Seric.vanhensbergen@arm.comSource('async.cc') 3910185Seric.vanhensbergen@arm.comSource('core.cc') 4010185Seric.vanhensbergen@arm.comSource('debug.cc') 4110185Seric.vanhensbergen@arm.comSource('eventq.cc') 4210185Seric.vanhensbergen@arm.comSource('init.cc') 4310185Seric.vanhensbergen@arm.comSource('main.cc', main=True, skip_lib=True) 4410185Seric.vanhensbergen@arm.comSource('root.cc') 4510185Seric.vanhensbergen@arm.comSource('serialize.cc') 4610185Seric.vanhensbergen@arm.comSource('sim_events.cc') 4710185Seric.vanhensbergen@arm.comSource('sim_object.cc') 4810185Seric.vanhensbergen@arm.comSource('simulate.cc') 4910185Seric.vanhensbergen@arm.comSource('stat_control.cc') 5010185Seric.vanhensbergen@arm.comSource('syscall_emul.cc') 5110185Seric.vanhensbergen@arm.com 5210185Seric.vanhensbergen@arm.comif env['TARGET_ISA'] != 'no': 5310185Seric.vanhensbergen@arm.com SimObject('Process.py') 5410185Seric.vanhensbergen@arm.com SimObject('System.py') 5510185Seric.vanhensbergen@arm.com Source('faults.cc') 5610185Seric.vanhensbergen@arm.com Source('process.cc') 5712157Sandreas.sandberg@arm.com Source('pseudo_inst.cc') 5812157Sandreas.sandberg@arm.com Source('system.cc') 5910185Seric.vanhensbergen@arm.com 6010185Seric.vanhensbergen@arm.comif env['TARGET_ISA'] != 'no': 6110185Seric.vanhensbergen@arm.com Source('tlb.cc') 6210185Seric.vanhensbergen@arm.com 6310185Seric.vanhensbergen@arm.comDebugFlag('Checkpoint') 6410185Seric.vanhensbergen@arm.comDebugFlag('Config') 6510185Seric.vanhensbergen@arm.comDebugFlag('Drain') 6610185Seric.vanhensbergen@arm.comDebugFlag('Event') 6710185Seric.vanhensbergen@arm.comDebugFlag('Fault') 6810185Seric.vanhensbergen@arm.comDebugFlag('Flow') 6910185Seric.vanhensbergen@arm.comDebugFlag('IPI') 7010185Seric.vanhensbergen@arm.comDebugFlag('IPR') 7110185Seric.vanhensbergen@arm.comDebugFlag('Interrupt') 7210185Seric.vanhensbergen@arm.comDebugFlag('Loader') 7310185Seric.vanhensbergen@arm.comDebugFlag('Stack') 7410185Seric.vanhensbergen@arm.comDebugFlag('SyscallVerbose') 7510185Seric.vanhensbergen@arm.comDebugFlag('TimeSync') 7610185Seric.vanhensbergen@arm.comDebugFlag('TLB') 7710185Seric.vanhensbergen@arm.comDebugFlag('Thread') 7810185Seric.vanhensbergen@arm.comDebugFlag('Timer') 7910185Seric.vanhensbergen@arm.comDebugFlag('VtoPhys') 8010185Seric.vanhensbergen@arm.comDebugFlag('WorkItems') 8110185Seric.vanhensbergen@arm.com