xbar.hh revision 9714
112396SRiken.Gohil@arm.com/* 212396SRiken.Gohil@arm.com * Copyright (c) 2011-2013 ARM Limited 312396SRiken.Gohil@arm.com * All rights reserved 412396SRiken.Gohil@arm.com * 512396SRiken.Gohil@arm.com * The license below extends only to copyright in the software and shall 612396SRiken.Gohil@arm.com * not be construed as granting a license to any other intellectual 712396SRiken.Gohil@arm.com * property including but not limited to intellectual property relating 812396SRiken.Gohil@arm.com * to a hardware implementation of the functionality of the software 912396SRiken.Gohil@arm.com * licensed hereunder. You may use the software subject to the license 1012396SRiken.Gohil@arm.com * terms below provided that you ensure that this notice is replicated 1112396SRiken.Gohil@arm.com * unmodified and in its entirety in all distributions of the software, 1212396SRiken.Gohil@arm.com * modified or unmodified, in source code or in binary form. 1312396SRiken.Gohil@arm.com * 1412396SRiken.Gohil@arm.com * Copyright (c) 2002-2005 The Regents of The University of Michigan 1512396SRiken.Gohil@arm.com * All rights reserved. 1612396SRiken.Gohil@arm.com * 1712396SRiken.Gohil@arm.com * Redistribution and use in source and binary forms, with or without 1812396SRiken.Gohil@arm.com * modification, are permitted provided that the following conditions are 1912396SRiken.Gohil@arm.com * met: redistributions of source code must retain the above copyright 2012396SRiken.Gohil@arm.com * notice, this list of conditions and the following disclaimer; 2112396SRiken.Gohil@arm.com * redistributions in binary form must reproduce the above copyright 2212396SRiken.Gohil@arm.com * notice, this list of conditions and the following disclaimer in the 2312396SRiken.Gohil@arm.com * documentation and/or other materials provided with the distribution; 2412396SRiken.Gohil@arm.com * neither the name of the copyright holders nor the names of its 2512396SRiken.Gohil@arm.com * contributors may be used to endorse or promote products derived from 2612396SRiken.Gohil@arm.com * this software without specific prior written permission. 2712396SRiken.Gohil@arm.com * 2812396SRiken.Gohil@arm.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2912396SRiken.Gohil@arm.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 3012396SRiken.Gohil@arm.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 3112396SRiken.Gohil@arm.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 3212396SRiken.Gohil@arm.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 3312396SRiken.Gohil@arm.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3412396SRiken.Gohil@arm.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3512396SRiken.Gohil@arm.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3612396SRiken.Gohil@arm.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3712396SRiken.Gohil@arm.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3812396SRiken.Gohil@arm.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3912396SRiken.Gohil@arm.com * 4012396SRiken.Gohil@arm.com * Authors: Ron Dreslinski 4112396SRiken.Gohil@arm.com * Ali Saidi 4212396SRiken.Gohil@arm.com * Andreas Hansson 4312396SRiken.Gohil@arm.com * William Wang 4412396SRiken.Gohil@arm.com */ 4512396SRiken.Gohil@arm.com 4612396SRiken.Gohil@arm.com/** 4712396SRiken.Gohil@arm.com * @file 4812396SRiken.Gohil@arm.com * Declaration of an abstract bus base class. 4912396SRiken.Gohil@arm.com */ 5012396SRiken.Gohil@arm.com 5112396SRiken.Gohil@arm.com#ifndef __MEM_BUS_HH__ 5212396SRiken.Gohil@arm.com#define __MEM_BUS_HH__ 5312396SRiken.Gohil@arm.com 5412396SRiken.Gohil@arm.com#include <deque> 5512396SRiken.Gohil@arm.com 5612396SRiken.Gohil@arm.com#include "base/addr_range_map.hh" 5712396SRiken.Gohil@arm.com#include "base/types.hh" 5812396SRiken.Gohil@arm.com#include "mem/mem_object.hh" 5912396SRiken.Gohil@arm.com#include "params/BaseBus.hh" 6012396SRiken.Gohil@arm.com#include "sim/stats.hh" 6112396SRiken.Gohil@arm.com 6212396SRiken.Gohil@arm.com/** 6312396SRiken.Gohil@arm.com * The base bus contains the common elements of the non-coherent and 6412396SRiken.Gohil@arm.com * coherent bus. It is an abstract class that does not have any of the 6512396SRiken.Gohil@arm.com * functionality relating to the actual reception and transmission of 6612396SRiken.Gohil@arm.com * packets, as this is left for the subclasses. 6712396SRiken.Gohil@arm.com * 6812396SRiken.Gohil@arm.com * The BaseBus is responsible for the basic flow control (busy or 6912396SRiken.Gohil@arm.com * not), the administration of retries, and the address decoding. 7012396SRiken.Gohil@arm.com */ 7112396SRiken.Gohil@arm.comclass BaseBus : public MemObject 7212396SRiken.Gohil@arm.com{ 7312396SRiken.Gohil@arm.com 7412396SRiken.Gohil@arm.com protected: 7512396SRiken.Gohil@arm.com 7612396SRiken.Gohil@arm.com /** 7712396SRiken.Gohil@arm.com * A bus layer is an internal bus structure with its own flow 7812396SRiken.Gohil@arm.com * control and arbitration. Hence, a single-layer bus mimics a 7912396SRiken.Gohil@arm.com * traditional off-chip tri-state bus (like PCI), where only one 8012396SRiken.Gohil@arm.com * set of wires are shared. For on-chip buses, a good starting 8112396SRiken.Gohil@arm.com * point is to have three layers, for requests, responses, and 8212396SRiken.Gohil@arm.com * snoop responses respectively (snoop requests are instantaneous 8312396SRiken.Gohil@arm.com * and do not need any flow control or arbitration). This case is 8412396SRiken.Gohil@arm.com * similar to AHB and some OCP configurations. 8512396SRiken.Gohil@arm.com * 8612396SRiken.Gohil@arm.com * As a further extensions beyond the three-layer bus, a future 8712396SRiken.Gohil@arm.com * multi-layer bus has with one layer per connected slave port 8812396SRiken.Gohil@arm.com * provides a full or partial crossbar, like AXI, OCP, PCIe etc. 8912396SRiken.Gohil@arm.com * 9012396SRiken.Gohil@arm.com * The template parameter, PortClass, indicates the destination 9112396SRiken.Gohil@arm.com * port type for the bus. The retry list holds either master ports 9212396SRiken.Gohil@arm.com * or slave ports, depending on the direction of the layer. Thus, 9312396SRiken.Gohil@arm.com * a request layer has a retry list containing slave ports, 9412396SRiken.Gohil@arm.com * whereas a response layer holds master ports. 9512396SRiken.Gohil@arm.com */ 9612396SRiken.Gohil@arm.com template <typename PortClass> 9712396SRiken.Gohil@arm.com class Layer : public Drainable 9812396SRiken.Gohil@arm.com { 9912396SRiken.Gohil@arm.com 10012396SRiken.Gohil@arm.com public: 10112396SRiken.Gohil@arm.com 10212396SRiken.Gohil@arm.com /** 10312396SRiken.Gohil@arm.com * Create a bus layer and give it a name. The bus layer uses 10412396SRiken.Gohil@arm.com * the bus an event manager. 10512396SRiken.Gohil@arm.com * 10612396SRiken.Gohil@arm.com * @param _bus the bus this layer belongs to 10712396SRiken.Gohil@arm.com * @param _name the layer's name 10812396SRiken.Gohil@arm.com * @param num_dest_ports number of destination ports 10912396SRiken.Gohil@arm.com */ 11012396SRiken.Gohil@arm.com Layer(BaseBus& _bus, const std::string& _name, uint16_t num_dest_ports); 11112396SRiken.Gohil@arm.com 11212396SRiken.Gohil@arm.com /** 11312396SRiken.Gohil@arm.com * Drain according to the normal semantics, so that the bus 11412396SRiken.Gohil@arm.com * can tell the layer to drain, and pass an event to signal 11512396SRiken.Gohil@arm.com * back when drained. 11612396SRiken.Gohil@arm.com * 11712396SRiken.Gohil@arm.com * @param de drain event to call once drained 11812396SRiken.Gohil@arm.com * 11912396SRiken.Gohil@arm.com * @return 1 if busy or waiting to retry, or 0 if idle 12012396SRiken.Gohil@arm.com */ 12112396SRiken.Gohil@arm.com unsigned int drain(DrainManager *dm); 12212396SRiken.Gohil@arm.com 12312396SRiken.Gohil@arm.com /** 12412396SRiken.Gohil@arm.com * Get the bus layer's name 12512396SRiken.Gohil@arm.com */ 12612396SRiken.Gohil@arm.com const std::string name() const { return bus.name() + _name; } 12712396SRiken.Gohil@arm.com 12812396SRiken.Gohil@arm.com 12912396SRiken.Gohil@arm.com /** 13012396SRiken.Gohil@arm.com * Determine if the bus layer accepts a packet from a specific 13112396SRiken.Gohil@arm.com * port. If not, the port in question is also added to the 13212396SRiken.Gohil@arm.com * retry list. In either case the state of the layer is 13312396SRiken.Gohil@arm.com * updated accordingly. 13412396SRiken.Gohil@arm.com * 13512396SRiken.Gohil@arm.com * @param port Source port presenting the packet 13612396SRiken.Gohil@arm.com * @param dest_port_id Destination port id 13712396SRiken.Gohil@arm.com * 13812396SRiken.Gohil@arm.com * @return True if the bus layer accepts the packet 13912396SRiken.Gohil@arm.com */ 14012396SRiken.Gohil@arm.com bool tryTiming(PortClass* port, PortID dest_port_id); 14112396SRiken.Gohil@arm.com 14212396SRiken.Gohil@arm.com /** 14312396SRiken.Gohil@arm.com * Deal with a destination port accepting a packet by potentially 14412396SRiken.Gohil@arm.com * removing the source port from the retry list (if retrying) and 14512396SRiken.Gohil@arm.com * occupying the bus layer accordingly. 14612396SRiken.Gohil@arm.com * 14712396SRiken.Gohil@arm.com * @param busy_time Time to spend as a result of a successful send 14812396SRiken.Gohil@arm.com */ 14912396SRiken.Gohil@arm.com void succeededTiming(Tick busy_time); 15012396SRiken.Gohil@arm.com 15112396SRiken.Gohil@arm.com /** 15212396SRiken.Gohil@arm.com * Deal with a destination port not accepting a packet by 15312396SRiken.Gohil@arm.com * potentially adding the source port to the retry list (if 15412396SRiken.Gohil@arm.com * not already at the front) and occupying the bus layer 15512396SRiken.Gohil@arm.com * accordingly. 15612396SRiken.Gohil@arm.com * 15712396SRiken.Gohil@arm.com * @param src_port Source port 15812396SRiken.Gohil@arm.com * @param dest_port_id Destination port id 15912396SRiken.Gohil@arm.com * @param busy_time Time to spend as a result of a failed send 16012396SRiken.Gohil@arm.com */ 16112396SRiken.Gohil@arm.com void failedTiming(PortClass* src_port, PortID dest_port_id, 16212396SRiken.Gohil@arm.com Tick busy_time); 16312396SRiken.Gohil@arm.com 16412396SRiken.Gohil@arm.com /** Occupy the bus layer until until */ 16512396SRiken.Gohil@arm.com void occupyLayer(Tick until); 16612396SRiken.Gohil@arm.com 16712396SRiken.Gohil@arm.com /** 16812396SRiken.Gohil@arm.com * Send a retry to the port at the head of waitingForLayer. The 16912396SRiken.Gohil@arm.com * caller must ensure that the list is not empty. 17012396SRiken.Gohil@arm.com */ 17112396SRiken.Gohil@arm.com void retryWaiting(); 17212396SRiken.Gohil@arm.com 17312396SRiken.Gohil@arm.com /** 17412396SRiken.Gohil@arm.com * Handle a retry from a neighbouring module. This wraps 17512396SRiken.Gohil@arm.com * retryWaiting by verifying that there are ports waiting 17612396SRiken.Gohil@arm.com * before calling retryWaiting. 17712396SRiken.Gohil@arm.com * 17812396SRiken.Gohil@arm.com * @param port_id Id of the port that received the retry 17912396SRiken.Gohil@arm.com */ 18012396SRiken.Gohil@arm.com void recvRetry(PortID port_id); 18112396SRiken.Gohil@arm.com 18212396SRiken.Gohil@arm.com /** 18312396SRiken.Gohil@arm.com * Register stats for the layer 18412396SRiken.Gohil@arm.com */ 18512396SRiken.Gohil@arm.com void regStats(); 18612396SRiken.Gohil@arm.com 18712396SRiken.Gohil@arm.com private: 18812396SRiken.Gohil@arm.com 18912396SRiken.Gohil@arm.com /** The bus this layer is a part of. */ 19012396SRiken.Gohil@arm.com BaseBus& bus; 19112396SRiken.Gohil@arm.com 19212396SRiken.Gohil@arm.com /** A name for this layer. */ 19312396SRiken.Gohil@arm.com std::string _name; 19412396SRiken.Gohil@arm.com 19512396SRiken.Gohil@arm.com /** 19612396SRiken.Gohil@arm.com * We declare an enum to track the state of the bus layer. The 19712396SRiken.Gohil@arm.com * starting point is an idle state where the bus layer is 19812396SRiken.Gohil@arm.com * waiting for a packet to arrive. Upon arrival, the bus layer 19912396SRiken.Gohil@arm.com * transitions to the busy state, where it remains either 20012396SRiken.Gohil@arm.com * until the packet transfer is done, or the header time is 20112396SRiken.Gohil@arm.com * spent. Once the bus layer leaves the busy state, it can 20212396SRiken.Gohil@arm.com * either go back to idle, if no packets have arrived while it 20312396SRiken.Gohil@arm.com * was busy, or the bus layer goes on to retry the first port 20412396SRiken.Gohil@arm.com * in waitingForLayer. A similar transition takes place from 20512396SRiken.Gohil@arm.com * idle to retry if the bus layer receives a retry from one of 20612396SRiken.Gohil@arm.com * its connected ports. The retry state lasts until the port 20712396SRiken.Gohil@arm.com * in questions calls sendTiming and returns control to the 20812396SRiken.Gohil@arm.com * bus layer, or goes to a busy state if the port does not 20912396SRiken.Gohil@arm.com * immediately react to the retry by calling sendTiming. 21012396SRiken.Gohil@arm.com */ 21112396SRiken.Gohil@arm.com enum State { IDLE, BUSY, RETRY }; 21212396SRiken.Gohil@arm.com 21312396SRiken.Gohil@arm.com /** track the state of the bus layer */ 214 State state; 215 216 /** manager to signal when drained */ 217 DrainManager *drainManager; 218 219 /** 220 * A deque of ports that retry should be called on because 221 * the original send was delayed due to a busy layer. 222 */ 223 std::deque<PortClass*> waitingForLayer; 224 225 /** 226 * Port that we are currently in the process of telling to 227 * retry a previously failed attempt to perform a timing 228 * transaction. This is a valid port when in the retry state, 229 * and NULL when in busy or idle. 230 */ 231 PortClass* retryingPort; 232 233 /** 234 * A vector that tracks who is waiting for the retry when 235 * receiving it from a peer. The vector indices are port ids 236 * of the outgoing ports for the specific layer. The values 237 * are the incoming ports that tried to forward something to 238 * the outgoing port, but was told to wait and is now waiting 239 * for a retry. If no port is waiting NULL is stored on the 240 * location in question. 241 */ 242 std::vector<PortClass*> waitingForPeer; 243 244 /** 245 * Release the bus layer after being occupied and return to an 246 * idle state where we proceed to send a retry to any 247 * potential waiting port, or drain if asked to do so. 248 */ 249 void releaseLayer(); 250 251 /** event used to schedule a release of the layer */ 252 EventWrapper<Layer, &Layer::releaseLayer> releaseEvent; 253 254 /** 255 * Stats for occupancy and utilization. These stats capture 256 * the time the bus spends in the busy state and are thus only 257 * relevant when the memory system is in timing mode. 258 */ 259 Stats::Scalar occupancy; 260 Stats::Formula utilization; 261 262 }; 263 264 /** cycles of overhead per transaction */ 265 const Cycles headerCycles; 266 /** the width of the bus in bytes */ 267 const uint32_t width; 268 269 typedef AddrRangeMap<PortID>::iterator PortMapIter; 270 typedef AddrRangeMap<PortID>::const_iterator PortMapConstIter; 271 AddrRangeMap<PortID> portMap; 272 273 /** all contigous ranges seen by this bus */ 274 AddrRangeList busRanges; 275 276 AddrRange defaultRange; 277 278 /** 279 * Function called by the port when the bus is recieving a range change. 280 * 281 * @param master_port_id id of the port that received the change 282 */ 283 void recvRangeChange(PortID master_port_id); 284 285 /** Find which port connected to this bus (if any) should be given a packet 286 * with this address. 287 * @param addr Address to find port for. 288 * @return id of port that the packet should be sent out of. 289 */ 290 PortID findPort(Addr addr); 291 292 // Cache for the findPort function storing recently used ports from portMap 293 struct PortCache { 294 bool valid; 295 PortID id; 296 AddrRange range; 297 }; 298 299 PortCache portCache[3]; 300 301 // Checks the cache and returns the id of the port that has the requested 302 // address within its range 303 inline PortID checkPortCache(Addr addr) const { 304 if (portCache[0].valid && portCache[0].range.contains(addr)) { 305 return portCache[0].id; 306 } 307 if (portCache[1].valid && portCache[1].range.contains(addr)) { 308 return portCache[1].id; 309 } 310 if (portCache[2].valid && portCache[2].range.contains(addr)) { 311 return portCache[2].id; 312 } 313 314 return InvalidPortID; 315 } 316 317 // Clears the earliest entry of the cache and inserts a new port entry 318 inline void updatePortCache(short id, const AddrRange& range) { 319 portCache[2].valid = portCache[1].valid; 320 portCache[2].id = portCache[1].id; 321 portCache[2].range = portCache[1].range; 322 323 portCache[1].valid = portCache[0].valid; 324 portCache[1].id = portCache[0].id; 325 portCache[1].range = portCache[0].range; 326 327 portCache[0].valid = true; 328 portCache[0].id = id; 329 portCache[0].range = range; 330 } 331 332 // Clears the cache. Needs to be called in constructor. 333 inline void clearPortCache() { 334 portCache[2].valid = false; 335 portCache[1].valid = false; 336 portCache[0].valid = false; 337 } 338 339 /** 340 * Return the address ranges the bus is responsible for. 341 * 342 * @return a list of non-overlapping address ranges 343 */ 344 AddrRangeList getAddrRanges() const; 345 346 /** 347 * Calculate the timing parameters for the packet. Updates the 348 * busFirstWordDelay and busLastWordDelay fields of the packet 349 * object with the relative number of ticks required to transmit 350 * the header and the first word, and the last word, respectively. 351 */ 352 void calcPacketTiming(PacketPtr pkt); 353 354 /** 355 * Ask everyone on the bus what their size is and determine the 356 * bus size as either the maximum, or if no device specifies a 357 * block size return the default. 358 * 359 * @return the max of all the sizes or the default if none is set 360 */ 361 unsigned deviceBlockSize() const; 362 363 /** 364 * Remember for each of the master ports of the bus if we got an 365 * address range from the connected slave. For convenience, also 366 * keep track of if we got ranges from all the slave modules or 367 * not. 368 */ 369 std::vector<bool> gotAddrRanges; 370 bool gotAllAddrRanges; 371 372 /** The master and slave ports of the bus */ 373 std::vector<SlavePort*> slavePorts; 374 std::vector<MasterPort*> masterPorts; 375 376 /** Convenience typedefs. */ 377 typedef std::vector<SlavePort*>::iterator SlavePortIter; 378 typedef std::vector<MasterPort*>::iterator MasterPortIter; 379 typedef std::vector<SlavePort*>::const_iterator SlavePortConstIter; 380 typedef std::vector<MasterPort*>::const_iterator MasterPortConstIter; 381 382 /** Port that handles requests that don't match any of the interfaces.*/ 383 PortID defaultPortID; 384 385 /** If true, use address range provided by default device. Any 386 address not handled by another port and not in default device's 387 range will cause a fatal error. If false, just send all 388 addresses not handled by another port to default device. */ 389 const bool useDefaultRange; 390 391 uint32_t blockSize; 392 393 BaseBus(const BaseBusParams *p); 394 395 virtual ~BaseBus(); 396 397 /** 398 * Stats for transaction distribution and data passing through the 399 * bus. The transaction distribution is globally counting 400 * different types of commands. The packet count and total packet 401 * size are two-dimensional vectors that are indexed by the bus 402 * slave port and master port id (thus the neighbouring master and 403 * neighbouring slave), summing up both directions (request and 404 * response). 405 */ 406 Stats::Formula throughput; 407 Stats::Vector transDist; 408 Stats::Vector2d pktCount; 409 Stats::Vector2d totPktSize; 410 411 public: 412 413 virtual void init(); 414 415 /** A function used to return the port associated with this bus object. */ 416 BaseMasterPort& getMasterPort(const std::string& if_name, 417 PortID idx = InvalidPortID); 418 BaseSlavePort& getSlavePort(const std::string& if_name, 419 PortID idx = InvalidPortID); 420 421 virtual unsigned int drain(DrainManager *dm) = 0; 422 423 virtual void regStats(); 424 425}; 426 427#endif //__MEM_BUS_HH__ 428