xbar.hh revision 9714
12086SN/A/* 22086SN/A * Copyright (c) 2011-2013 ARM Limited 35268Sksewell@umich.edu * All rights reserved 42086SN/A * 52086SN/A * The license below extends only to copyright in the software and shall 62086SN/A * not be construed as granting a license to any other intellectual 72086SN/A * property including but not limited to intellectual property relating 82086SN/A * to a hardware implementation of the functionality of the software 92086SN/A * licensed hereunder. You may use the software subject to the license 102086SN/A * terms below provided that you ensure that this notice is replicated 112086SN/A * unmodified and in its entirety in all distributions of the software, 122086SN/A * modified or unmodified, in source code or in binary form. 132086SN/A * 142086SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 152086SN/A * All rights reserved. 162086SN/A * 172086SN/A * Redistribution and use in source and binary forms, with or without 182086SN/A * modification, are permitted provided that the following conditions are 192086SN/A * met: redistributions of source code must retain the above copyright 202086SN/A * notice, this list of conditions and the following disclaimer; 212086SN/A * redistributions in binary form must reproduce the above copyright 222086SN/A * notice, this list of conditions and the following disclaimer in the 232086SN/A * documentation and/or other materials provided with the distribution; 242086SN/A * neither the name of the copyright holders nor the names of its 252086SN/A * contributors may be used to endorse or promote products derived from 262086SN/A * this software without specific prior written permission. 272086SN/A * 282665Ssaidi@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292665Ssaidi@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302665Ssaidi@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312686Sksewell@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322086SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 334202Sbinkertn@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342086SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 354202Sbinkertn@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 368775Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 379022Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 388758Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 394202Sbinkertn@umich.edu * 408775Sgblack@eecs.umich.edu * Authors: Ron Dreslinski 418745Sgblack@eecs.umich.edu * Ali Saidi 426313Sgblack@eecs.umich.edu * Andreas Hansson 438775Sgblack@eecs.umich.edu * William Wang 448775Sgblack@eecs.umich.edu */ 458775Sgblack@eecs.umich.edu 468758Sgblack@eecs.umich.edu/** 478775Sgblack@eecs.umich.edu * @file 488758Sgblack@eecs.umich.edu * Declaration of an abstract bus base class. 498775Sgblack@eecs.umich.edu */ 508775Sgblack@eecs.umich.edu 514997Sgblack@eecs.umich.edu#ifndef __MEM_BUS_HH__ 524202Sbinkertn@umich.edu#define __MEM_BUS_HH__ 538758Sgblack@eecs.umich.edu 544997Sgblack@eecs.umich.edu#include <deque> 558745Sgblack@eecs.umich.edu 569384SAndreas.Sandberg@arm.com#include "base/addr_range_map.hh" 578775Sgblack@eecs.umich.edu#include "base/types.hh" 584997Sgblack@eecs.umich.edu#include "mem/mem_object.hh" 595192Ssaidi@eecs.umich.edu#include "params/BaseBus.hh" 608775Sgblack@eecs.umich.edu#include "sim/stats.hh" 612086SN/A 6210196SCurtis.Dunham@arm.com/** 63 * The base bus contains the common elements of the non-coherent and 64 * coherent bus. It is an abstract class that does not have any of the 65 * functionality relating to the actual reception and transmission of 66 * packets, as this is left for the subclasses. 67 * 68 * The BaseBus is responsible for the basic flow control (busy or 69 * not), the administration of retries, and the address decoding. 70 */ 71class BaseBus : public MemObject 72{ 73 74 protected: 75 76 /** 77 * A bus layer is an internal bus structure with its own flow 78 * control and arbitration. Hence, a single-layer bus mimics a 79 * traditional off-chip tri-state bus (like PCI), where only one 80 * set of wires are shared. For on-chip buses, a good starting 81 * point is to have three layers, for requests, responses, and 82 * snoop responses respectively (snoop requests are instantaneous 83 * and do not need any flow control or arbitration). This case is 84 * similar to AHB and some OCP configurations. 85 * 86 * As a further extensions beyond the three-layer bus, a future 87 * multi-layer bus has with one layer per connected slave port 88 * provides a full or partial crossbar, like AXI, OCP, PCIe etc. 89 * 90 * The template parameter, PortClass, indicates the destination 91 * port type for the bus. The retry list holds either master ports 92 * or slave ports, depending on the direction of the layer. Thus, 93 * a request layer has a retry list containing slave ports, 94 * whereas a response layer holds master ports. 95 */ 96 template <typename PortClass> 97 class Layer : public Drainable 98 { 99 100 public: 101 102 /** 103 * Create a bus layer and give it a name. The bus layer uses 104 * the bus an event manager. 105 * 106 * @param _bus the bus this layer belongs to 107 * @param _name the layer's name 108 * @param num_dest_ports number of destination ports 109 */ 110 Layer(BaseBus& _bus, const std::string& _name, uint16_t num_dest_ports); 111 112 /** 113 * Drain according to the normal semantics, so that the bus 114 * can tell the layer to drain, and pass an event to signal 115 * back when drained. 116 * 117 * @param de drain event to call once drained 118 * 119 * @return 1 if busy or waiting to retry, or 0 if idle 120 */ 121 unsigned int drain(DrainManager *dm); 122 123 /** 124 * Get the bus layer's name 125 */ 126 const std::string name() const { return bus.name() + _name; } 127 128 129 /** 130 * Determine if the bus layer accepts a packet from a specific 131 * port. If not, the port in question is also added to the 132 * retry list. In either case the state of the layer is 133 * updated accordingly. 134 * 135 * @param port Source port presenting the packet 136 * @param dest_port_id Destination port id 137 * 138 * @return True if the bus layer accepts the packet 139 */ 140 bool tryTiming(PortClass* port, PortID dest_port_id); 141 142 /** 143 * Deal with a destination port accepting a packet by potentially 144 * removing the source port from the retry list (if retrying) and 145 * occupying the bus layer accordingly. 146 * 147 * @param busy_time Time to spend as a result of a successful send 148 */ 149 void succeededTiming(Tick busy_time); 150 151 /** 152 * Deal with a destination port not accepting a packet by 153 * potentially adding the source port to the retry list (if 154 * not already at the front) and occupying the bus layer 155 * accordingly. 156 * 157 * @param src_port Source port 158 * @param dest_port_id Destination port id 159 * @param busy_time Time to spend as a result of a failed send 160 */ 161 void failedTiming(PortClass* src_port, PortID dest_port_id, 162 Tick busy_time); 163 164 /** Occupy the bus layer until until */ 165 void occupyLayer(Tick until); 166 167 /** 168 * Send a retry to the port at the head of waitingForLayer. The 169 * caller must ensure that the list is not empty. 170 */ 171 void retryWaiting(); 172 173 /** 174 * Handle a retry from a neighbouring module. This wraps 175 * retryWaiting by verifying that there are ports waiting 176 * before calling retryWaiting. 177 * 178 * @param port_id Id of the port that received the retry 179 */ 180 void recvRetry(PortID port_id); 181 182 /** 183 * Register stats for the layer 184 */ 185 void regStats(); 186 187 private: 188 189 /** The bus this layer is a part of. */ 190 BaseBus& bus; 191 192 /** A name for this layer. */ 193 std::string _name; 194 195 /** 196 * We declare an enum to track the state of the bus layer. The 197 * starting point is an idle state where the bus layer is 198 * waiting for a packet to arrive. Upon arrival, the bus layer 199 * transitions to the busy state, where it remains either 200 * until the packet transfer is done, or the header time is 201 * spent. Once the bus layer leaves the busy state, it can 202 * either go back to idle, if no packets have arrived while it 203 * was busy, or the bus layer goes on to retry the first port 204 * in waitingForLayer. A similar transition takes place from 205 * idle to retry if the bus layer receives a retry from one of 206 * its connected ports. The retry state lasts until the port 207 * in questions calls sendTiming and returns control to the 208 * bus layer, or goes to a busy state if the port does not 209 * immediately react to the retry by calling sendTiming. 210 */ 211 enum State { IDLE, BUSY, RETRY }; 212 213 /** track the state of the bus layer */ 214 State state; 215 216 /** manager to signal when drained */ 217 DrainManager *drainManager; 218 219 /** 220 * A deque of ports that retry should be called on because 221 * the original send was delayed due to a busy layer. 222 */ 223 std::deque<PortClass*> waitingForLayer; 224 225 /** 226 * Port that we are currently in the process of telling to 227 * retry a previously failed attempt to perform a timing 228 * transaction. This is a valid port when in the retry state, 229 * and NULL when in busy or idle. 230 */ 231 PortClass* retryingPort; 232 233 /** 234 * A vector that tracks who is waiting for the retry when 235 * receiving it from a peer. The vector indices are port ids 236 * of the outgoing ports for the specific layer. The values 237 * are the incoming ports that tried to forward something to 238 * the outgoing port, but was told to wait and is now waiting 239 * for a retry. If no port is waiting NULL is stored on the 240 * location in question. 241 */ 242 std::vector<PortClass*> waitingForPeer; 243 244 /** 245 * Release the bus layer after being occupied and return to an 246 * idle state where we proceed to send a retry to any 247 * potential waiting port, or drain if asked to do so. 248 */ 249 void releaseLayer(); 250 251 /** event used to schedule a release of the layer */ 252 EventWrapper<Layer, &Layer::releaseLayer> releaseEvent; 253 254 /** 255 * Stats for occupancy and utilization. These stats capture 256 * the time the bus spends in the busy state and are thus only 257 * relevant when the memory system is in timing mode. 258 */ 259 Stats::Scalar occupancy; 260 Stats::Formula utilization; 261 262 }; 263 264 /** cycles of overhead per transaction */ 265 const Cycles headerCycles; 266 /** the width of the bus in bytes */ 267 const uint32_t width; 268 269 typedef AddrRangeMap<PortID>::iterator PortMapIter; 270 typedef AddrRangeMap<PortID>::const_iterator PortMapConstIter; 271 AddrRangeMap<PortID> portMap; 272 273 /** all contigous ranges seen by this bus */ 274 AddrRangeList busRanges; 275 276 AddrRange defaultRange; 277 278 /** 279 * Function called by the port when the bus is recieving a range change. 280 * 281 * @param master_port_id id of the port that received the change 282 */ 283 void recvRangeChange(PortID master_port_id); 284 285 /** Find which port connected to this bus (if any) should be given a packet 286 * with this address. 287 * @param addr Address to find port for. 288 * @return id of port that the packet should be sent out of. 289 */ 290 PortID findPort(Addr addr); 291 292 // Cache for the findPort function storing recently used ports from portMap 293 struct PortCache { 294 bool valid; 295 PortID id; 296 AddrRange range; 297 }; 298 299 PortCache portCache[3]; 300 301 // Checks the cache and returns the id of the port that has the requested 302 // address within its range 303 inline PortID checkPortCache(Addr addr) const { 304 if (portCache[0].valid && portCache[0].range.contains(addr)) { 305 return portCache[0].id; 306 } 307 if (portCache[1].valid && portCache[1].range.contains(addr)) { 308 return portCache[1].id; 309 } 310 if (portCache[2].valid && portCache[2].range.contains(addr)) { 311 return portCache[2].id; 312 } 313 314 return InvalidPortID; 315 } 316 317 // Clears the earliest entry of the cache and inserts a new port entry 318 inline void updatePortCache(short id, const AddrRange& range) { 319 portCache[2].valid = portCache[1].valid; 320 portCache[2].id = portCache[1].id; 321 portCache[2].range = portCache[1].range; 322 323 portCache[1].valid = portCache[0].valid; 324 portCache[1].id = portCache[0].id; 325 portCache[1].range = portCache[0].range; 326 327 portCache[0].valid = true; 328 portCache[0].id = id; 329 portCache[0].range = range; 330 } 331 332 // Clears the cache. Needs to be called in constructor. 333 inline void clearPortCache() { 334 portCache[2].valid = false; 335 portCache[1].valid = false; 336 portCache[0].valid = false; 337 } 338 339 /** 340 * Return the address ranges the bus is responsible for. 341 * 342 * @return a list of non-overlapping address ranges 343 */ 344 AddrRangeList getAddrRanges() const; 345 346 /** 347 * Calculate the timing parameters for the packet. Updates the 348 * busFirstWordDelay and busLastWordDelay fields of the packet 349 * object with the relative number of ticks required to transmit 350 * the header and the first word, and the last word, respectively. 351 */ 352 void calcPacketTiming(PacketPtr pkt); 353 354 /** 355 * Ask everyone on the bus what their size is and determine the 356 * bus size as either the maximum, or if no device specifies a 357 * block size return the default. 358 * 359 * @return the max of all the sizes or the default if none is set 360 */ 361 unsigned deviceBlockSize() const; 362 363 /** 364 * Remember for each of the master ports of the bus if we got an 365 * address range from the connected slave. For convenience, also 366 * keep track of if we got ranges from all the slave modules or 367 * not. 368 */ 369 std::vector<bool> gotAddrRanges; 370 bool gotAllAddrRanges; 371 372 /** The master and slave ports of the bus */ 373 std::vector<SlavePort*> slavePorts; 374 std::vector<MasterPort*> masterPorts; 375 376 /** Convenience typedefs. */ 377 typedef std::vector<SlavePort*>::iterator SlavePortIter; 378 typedef std::vector<MasterPort*>::iterator MasterPortIter; 379 typedef std::vector<SlavePort*>::const_iterator SlavePortConstIter; 380 typedef std::vector<MasterPort*>::const_iterator MasterPortConstIter; 381 382 /** Port that handles requests that don't match any of the interfaces.*/ 383 PortID defaultPortID; 384 385 /** If true, use address range provided by default device. Any 386 address not handled by another port and not in default device's 387 range will cause a fatal error. If false, just send all 388 addresses not handled by another port to default device. */ 389 const bool useDefaultRange; 390 391 uint32_t blockSize; 392 393 BaseBus(const BaseBusParams *p); 394 395 virtual ~BaseBus(); 396 397 /** 398 * Stats for transaction distribution and data passing through the 399 * bus. The transaction distribution is globally counting 400 * different types of commands. The packet count and total packet 401 * size are two-dimensional vectors that are indexed by the bus 402 * slave port and master port id (thus the neighbouring master and 403 * neighbouring slave), summing up both directions (request and 404 * response). 405 */ 406 Stats::Formula throughput; 407 Stats::Vector transDist; 408 Stats::Vector2d pktCount; 409 Stats::Vector2d totPktSize; 410 411 public: 412 413 virtual void init(); 414 415 /** A function used to return the port associated with this bus object. */ 416 BaseMasterPort& getMasterPort(const std::string& if_name, 417 PortID idx = InvalidPortID); 418 BaseSlavePort& getSlavePort(const std::string& if_name, 419 PortID idx = InvalidPortID); 420 421 virtual unsigned int drain(DrainManager *dm) = 0; 422 423 virtual void regStats(); 424 425}; 426 427#endif //__MEM_BUS_HH__ 428