RubyPort.hh revision 8914:8c3bd7bea667 
1/*
2 * Copyright (c) 2009 Advanced Micro Devices, Inc.
3 * Copyright (c) 2011 Mark D. Hill and David A. Wood
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;
10 * redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution;
13 * neither the name of the copyright holders nor the names of its
14 * contributors may be used to endorse or promote products derived from
15 * this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 */
29
30#ifndef __MEM_RUBY_SYSTEM_RUBYPORT_HH__
31#define __MEM_RUBY_SYSTEM_RUBYPORT_HH__
32
33#include <cassert>
34#include <string>
35
36#include "mem/protocol/RequestStatus.hh"
37#include "mem/ruby/system/System.hh"
38#include "mem/mem_object.hh"
39#include "mem/physical.hh"
40#include "mem/tport.hh"
41#include "params/RubyPort.hh"
42
43class MessageBuffer;
44class AbstractController;
45
46class RubyPort : public MemObject
47{
48  public:
49    class M5Port : public QueuedPort
50    {
51      private:
52
53        PacketQueue queue;
54        RubyPort *ruby_port;
55        RubySystem* ruby_system;
56        bool _onRetryList;
57        bool access_phys_mem;
58
59      public:
60        M5Port(const std::string &_name, RubyPort *_port,
61               RubySystem*_system, bool _access_phys_mem);
62        bool sendNextCycle(PacketPtr pkt);
63        void hitCallback(PacketPtr pkt);
64        void evictionCallback(const Address& address);
65        unsigned deviceBlockSize() const;
66
67        bool onRetryList()
68        { return _onRetryList; }
69
70        void onRetryList(bool newVal)
71        { _onRetryList = newVal; }
72
73      protected:
74        virtual bool recvTiming(PacketPtr pkt);
75        virtual Tick recvAtomic(PacketPtr pkt);
76        virtual void recvFunctional(PacketPtr pkt);
77
78      private:
79        bool isPhysMemAddress(Addr addr);
80        bool doFunctionalRead(PacketPtr pkt);
81        bool doFunctionalWrite(PacketPtr pkt);
82    };
83
84    friend class M5Port;
85
86    class PioPort : public QueuedPort
87    {
88      private:
89
90        PacketQueue queue;
91
92        RubyPort *ruby_port;
93
94      public:
95        PioPort(const std::string &_name, RubyPort *_port);
96        bool sendNextCycle(PacketPtr pkt);
97
98      protected:
99        virtual bool recvTiming(PacketPtr pkt);
100        virtual Tick recvAtomic(PacketPtr pkt);
101        virtual void recvFunctional(PacketPtr pkt) { }
102    };
103
104    friend class PioPort;
105
106    struct SenderState : public Packet::SenderState
107    {
108        M5Port* port;
109        Packet::SenderState *saved;
110
111        SenderState(M5Port* _port, Packet::SenderState *sender_state = NULL)
112            : port(_port), saved(sender_state)
113        {}
114    };
115
116    typedef RubyPortParams Params;
117    RubyPort(const Params *p);
118    virtual ~RubyPort() {}
119
120    void init();
121
122    Port *getPort(const std::string &if_name, int idx);
123
124    virtual RequestStatus makeRequest(PacketPtr pkt) = 0;
125    virtual int outstandingCount() const = 0;
126    virtual bool isDeadlockEventScheduled() const = 0;
127    virtual void descheduleDeadlockEvent() = 0;
128
129    //
130    // Called by the controller to give the sequencer a pointer.
131    // A pointer to the controller is needed for atomic support.
132    //
133    void setController(AbstractController* _cntrl) { m_controller = _cntrl; }
134    int getId() { return m_version; }
135    unsigned int drain(Event *de);
136
137  protected:
138    const std::string m_name;
139    void ruby_hit_callback(PacketPtr pkt);
140    void testDrainComplete();
141    void ruby_eviction_callback(const Address& address);
142
143    int m_version;
144    AbstractController* m_controller;
145    MessageBuffer* m_mandatory_q_ptr;
146    PioPort pio_port;
147    bool m_usingRubyTester;
148
149  private:
150    void addToRetryList(M5Port * port)
151    {
152        if (!port->onRetryList()) {
153            port->onRetryList(true);
154            retryList.push_back(port);
155            waitingOnSequencer = true;
156        }
157    }
158
159    unsigned int getDrainCount(Event *de);
160
161    uint16_t m_port_id;
162    uint64_t m_request_cnt;
163
164    PioPort physMemPort;
165
166    /*! Vector of CPU Port attached to this Ruby port. */
167    typedef std::vector<M5Port*>::iterator CpuPortIter;
168    std::vector<M5Port*> cpu_ports;
169
170    Event *drainEvent;
171
172    PhysicalMemory* physmem;
173    RubySystem* ruby_system;
174
175    //
176    // Based on similar code in the M5 bus.  Stores pointers to those ports
177    // that should be called when the Sequencer becomes available after a stall.
178    //
179    std::list<M5Port*> retryList;
180
181    bool waitingOnSequencer;
182    bool access_phys_mem;
183};
184
185#endif // __MEM_RUBY_SYSTEM_RUBYPORT_HH__
186