RubyPort.hh revision 8686:71ac9dda5432 
1/*
2 * Copyright (c) 2009 Advanced Micro Devices, Inc.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#ifndef __MEM_RUBY_SYSTEM_RUBYPORT_HH__
30#define __MEM_RUBY_SYSTEM_RUBYPORT_HH__
31
32#include <cassert>
33#include <string>
34
35#include "mem/protocol/RequestStatus.hh"
36#include "mem/ruby/slicc_interface/RubyRequest.hh"
37#include "mem/ruby/system/System.hh"
38#include "mem/mem_object.hh"
39#include "mem/physical.hh"
40#include "mem/tport.hh"
41#include "params/RubyPort.hh"
42
43class MessageBuffer;
44class AbstractController;
45
46class RubyPort : public MemObject
47{
48  public:
49    class M5Port : public SimpleTimingPort
50    {
51      private:
52        RubyPort *ruby_port;
53        RubySystem* ruby_system;
54        bool _onRetryList;
55        bool access_phys_mem;
56
57      public:
58        M5Port(const std::string &_name, RubyPort *_port,
59               RubySystem*_system, bool _access_phys_mem);
60        bool sendTiming(PacketPtr pkt);
61        void hitCallback(PacketPtr pkt);
62        unsigned deviceBlockSize() const;
63
64        bool onRetryList()
65        { return _onRetryList; }
66
67        void onRetryList(bool newVal)
68        { _onRetryList = newVal; }
69
70      protected:
71        virtual bool recvTiming(PacketPtr pkt);
72        virtual Tick recvAtomic(PacketPtr pkt);
73        virtual void recvFunctional(PacketPtr pkt);
74
75      private:
76        bool isPhysMemAddress(Addr addr);
77        bool doFunctionalRead(PacketPtr pkt);
78        bool doFunctionalWrite(PacketPtr pkt);
79    };
80
81    friend class M5Port;
82
83    class PioPort : public SimpleTimingPort
84    {
85      private:
86        RubyPort *ruby_port;
87
88      public:
89        PioPort(const std::string &_name, RubyPort *_port);
90        bool sendTiming(PacketPtr pkt);
91
92      protected:
93        virtual bool recvTiming(PacketPtr pkt);
94        virtual Tick recvAtomic(PacketPtr pkt);
95    };
96
97    friend class PioPort;
98
99    struct SenderState : public Packet::SenderState
100    {
101        M5Port* port;
102        Packet::SenderState *saved;
103
104        SenderState(M5Port* _port, Packet::SenderState *sender_state = NULL)
105            : port(_port), saved(sender_state)
106        {}
107    };
108
109    typedef RubyPortParams Params;
110    RubyPort(const Params *p);
111    virtual ~RubyPort() {}
112
113    void init();
114
115    Port *getPort(const std::string &if_name, int idx);
116
117    virtual RequestStatus makeRequest(PacketPtr pkt) = 0;
118
119    //
120    // Called by the controller to give the sequencer a pointer.
121    // A pointer to the controller is needed for atomic support.
122    //
123    void setController(AbstractController* _cntrl) { m_controller = _cntrl; }
124
125  protected:
126    const std::string m_name;
127    void ruby_hit_callback(PacketPtr pkt);
128    void hit(PacketPtr pkt);
129
130    int m_version;
131    AbstractController* m_controller;
132    MessageBuffer* m_mandatory_q_ptr;
133    PioPort* pio_port;
134    bool m_usingRubyTester;
135
136  private:
137    void addToRetryList(M5Port * port)
138    {
139        if (!port->onRetryList()) {
140            port->onRetryList(true);
141            retryList.push_back(port);
142            waitingOnSequencer = true;
143        }
144    }
145
146    uint16_t m_port_id;
147    uint64_t m_request_cnt;
148
149    M5Port* physMemPort;
150
151    /*! Vector of CPU Port attached to this Ruby port. */
152    typedef std::vector<M5Port*>::iterator CpuPortIter;
153    std::vector<M5Port*> cpu_ports;
154
155    PhysicalMemory* physmem;
156    RubySystem* ruby_system;
157
158    //
159    // Based on similar code in the M5 bus.  Stores pointers to those ports
160    // that should be called when the Sequencer becomes available after a stall.
161    //
162    std::list<M5Port*> retryList;
163
164    bool waitingOnSequencer;
165    bool access_phys_mem;
166};
167
168#endif // __MEM_RUBY_SYSTEM_RUBYPORT_HH__
169