RubyPort.hh revision 8229:78bf55f23338 
1/*
2 * Copyright (c) 2009 Advanced Micro Devices, Inc.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#ifndef __MEM_RUBY_SYSTEM_RUBYPORT_HH__
30#define __MEM_RUBY_SYSTEM_RUBYPORT_HH__
31
32#include <cassert>
33#include <string>
34
35#include "mem/protocol/RequestStatus.hh"
36#include "mem/ruby/slicc_interface/RubyRequest.hh"
37#include "mem/ruby/system/System.hh"
38#include "mem/mem_object.hh"
39#include "mem/physical.hh"
40#include "mem/tport.hh"
41#include "params/RubyPort.hh"
42
43class MessageBuffer;
44class AbstractController;
45
46class RubyPort : public MemObject
47{
48  public:
49    class M5Port : public SimpleTimingPort
50    {
51      private:
52        RubyPort *ruby_port;
53        bool _onRetryList;
54        bool access_phys_mem;
55
56      public:
57        M5Port(const std::string &_name, RubyPort *_port,
58               bool _access_phys_mem);
59        bool sendTiming(PacketPtr pkt);
60        void hitCallback(PacketPtr pkt);
61        unsigned deviceBlockSize() const;
62
63        bool onRetryList()
64        { return _onRetryList; }
65
66        void onRetryList(bool newVal)
67        { _onRetryList = newVal; }
68
69      protected:
70        virtual bool recvTiming(PacketPtr pkt);
71        virtual Tick recvAtomic(PacketPtr pkt);
72
73      private:
74        bool isPhysMemAddress(Addr addr);
75    };
76
77    friend class M5Port;
78
79    class PioPort : public SimpleTimingPort
80    {
81      private:
82        RubyPort *ruby_port;
83
84      public:
85        PioPort(const std::string &_name, RubyPort *_port);
86        bool sendTiming(PacketPtr pkt);
87
88      protected:
89        virtual bool recvTiming(PacketPtr pkt);
90        virtual Tick recvAtomic(PacketPtr pkt);
91    };
92
93    friend class PioPort;
94
95    struct SenderState : public Packet::SenderState
96    {
97        M5Port* port;
98        Packet::SenderState *saved;
99
100        SenderState(M5Port* _port, Packet::SenderState *sender_state = NULL)
101            : port(_port), saved(sender_state)
102        {}
103    };
104
105    typedef RubyPortParams Params;
106    RubyPort(const Params *p);
107    virtual ~RubyPort() {}
108
109    void init();
110
111    Port *getPort(const std::string &if_name, int idx);
112
113    virtual RequestStatus makeRequest(const RubyRequest & request) = 0;
114
115    //
116    // Called by the controller to give the sequencer a pointer.
117    // A pointer to the controller is needed for atomic support.
118    //
119    void setController(AbstractController* _cntrl) { m_controller = _cntrl; }
120
121  protected:
122    const std::string m_name;
123    void ruby_hit_callback(PacketPtr pkt);
124    void hit(PacketPtr pkt);
125
126    int m_version;
127    AbstractController* m_controller;
128    MessageBuffer* m_mandatory_q_ptr;
129    PioPort* pio_port;
130    bool m_usingRubyTester;
131
132  private:
133    void addToRetryList(M5Port * port)
134    {
135        if (!port->onRetryList()) {
136            port->onRetryList(true);
137            retryList.push_back(port);
138            waitingOnSequencer = true;
139        }
140    }
141
142    uint16_t m_port_id;
143    uint64_t m_request_cnt;
144
145    M5Port* physMemPort;
146
147    PhysicalMemory* physmem;
148
149    //
150    // Based on similar code in the M5 bus.  Stores pointers to those ports
151    // that should be called when the Sequencer becomes available after a stall.
152    //
153    std::list<M5Port*> retryList;
154
155    bool waitingOnSequencer;
156    bool access_phys_mem;
157};
158
159#endif // __MEM_RUBY_SYSTEM_RUBYPORT_HH__
160