RubyPort.hh revision 7910:8a92b39be50e 
1/*
2 * Copyright (c) 2009 Advanced Micro Devices, Inc.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#ifndef __MEM_RUBY_SYSTEM_RUBYPORT_HH__
30#define __MEM_RUBY_SYSTEM_RUBYPORT_HH__
31
32#include <cassert>
33#include <string>
34
35#include "mem/mem_object.hh"
36#include "mem/physical.hh"
37#include "mem/protocol/RequestStatus.hh"
38#include "mem/ruby/libruby.hh"
39#include "mem/ruby/system/System.hh"
40#include "mem/tport.hh"
41#include "params/RubyPort.hh"
42
43class MessageBuffer;
44class AbstractController;
45
46class RubyPort : public MemObject
47{
48  public:
49    class M5Port : public SimpleTimingPort
50    {
51      private:
52        RubyPort *ruby_port;
53        bool _onRetryList;
54
55      public:
56        M5Port(const std::string &_name, RubyPort *_port);
57        bool sendTiming(PacketPtr pkt);
58        void hitCallback(PacketPtr pkt);
59        unsigned deviceBlockSize() const;
60
61        bool onRetryList()
62        { return _onRetryList; }
63
64        void onRetryList(bool newVal)
65        { _onRetryList = newVal; }
66
67      protected:
68        virtual bool recvTiming(PacketPtr pkt);
69        virtual Tick recvAtomic(PacketPtr pkt);
70
71      private:
72        bool isPhysMemAddress(Addr addr);
73    };
74
75    friend class M5Port;
76
77    class PioPort : public SimpleTimingPort
78    {
79      private:
80        RubyPort *ruby_port;
81
82      public:
83        PioPort(const std::string &_name, RubyPort *_port);
84        bool sendTiming(PacketPtr pkt);
85
86      protected:
87        virtual bool recvTiming(PacketPtr pkt);
88        virtual Tick recvAtomic(PacketPtr pkt);
89    };
90
91    friend class PioPort;
92
93    struct SenderState : public Packet::SenderState
94    {
95        M5Port* port;
96        Packet::SenderState *saved;
97
98        SenderState(M5Port* _port, Packet::SenderState *sender_state = NULL)
99            : port(_port), saved(sender_state)
100        {}
101    };
102
103    typedef RubyPortParams Params;
104    RubyPort(const Params *p);
105    virtual ~RubyPort() {}
106
107    void init();
108
109    Port *getPort(const std::string &if_name, int idx);
110
111    virtual RequestStatus makeRequest(const RubyRequest & request) = 0;
112
113    //
114    // Called by the controller to give the sequencer a pointer.
115    // A pointer to the controller is needed for atomic support.
116    //
117    void setController(AbstractController* _cntrl) { m_controller = _cntrl; }
118
119  protected:
120    const std::string m_name;
121    void ruby_hit_callback(PacketPtr pkt);
122    void hit(PacketPtr pkt);
123
124    int m_version;
125    AbstractController* m_controller;
126    MessageBuffer* m_mandatory_q_ptr;
127    PioPort* pio_port;
128    bool m_usingRubyTester;
129
130  private:
131    void addToRetryList(M5Port * port)
132    {
133        if (!port->onRetryList()) {
134            port->onRetryList(true);
135            retryList.push_back(port);
136            waitingOnSequencer = true;
137        }
138    }
139
140    uint16_t m_port_id;
141    uint64_t m_request_cnt;
142
143    M5Port* physMemPort;
144
145    PhysicalMemory* physmem;
146
147    //
148    // Based on similar code in the M5 bus.  Stores pointers to those ports
149    // that should be called when the Sequencer becomes available after a stall.
150    //
151    std::list<M5Port*> retryList;
152
153    bool waitingOnSequencer;
154};
155
156#endif // __MEM_RUBY_SYSTEM_RUBYPORT_HH__
157