RubyPort.hh revision 7055:4e24742201d7 
1/*
2 * Copyright (c) 2009 Advanced Micro Devices, Inc.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#ifndef __MEM_RUBY_SYSTEM_RUBYPORT_HH__
30#define __MEM_RUBY_SYSTEM_RUBYPORT_HH__
31
32#include <cassert>
33#include <string>
34
35#include "mem/mem_object.hh"
36#include "mem/physical.hh"
37#include "mem/protocol/RequestStatus.hh"
38#include "mem/ruby/libruby.hh"
39#include "mem/tport.hh"
40#include "params/RubyPort.hh"
41
42class MessageBuffer;
43class AbstractController;
44
45class RubyPort : public MemObject
46{
47  public:
48    class M5Port : public SimpleTimingPort
49    {
50      private:
51        RubyPort *ruby_port;
52
53      public:
54        M5Port(const std::string &_name, RubyPort *_port);
55        bool sendTiming(PacketPtr pkt);
56        void hitCallback(PacketPtr pkt);
57
58      protected:
59        virtual bool recvTiming(PacketPtr pkt);
60        virtual Tick recvAtomic(PacketPtr pkt);
61
62      private:
63        bool isPhysMemAddress(Addr addr);
64    };
65
66    friend class M5Port;
67
68    class PioPort : public SimpleTimingPort
69    {
70      private:
71        RubyPort *ruby_port;
72
73      public:
74        PioPort(const std::string &_name, RubyPort *_port);
75        bool sendTiming(PacketPtr pkt);
76
77      protected:
78        virtual bool recvTiming(PacketPtr pkt);
79        virtual Tick recvAtomic(PacketPtr pkt);
80    };
81
82    friend class PioPort;
83
84    struct SenderState : public Packet::SenderState
85    {
86        M5Port* port;
87        Packet::SenderState *saved;
88
89        SenderState(M5Port* _port, Packet::SenderState *sender_state = NULL)
90            : port(_port), saved(sender_state)
91        {}
92    };
93
94    typedef RubyPortParams Params;
95    RubyPort(const Params *p);
96    virtual ~RubyPort() {}
97
98    void init();
99
100    Port *getPort(const std::string &if_name, int idx);
101
102    virtual RequestStatus makeRequest(const RubyRequest & request) = 0;
103
104    //
105    // Called by the controller to give the sequencer a pointer.
106    // A pointer to the controller is needed for atomic support.
107    //
108    void setController(AbstractController* _cntrl) { m_controller = _cntrl; }
109
110  protected:
111    const std::string m_name;
112    void ruby_hit_callback(PacketPtr pkt);
113    void hit(PacketPtr pkt);
114
115    int m_version;
116    AbstractController* m_controller;
117    MessageBuffer* m_mandatory_q_ptr;
118    PioPort* pio_port;
119
120  private:
121    uint16_t m_port_id;
122    uint64_t m_request_cnt;
123
124    M5Port* physMemPort;
125
126    PhysicalMemory* physmem;
127};
128
129#endif // __MEM_RUBY_SYSTEM_RUBYPORT_HH__
130