RubyPort.hh revision 6922:1620cffaa3b6 
1
2/*
3 * Copyright (c) 2009 Advanced Micro Devices, Inc.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;
10 * redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution;
13 * neither the name of the copyright holders nor the names of its
14 * contributors may be used to endorse or promote products derived from
15 * this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 */
29
30#ifndef RUBYPORT_H
31#define RUBYPORT_H
32
33#include "mem/ruby/libruby.hh"
34#include <string>
35#include <assert.h>
36
37#include "mem/mem_object.hh"
38#include "mem/tport.hh"
39#include "mem/physical.hh"
40#include "mem/protocol/RequestStatus.hh"
41
42#include "params/RubyPort.hh"
43
44using namespace std;
45
46class MessageBuffer;
47class AbstractController;
48
49class RubyPort : public MemObject {
50public:
51
52    class M5Port : public SimpleTimingPort
53    {
54
55        RubyPort *ruby_port;
56
57      public:
58        M5Port(const std::string &_name,
59               RubyPort *_port);
60        bool sendTiming(PacketPtr pkt);
61        void hitCallback(PacketPtr pkt);
62
63      protected:
64        virtual bool recvTiming(PacketPtr pkt);
65        virtual Tick recvAtomic(PacketPtr pkt);
66
67      private:
68        bool isPhysMemAddress(Addr addr);
69    };
70
71    friend class M5Port;
72
73    class PioPort : public SimpleTimingPort
74    {
75
76        RubyPort *ruby_port;
77
78      public:
79        PioPort(const std::string &_name,
80                RubyPort *_port);
81        bool sendTiming(PacketPtr pkt);
82
83      protected:
84        virtual bool recvTiming(PacketPtr pkt);
85        virtual Tick recvAtomic(PacketPtr pkt);
86    };
87
88    friend class PioPort;
89
90    struct SenderState : public Packet::SenderState
91    {
92        M5Port* port;
93        Packet::SenderState *saved;
94
95        SenderState(M5Port* _port,
96                    Packet::SenderState *sender_state = NULL)
97            : port(_port), saved(sender_state)
98        {}
99    };
100
101    typedef RubyPortParams Params;
102    RubyPort(const Params *p);
103    virtual ~RubyPort() {}
104
105    void init();
106
107    Port *getPort(const std::string &if_name, int idx);
108
109    virtual RequestStatus makeRequest(const RubyRequest & request) = 0;
110
111    //
112    // Called by the controller to give the sequencer a pointer.
113    // A pointer to the controller is needed for atomic support.
114    //
115    void setController(AbstractController* _cntrl) { m_controller = _cntrl; }
116
117protected:
118  const string m_name;
119  void ruby_hit_callback(PacketPtr pkt);
120  void hit(PacketPtr pkt);
121
122  int m_version;
123  AbstractController* m_controller;
124  MessageBuffer* m_mandatory_q_ptr;
125    PioPort* pio_port;
126
127private:
128    uint16_t m_port_id;
129    uint64_t m_request_cnt;
130
131    M5Port* physMemPort;
132
133    PhysicalMemory* physmem;
134};
135
136#endif
137