RubyPort.hh revision 6899:f8057af86bf7 
1
2/*
3 * Copyright (c) 2009 Advanced Micro Devices, Inc.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;
10 * redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution;
13 * neither the name of the copyright holders nor the names of its
14 * contributors may be used to endorse or promote products derived from
15 * this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 */
29
30#ifndef RUBYPORT_H
31#define RUBYPORT_H
32
33#include "mem/ruby/libruby.hh"
34#include <string>
35#include <assert.h>
36
37#include "mem/mem_object.hh"
38#include "mem/tport.hh"
39#include "mem/physical.hh"
40
41#include "params/RubyPort.hh"
42
43using namespace std;
44
45class MessageBuffer;
46class AbstractController;
47
48class RubyPort : public MemObject {
49public:
50
51    class M5Port : public SimpleTimingPort
52    {
53
54        RubyPort *ruby_port;
55
56      public:
57        M5Port(const std::string &_name,
58               RubyPort *_port);
59        bool sendTiming(PacketPtr pkt);
60        void hitCallback(PacketPtr pkt);
61
62      protected:
63        virtual bool recvTiming(PacketPtr pkt);
64        virtual Tick recvAtomic(PacketPtr pkt);
65
66      private:
67        bool isPhysMemAddress(Addr addr);
68    };
69
70    friend class M5Port;
71
72    class PioPort : public SimpleTimingPort
73    {
74
75        RubyPort *ruby_port;
76
77      public:
78        PioPort(const std::string &_name,
79                RubyPort *_port);
80        bool sendTiming(PacketPtr pkt);
81
82      protected:
83        virtual bool recvTiming(PacketPtr pkt);
84        virtual Tick recvAtomic(PacketPtr pkt);
85    };
86
87    friend class PioPort;
88
89    struct SenderState : public Packet::SenderState
90    {
91        M5Port* port;
92        Packet::SenderState *saved;
93
94        SenderState(M5Port* _port,
95                    Packet::SenderState *sender_state = NULL)
96            : port(_port), saved(sender_state)
97        {}
98    };
99
100    typedef RubyPortParams Params;
101    RubyPort(const Params *p);
102    virtual ~RubyPort() {}
103
104    void init();
105
106    Port *getPort(const std::string &if_name, int idx);
107
108    virtual int64_t makeRequest(const RubyRequest & request) = 0;
109
110    void registerHitCallback(void (*hit_callback)(int64_t request_id)) {
111        //
112        // Can't assign hit_callback twice and by default it is set to the
113        // RubyPort's default callback function.
114        //
115        assert(m_hit_callback == ruby_hit_callback);
116        m_hit_callback = hit_callback;
117    }
118
119    //
120    // Called by the controller to give the sequencer a pointer.
121    // A pointer to the controller is needed for atomic support.
122    //
123    void setController(AbstractController* _cntrl) { m_controller = _cntrl; }
124
125protected:
126  const string m_name;
127  void (*m_hit_callback)(int64_t);
128
129  int64_t makeUniqueRequestID() {
130    // The request ID is generated by combining the port ID with a request count
131    // so that request IDs can be formed concurrently by multiple threads.
132    // IDs are formed as follows:
133    //
134    //
135    //   0        PortID                         Request Count
136    // +----+---------------+-----------------------------------------------------+
137    // | 63 |     62-48     |                         47-0                        |
138    // +----+---------------+-----------------------------------------------------+
139    //
140    //
141    //  This limits the system to a maximum of 2^11 == 2048 components
142    //  and 2^48 ~= 3x10^14 requests per component
143
144    int64_t id = (static_cast<uint64_t>(m_port_id) << 48) | m_request_cnt;
145    m_request_cnt++;
146    // assert((m_request_cnt & (1<<48)) == 0);
147    return id;
148  }
149
150  int m_version;
151  AbstractController* m_controller;
152  MessageBuffer* m_mandatory_q_ptr;
153    PioPort* pio_port;
154
155    //
156    // The pending request map is protected so that the Sequencer can access it.
157    // This is a temporary fix until the libruby inteface is cleaned
158    //
159    struct RequestCookie {
160        Packet *pkt;
161        M5Port *m5Port;
162        RequestCookie(Packet *p, M5Port *m5p)
163            : pkt(p), m5Port(m5p)
164        {}
165    };
166
167    typedef std::map<int64_t, RequestCookie*> RequestMap;
168    static RequestMap pending_cpu_requests;
169
170private:
171  static uint16_t m_num_ports;
172  uint16_t m_port_id;
173  uint64_t m_request_cnt;
174
175    static void ruby_hit_callback(int64_t req_id);
176
177    M5Port* physMemPort;
178
179    PhysicalMemory* physmem;
180};
181
182#endif
183