RubyPort.hh revision 10089:bc3126a05a7f 
1/*
2 * Copyright (c) 2012-2013 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2009 Advanced Micro Devices, Inc.
15 * Copyright (c) 2011 Mark D. Hill and David A. Wood
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 */
41
42#ifndef __MEM_RUBY_SYSTEM_RUBYPORT_HH__
43#define __MEM_RUBY_SYSTEM_RUBYPORT_HH__
44
45#include <cassert>
46#include <string>
47
48#include "mem/protocol/RequestStatus.hh"
49#include "mem/ruby/buffers/MessageBuffer.hh"
50#include "mem/ruby/system/System.hh"
51#include "mem/mem_object.hh"
52#include "mem/physical.hh"
53#include "mem/tport.hh"
54#include "params/RubyPort.hh"
55
56class AbstractController;
57
58class RubyPort : public MemObject
59{
60  public:
61    class M5Port : public QueuedSlavePort
62    {
63      private:
64
65        SlavePacketQueue queue;
66        RubyPort *ruby_port;
67        RubySystem* ruby_system;
68        bool access_phys_mem;
69
70      public:
71        M5Port(const std::string &_name, RubyPort *_port,
72               RubySystem*_system, bool _access_phys_mem, PortID id);
73        void hitCallback(PacketPtr pkt);
74        void evictionCallback(const Address& address);
75
76      protected:
77        bool recvTimingReq(PacketPtr pkt);
78        Tick recvAtomic(PacketPtr pkt);
79        void recvFunctional(PacketPtr pkt);
80        AddrRangeList getAddrRanges() const;
81
82      private:
83        bool isPhysMemAddress(Addr addr) const;
84    };
85
86    class PioPort : public QueuedMasterPort
87    {
88      private:
89
90        MasterPacketQueue queue;
91        RubyPort *ruby_port;
92
93      public:
94        PioPort(const std::string &_name, RubyPort *_port);
95
96      protected:
97        bool recvTimingResp(PacketPtr pkt)
98        { return ruby_port->recvTimingResp(pkt, id); }
99    };
100
101    typedef RubyPortParams Params;
102    RubyPort(const Params *p);
103    virtual ~RubyPort() {}
104
105    void init();
106
107    BaseMasterPort &getMasterPort(const std::string &if_name,
108                                  PortID idx = InvalidPortID);
109    BaseSlavePort &getSlavePort(const std::string &if_name,
110                                PortID idx = InvalidPortID);
111
112    virtual RequestStatus makeRequest(PacketPtr pkt) = 0;
113    virtual int outstandingCount() const = 0;
114    virtual bool isDeadlockEventScheduled() const = 0;
115    virtual void descheduleDeadlockEvent() = 0;
116
117    //
118    // Called by the controller to give the sequencer a pointer.
119    // A pointer to the controller is needed for atomic support.
120    //
121    void setController(AbstractController* _cntrl) { m_controller = _cntrl; }
122    uint32_t getId() { return m_version; }
123    unsigned int drain(DrainManager *dm);
124
125  protected:
126    const std::string m_name;
127    void ruby_hit_callback(PacketPtr pkt);
128    void testDrainComplete();
129    void ruby_eviction_callback(const Address& address);
130
131    /**
132     * Called by the PIO port when receiving a timing response.
133     *
134     * @param pkt Response packet
135     * @param master_port_id Port id of the PIO port
136     *
137     * @return Whether successfully sent
138     */
139    bool recvTimingResp(PacketPtr pkt, PortID master_port_id);
140
141    uint32_t m_version;
142    AbstractController* m_controller;
143    MessageBuffer* m_mandatory_q_ptr;
144    PioPort pio_port;
145    bool m_usingRubyTester;
146
147  private:
148    void addToRetryList(M5Port * port)
149    {
150        assert(std::find(retryList.begin(), retryList.end(), port) ==
151               retryList.end());
152        retryList.push_back(port);
153    }
154
155    unsigned int getChildDrainCount(DrainManager *dm);
156
157    /** Vector of M5 Ports attached to this Ruby port. */
158    typedef std::vector<M5Port*>::iterator CpuPortIter;
159    std::vector<M5Port*> slave_ports;
160    std::vector<PioPort*> master_ports;
161
162    DrainManager *drainManager;
163
164    RubySystem* ruby_system;
165    System* system;
166
167    //
168    // Based on similar code in the M5 bus.  Stores pointers to those ports
169    // that should be called when the Sequencer becomes available after a stall.
170    //
171    std::vector<M5Port*> retryList;
172
173    bool access_phys_mem;
174};
175
176#endif // __MEM_RUBY_SYSTEM_RUBYPORT_HH__
177