RubyPort.cc revision 8923:820111f58fbb
1/* 2 * Copyright (c) 2012 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2009 Advanced Micro Devices, Inc. 15 * Copyright (c) 2011 Mark D. Hill and David A. Wood 16 * All rights reserved. 17 * 18 * Redistribution and use in source and binary forms, with or without 19 * modification, are permitted provided that the following conditions are 20 * met: redistributions of source code must retain the above copyright 21 * notice, this list of conditions and the following disclaimer; 22 * redistributions in binary form must reproduce the above copyright 23 * notice, this list of conditions and the following disclaimer in the 24 * documentation and/or other materials provided with the distribution; 25 * neither the name of the copyright holders nor the names of its 26 * contributors may be used to endorse or promote products derived from 27 * this software without specific prior written permission. 28 * 29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40 */ 41 42#include "cpu/testers/rubytest/RubyTester.hh" 43#include "debug/Config.hh" 44#include "debug/Ruby.hh" 45#include "mem/protocol/AccessPermission.hh" 46#include "mem/ruby/slicc_interface/AbstractController.hh" 47#include "mem/ruby/system/RubyPort.hh" 48#include "sim/system.hh" 49 50RubyPort::RubyPort(const Params *p) 51 : MemObject(p), m_version(p->version), m_controller(NULL), 52 m_mandatory_q_ptr(NULL), 53 pio_port(csprintf("%s-pio-port", name()), this), 54 m_usingRubyTester(p->using_ruby_tester), m_request_cnt(0), 55 drainEvent(NULL), ruby_system(p->ruby_system), system(p->system), 56 waitingOnSequencer(false), access_phys_mem(p->access_phys_mem) 57{ 58 assert(m_version != -1); 59 60 // create the slave ports based on the number of connected ports 61 for (size_t i = 0; i < p->port_slave_connection_count; ++i) { 62 slave_ports.push_back(new M5Port(csprintf("%s-slave%d", name(), i), 63 this, ruby_system, access_phys_mem)); 64 } 65 66 // create the master ports based on the number of connected ports 67 for (size_t i = 0; i < p->port_master_connection_count; ++i) { 68 master_ports.push_back(new PioPort(csprintf("%s-master%d", name(), i), 69 this)); 70 } 71} 72 73void 74RubyPort::init() 75{ 76 assert(m_controller != NULL); 77 m_mandatory_q_ptr = m_controller->getMandatoryQueue(); 78} 79 80MasterPort & 81RubyPort::getMasterPort(const std::string &if_name, int idx) 82{ 83 if (if_name == "pio_port") { 84 return pio_port; 85 } 86 87 // used by the x86 CPUs to connect the interrupt PIO and interrupt slave 88 // port 89 if (if_name != "master") { 90 // pass it along to our super class 91 return MemObject::getMasterPort(if_name, idx); 92 } else { 93 if (idx >= static_cast<int>(master_ports.size())) { 94 panic("RubyPort::getMasterPort: unknown index %d\n", idx); 95 } 96 97 return *master_ports[idx]; 98 } 99} 100 101SlavePort & 102RubyPort::getSlavePort(const std::string &if_name, int idx) 103{ 104 // used by the CPUs to connect the caches to the interconnect, and 105 // for the x86 case also the interrupt master 106 if (if_name != "slave") { 107 // pass it along to our super class 108 return MemObject::getSlavePort(if_name, idx); 109 } else { 110 if (idx >= static_cast<int>(slave_ports.size())) { 111 panic("RubyPort::getSlavePort: unknown index %d\n", idx); 112 } 113 114 return *slave_ports[idx]; 115 } 116} 117 118RubyPort::PioPort::PioPort(const std::string &_name, 119 RubyPort *_port) 120 : QueuedMasterPort(_name, _port, queue), queue(*_port, *this), 121 ruby_port(_port) 122{ 123 DPRINTF(RubyPort, "creating master port on ruby sequencer %s\n", _name); 124} 125 126RubyPort::M5Port::M5Port(const std::string &_name, RubyPort *_port, 127 RubySystem *_system, bool _access_phys_mem) 128 : QueuedSlavePort(_name, _port, queue), queue(*_port, *this), 129 ruby_port(_port), ruby_system(_system), 130 _onRetryList(false), access_phys_mem(_access_phys_mem) 131{ 132 DPRINTF(RubyPort, "creating slave port on ruby sequencer %s\n", _name); 133} 134 135Tick 136RubyPort::PioPort::recvAtomic(PacketPtr pkt) 137{ 138 panic("RubyPort::PioPort::recvAtomic() not implemented!\n"); 139 return 0; 140} 141 142Tick 143RubyPort::M5Port::recvAtomic(PacketPtr pkt) 144{ 145 panic("RubyPort::M5Port::recvAtomic() not implemented!\n"); 146 return 0; 147} 148 149 150bool 151RubyPort::PioPort::recvTiming(PacketPtr pkt) 152{ 153 // In FS mode, ruby memory will receive pio responses from devices 154 // and it must forward these responses back to the particular CPU. 155 DPRINTF(RubyPort, "Pio response for address %#x\n", pkt->getAddr()); 156 157 assert(pkt->isResponse()); 158 159 // First we must retrieve the request port from the sender State 160 RubyPort::SenderState *senderState = 161 safe_cast<RubyPort::SenderState *>(pkt->senderState); 162 M5Port *port = senderState->port; 163 assert(port != NULL); 164 165 // pop the sender state from the packet 166 pkt->senderState = senderState->saved; 167 delete senderState; 168 169 port->sendTiming(pkt); 170 171 return true; 172} 173 174bool 175RubyPort::M5Port::recvTiming(PacketPtr pkt) 176{ 177 DPRINTF(RubyPort, 178 "Timing access caught for address %#x\n", pkt->getAddr()); 179 180 //dsm: based on SimpleTimingPort::recvTiming(pkt); 181 182 // The received packets should only be M5 requests, which should never 183 // get nacked. There used to be code to hanldle nacks here, but 184 // I'm pretty sure it didn't work correctly with the drain code, 185 // so that would need to be fixed if we ever added it back. 186 assert(pkt->isRequest()); 187 188 if (pkt->memInhibitAsserted()) { 189 warn("memInhibitAsserted???"); 190 // snooper will supply based on copy of packet 191 // still target's responsibility to delete packet 192 delete pkt; 193 return true; 194 } 195 196 // Save the port in the sender state object to be used later to 197 // route the response 198 pkt->senderState = new SenderState(this, pkt->senderState); 199 200 // Check for pio requests and directly send them to the dedicated 201 // pio port. 202 if (!isPhysMemAddress(pkt->getAddr())) { 203 assert(ruby_port->pio_port.isConnected()); 204 DPRINTF(RubyPort, 205 "Request for address 0x%#x is assumed to be a pio request\n", 206 pkt->getAddr()); 207 208 return ruby_port->pio_port.sendNextCycle(pkt); 209 } 210 211 assert(Address(pkt->getAddr()).getOffset() + pkt->getSize() <= 212 RubySystem::getBlockSizeBytes()); 213 214 // Submit the ruby request 215 RequestStatus requestStatus = ruby_port->makeRequest(pkt); 216 217 // If the request successfully issued then we should return true. 218 // Otherwise, we need to delete the senderStatus we just created and return 219 // false. 220 if (requestStatus == RequestStatus_Issued) { 221 DPRINTF(RubyPort, "Request %#x issued\n", pkt->getAddr()); 222 return true; 223 } 224 225 // 226 // Unless one is using the ruby tester, record the stalled M5 port for 227 // later retry when the sequencer becomes free. 228 // 229 if (!ruby_port->m_usingRubyTester) { 230 ruby_port->addToRetryList(this); 231 } 232 233 DPRINTF(RubyPort, 234 "Request for address %#x did not issue because %s\n", 235 pkt->getAddr(), RequestStatus_to_string(requestStatus)); 236 237 SenderState* senderState = safe_cast<SenderState*>(pkt->senderState); 238 pkt->senderState = senderState->saved; 239 delete senderState; 240 return false; 241} 242 243bool 244RubyPort::M5Port::doFunctionalRead(PacketPtr pkt) 245{ 246 Address address(pkt->getAddr()); 247 Address line_address(address); 248 line_address.makeLineAddress(); 249 250 AccessPermission access_perm = AccessPermission_NotPresent; 251 int num_controllers = ruby_system->m_abs_cntrl_vec.size(); 252 253 DPRINTF(RubyPort, "Functional Read request for %s\n",address); 254 255 unsigned int num_ro = 0; 256 unsigned int num_rw = 0; 257 unsigned int num_busy = 0; 258 unsigned int num_backing_store = 0; 259 unsigned int num_invalid = 0; 260 261 // In this loop we count the number of controllers that have the given 262 // address in read only, read write and busy states. 263 for (int i = 0; i < num_controllers; ++i) { 264 access_perm = ruby_system->m_abs_cntrl_vec[i]-> 265 getAccessPermission(line_address); 266 if (access_perm == AccessPermission_Read_Only) 267 num_ro++; 268 else if (access_perm == AccessPermission_Read_Write) 269 num_rw++; 270 else if (access_perm == AccessPermission_Busy) 271 num_busy++; 272 else if (access_perm == AccessPermission_Backing_Store) 273 // See RubySlicc_Exports.sm for details, but Backing_Store is meant 274 // to represent blocks in memory *for Broadcast/Snooping protocols*, 275 // where memory has no idea whether it has an exclusive copy of data 276 // or not. 277 num_backing_store++; 278 else if (access_perm == AccessPermission_Invalid || 279 access_perm == AccessPermission_NotPresent) 280 num_invalid++; 281 } 282 assert(num_rw <= 1); 283 284 uint8* data = pkt->getPtr<uint8_t>(true); 285 unsigned int size_in_bytes = pkt->getSize(); 286 unsigned startByte = address.getAddress() - line_address.getAddress(); 287 288 // This if case is meant to capture what happens in a Broadcast/Snoop 289 // protocol where the block does not exist in the cache hierarchy. You 290 // only want to read from the Backing_Store memory if there is no copy in 291 // the cache hierarchy, otherwise you want to try to read the RO or RW 292 // copies existing in the cache hierarchy (covered by the else statement). 293 // The reason is because the Backing_Store memory could easily be stale, if 294 // there are copies floating around the cache hierarchy, so you want to read 295 // it only if it's not in the cache hierarchy at all. 296 if (num_invalid == (num_controllers - 1) && 297 num_backing_store == 1) 298 { 299 DPRINTF(RubyPort, "only copy in Backing_Store memory, read from it\n"); 300 for (int i = 0; i < num_controllers; ++i) { 301 access_perm = ruby_system->m_abs_cntrl_vec[i] 302 ->getAccessPermission(line_address); 303 if (access_perm == AccessPermission_Backing_Store) { 304 DataBlock& block = ruby_system->m_abs_cntrl_vec[i] 305 ->getDataBlock(line_address); 306 307 DPRINTF(RubyPort, "reading from %s block %s\n", 308 ruby_system->m_abs_cntrl_vec[i]->name(), block); 309 for (unsigned i = 0; i < size_in_bytes; ++i) { 310 data[i] = block.getByte(i + startByte); 311 } 312 return true; 313 } 314 } 315 } else { 316 // In Broadcast/Snoop protocols, this covers if you know the block 317 // exists somewhere in the caching hierarchy, then you want to read any 318 // valid RO or RW block. In directory protocols, same thing, you want 319 // to read any valid readable copy of the block. 320 DPRINTF(RubyPort, "num_busy = %d, num_ro = %d, num_rw = %d\n", 321 num_busy, num_ro, num_rw); 322 // In this loop, we try to figure which controller has a read only or 323 // a read write copy of the given address. Any valid copy would suffice 324 // for a functional read. 325 for(int i = 0;i < num_controllers;++i) { 326 access_perm = ruby_system->m_abs_cntrl_vec[i] 327 ->getAccessPermission(line_address); 328 if(access_perm == AccessPermission_Read_Only || 329 access_perm == AccessPermission_Read_Write) 330 { 331 DataBlock& block = ruby_system->m_abs_cntrl_vec[i] 332 ->getDataBlock(line_address); 333 334 DPRINTF(RubyPort, "reading from %s block %s\n", 335 ruby_system->m_abs_cntrl_vec[i]->name(), block); 336 for (unsigned i = 0; i < size_in_bytes; ++i) { 337 data[i] = block.getByte(i + startByte); 338 } 339 return true; 340 } 341 } 342 } 343 return false; 344} 345 346bool 347RubyPort::M5Port::doFunctionalWrite(PacketPtr pkt) 348{ 349 Address addr(pkt->getAddr()); 350 Address line_addr = line_address(addr); 351 AccessPermission access_perm = AccessPermission_NotPresent; 352 int num_controllers = ruby_system->m_abs_cntrl_vec.size(); 353 354 DPRINTF(RubyPort, "Functional Write request for %s\n",addr); 355 356 unsigned int num_ro = 0; 357 unsigned int num_rw = 0; 358 unsigned int num_busy = 0; 359 unsigned int num_backing_store = 0; 360 unsigned int num_invalid = 0; 361 362 // In this loop we count the number of controllers that have the given 363 // address in read only, read write and busy states. 364 for(int i = 0;i < num_controllers;++i) { 365 access_perm = ruby_system->m_abs_cntrl_vec[i]-> 366 getAccessPermission(line_addr); 367 if (access_perm == AccessPermission_Read_Only) 368 num_ro++; 369 else if (access_perm == AccessPermission_Read_Write) 370 num_rw++; 371 else if (access_perm == AccessPermission_Busy) 372 num_busy++; 373 else if (access_perm == AccessPermission_Backing_Store) 374 // See RubySlicc_Exports.sm for details, but Backing_Store is meant 375 // to represent blocks in memory *for Broadcast/Snooping protocols*, 376 // where memory has no idea whether it has an exclusive copy of data 377 // or not. 378 num_backing_store++; 379 else if (access_perm == AccessPermission_Invalid || 380 access_perm == AccessPermission_NotPresent) 381 num_invalid++; 382 } 383 384 // If the number of read write copies is more than 1, then there is bug in 385 // coherence protocol. Otherwise, if all copies are in stable states, i.e. 386 // num_busy == 0, we update all the copies. If there is at least one copy 387 // in busy state, then we check if there is read write copy. If yes, then 388 // also we let the access go through. Or, if there is no copy in the cache 389 // hierarchy at all, we still want to do the write to the memory 390 // (Backing_Store) instead of failing. 391 392 DPRINTF(RubyPort, "num_busy = %d, num_ro = %d, num_rw = %d\n", 393 num_busy, num_ro, num_rw); 394 assert(num_rw <= 1); 395 396 uint8* data = pkt->getPtr<uint8_t>(true); 397 unsigned int size_in_bytes = pkt->getSize(); 398 unsigned startByte = addr.getAddress() - line_addr.getAddress(); 399 400 if ((num_busy == 0 && num_ro > 0) || num_rw == 1 || 401 (num_invalid == (num_controllers - 1) && num_backing_store == 1)) 402 { 403 for(int i = 0; i < num_controllers;++i) { 404 access_perm = ruby_system->m_abs_cntrl_vec[i]-> 405 getAccessPermission(line_addr); 406 if(access_perm == AccessPermission_Read_Only || 407 access_perm == AccessPermission_Read_Write|| 408 access_perm == AccessPermission_Maybe_Stale || 409 access_perm == AccessPermission_Backing_Store) 410 { 411 DataBlock& block = ruby_system->m_abs_cntrl_vec[i] 412 ->getDataBlock(line_addr); 413 414 DPRINTF(RubyPort, "%s\n",block); 415 for (unsigned i = 0; i < size_in_bytes; ++i) { 416 block.setByte(i + startByte, data[i]); 417 } 418 DPRINTF(RubyPort, "%s\n",block); 419 } 420 } 421 return true; 422 } 423 return false; 424} 425 426void 427RubyPort::M5Port::recvFunctional(PacketPtr pkt) 428{ 429 DPRINTF(RubyPort, "Functional access caught for address %#x\n", 430 pkt->getAddr()); 431 432 // Check for pio requests and directly send them to the dedicated 433 // pio port. 434 if (!isPhysMemAddress(pkt->getAddr())) { 435 assert(ruby_port->pio_port.isConnected()); 436 DPRINTF(RubyPort, "Request for address 0x%#x is a pio request\n", 437 pkt->getAddr()); 438 panic("RubyPort::PioPort::recvFunctional() not implemented!\n"); 439 } 440 441 assert(pkt->getAddr() + pkt->getSize() <= 442 line_address(Address(pkt->getAddr())).getAddress() + 443 RubySystem::getBlockSizeBytes()); 444 445 bool accessSucceeded = false; 446 bool needsResponse = pkt->needsResponse(); 447 448 // Do the functional access on ruby memory 449 if (pkt->isRead()) { 450 accessSucceeded = doFunctionalRead(pkt); 451 } else if (pkt->isWrite()) { 452 accessSucceeded = doFunctionalWrite(pkt); 453 } else { 454 panic("RubyPort: unsupported functional command %s\n", 455 pkt->cmdString()); 456 } 457 458 // Unless the requester explicitly said otherwise, generate an error if 459 // the functional request failed 460 if (!accessSucceeded && !pkt->suppressFuncError()) { 461 fatal("Ruby functional %s failed for address %#x\n", 462 pkt->isWrite() ? "write" : "read", pkt->getAddr()); 463 } 464 465 if (access_phys_mem) { 466 // The attached physmem contains the official version of data. 467 // The following command performs the real functional access. 468 // This line should be removed once Ruby supplies the official version 469 // of data. 470 ruby_port->system->physmem->doFunctionalAccess(pkt); 471 } 472 473 // turn packet around to go back to requester if response expected 474 if (needsResponse) { 475 pkt->setFunctionalResponseStatus(accessSucceeded); 476 477 // @todo There should not be a reverse call since the response is 478 // communicated through the packet pointer 479 // DPRINTF(RubyPort, "Sending packet back over port\n"); 480 // sendFunctional(pkt); 481 } 482 DPRINTF(RubyPort, "Functional access %s!\n", 483 accessSucceeded ? "successful":"failed"); 484} 485 486void 487RubyPort::ruby_hit_callback(PacketPtr pkt) 488{ 489 // Retrieve the request port from the sender State 490 RubyPort::SenderState *senderState = 491 safe_cast<RubyPort::SenderState *>(pkt->senderState); 492 M5Port *port = senderState->port; 493 assert(port != NULL); 494 495 // pop the sender state from the packet 496 pkt->senderState = senderState->saved; 497 delete senderState; 498 499 port->hitCallback(pkt); 500 501 // 502 // If we had to stall the M5Ports, wake them up because the sequencer 503 // likely has free resources now. 504 // 505 if (waitingOnSequencer) { 506 // 507 // Record the current list of ports to retry on a temporary list before 508 // calling sendRetry on those ports. sendRetry will cause an 509 // immediate retry, which may result in the ports being put back on the 510 // list. Therefore we want to clear the retryList before calling 511 // sendRetry. 512 // 513 std::list<M5Port*> curRetryList(retryList); 514 515 retryList.clear(); 516 waitingOnSequencer = false; 517 518 for (std::list<M5Port*>::iterator i = curRetryList.begin(); 519 i != curRetryList.end(); ++i) { 520 DPRINTF(RubyPort, 521 "Sequencer may now be free. SendRetry to port %s\n", 522 (*i)->name()); 523 (*i)->onRetryList(false); 524 (*i)->sendRetry(); 525 } 526 } 527 528 testDrainComplete(); 529} 530 531void 532RubyPort::testDrainComplete() 533{ 534 //If we weren't able to drain before, we might be able to now. 535 if (drainEvent != NULL) { 536 unsigned int drainCount = getDrainCount(drainEvent); 537 DPRINTF(Config, "Drain count: %u\n", drainCount); 538 if (drainCount == 0) { 539 drainEvent->process(); 540 // Clear the drain event once we're done with it. 541 drainEvent = NULL; 542 } 543 } 544} 545 546unsigned int 547RubyPort::getDrainCount(Event *de) 548{ 549 int count = 0; 550 // 551 // If the sequencer is not empty, then requests need to drain. 552 // The outstandingCount is the number of requests outstanding and thus the 553 // number of times M5's timing port will process the drain event. 554 // 555 count += outstandingCount(); 556 557 DPRINTF(Config, "outstanding count %d\n", outstandingCount()); 558 559 // To simplify the draining process, the sequencer's deadlock detection 560 // event should have been descheduled. 561 assert(isDeadlockEventScheduled() == false); 562 563 if (pio_port.isConnected()) { 564 count += pio_port.drain(de); 565 DPRINTF(Config, "count after pio check %d\n", count); 566 } 567 568 for (CpuPortIter p = slave_ports.begin(); p != slave_ports.end(); ++p) { 569 count += (*p)->drain(de); 570 DPRINTF(Config, "count after slave port check %d\n", count); 571 } 572 573 for (std::vector<PioPort*>::iterator p = master_ports.begin(); 574 p != master_ports.end(); ++p) { 575 count += (*p)->drain(de); 576 DPRINTF(Config, "count after master port check %d\n", count); 577 } 578 579 DPRINTF(Config, "final count %d\n", count); 580 581 return count; 582} 583 584unsigned int 585RubyPort::drain(Event *de) 586{ 587 if (isDeadlockEventScheduled()) { 588 descheduleDeadlockEvent(); 589 } 590 591 int count = getDrainCount(de); 592 593 // Set status 594 if (count != 0) { 595 drainEvent = de; 596 597 changeState(SimObject::Draining); 598 return count; 599 } 600 601 changeState(SimObject::Drained); 602 return 0; 603} 604 605void 606RubyPort::M5Port::hitCallback(PacketPtr pkt) 607{ 608 bool needsResponse = pkt->needsResponse(); 609 610 // 611 // Unless specified at configuraiton, all responses except failed SC 612 // and Flush operations access M5 physical memory. 613 // 614 bool accessPhysMem = access_phys_mem; 615 616 if (pkt->isLLSC()) { 617 if (pkt->isWrite()) { 618 if (pkt->req->getExtraData() != 0) { 619 // 620 // Successful SC packets convert to normal writes 621 // 622 pkt->convertScToWrite(); 623 } else { 624 // 625 // Failed SC packets don't access physical memory and thus 626 // the RubyPort itself must convert it to a response. 627 // 628 accessPhysMem = false; 629 } 630 } else { 631 // 632 // All LL packets convert to normal loads so that M5 PhysMem does 633 // not lock the blocks. 634 // 635 pkt->convertLlToRead(); 636 } 637 } 638 639 // 640 // Flush requests don't access physical memory 641 // 642 if (pkt->isFlush()) { 643 accessPhysMem = false; 644 } 645 646 DPRINTF(RubyPort, "Hit callback needs response %d\n", needsResponse); 647 648 if (accessPhysMem) { 649 ruby_port->system->physmem->doAtomicAccess(pkt); 650 } else if (needsResponse) { 651 pkt->makeResponse(); 652 } 653 654 // turn packet around to go back to requester if response expected 655 if (needsResponse) { 656 DPRINTF(RubyPort, "Sending packet back over port\n"); 657 sendNextCycle(pkt); 658 } else { 659 delete pkt; 660 } 661 DPRINTF(RubyPort, "Hit callback done!\n"); 662} 663 664bool 665RubyPort::M5Port::sendNextCycle(PacketPtr pkt) 666{ 667 //minimum latency, must be > 0 668 queue.schedSendTiming(pkt, curTick() + (1 * g_eventQueue_ptr->getClock())); 669 return true; 670} 671 672bool 673RubyPort::PioPort::sendNextCycle(PacketPtr pkt) 674{ 675 //minimum latency, must be > 0 676 queue.schedSendTiming(pkt, curTick() + (1 * g_eventQueue_ptr->getClock())); 677 return true; 678} 679 680AddrRangeList 681RubyPort::M5Port::getAddrRanges() 682{ 683 // at the moment the assumption is that the master does not care 684 AddrRangeList ranges; 685 return ranges; 686} 687 688bool 689RubyPort::M5Port::isPhysMemAddress(Addr addr) 690{ 691 return ruby_port->system->isMemory(addr); 692} 693 694unsigned 695RubyPort::M5Port::deviceBlockSize() const 696{ 697 return (unsigned) RubySystem::getBlockSizeBytes(); 698} 699 700void 701RubyPort::ruby_eviction_callback(const Address& address) 702{ 703 DPRINTF(RubyPort, "Sending invalidations.\n"); 704 // should this really be using funcMasterId? 705 Request req(address.getAddress(), 0, 0, Request::funcMasterId); 706 for (CpuPortIter p = slave_ports.begin(); p != slave_ports.end(); ++p) { 707 if ((*p)->getMasterPort().isSnooping()) { 708 Packet *pkt = new Packet(&req, MemCmd::InvalidationReq, -1); 709 (*p)->sendNextCycle(pkt); 710 } 711 } 712} 713