RubyPort.cc revision 10657:8bb4a9717eaa
1/* 2 * Copyright (c) 2012-2013 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2009 Advanced Micro Devices, Inc. 15 * Copyright (c) 2011 Mark D. Hill and David A. Wood 16 * All rights reserved. 17 * 18 * Redistribution and use in source and binary forms, with or without 19 * modification, are permitted provided that the following conditions are 20 * met: redistributions of source code must retain the above copyright 21 * notice, this list of conditions and the following disclaimer; 22 * redistributions in binary form must reproduce the above copyright 23 * notice, this list of conditions and the following disclaimer in the 24 * documentation and/or other materials provided with the distribution; 25 * neither the name of the copyright holders nor the names of its 26 * contributors may be used to endorse or promote products derived from 27 * this software without specific prior written permission. 28 * 29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40 */ 41 42#include "cpu/testers/rubytest/RubyTester.hh" 43#include "debug/Config.hh" 44#include "debug/Drain.hh" 45#include "debug/Ruby.hh" 46#include "mem/protocol/AccessPermission.hh" 47#include "mem/ruby/slicc_interface/AbstractController.hh" 48#include "mem/ruby/system/RubyPort.hh" 49#include "mem/simple_mem.hh" 50#include "sim/full_system.hh" 51#include "sim/system.hh" 52 53RubyPort::RubyPort(const Params *p) 54 : MemObject(p), m_version(p->version), m_controller(NULL), 55 m_mandatory_q_ptr(NULL), m_usingRubyTester(p->using_ruby_tester), 56 system(p->system), 57 pioMasterPort(csprintf("%s.pio-master-port", name()), this), 58 pioSlavePort(csprintf("%s.pio-slave-port", name()), this), 59 memMasterPort(csprintf("%s.mem-master-port", name()), this), 60 memSlavePort(csprintf("%s-mem-slave-port", name()), this, 61 p->ruby_system, p->access_backing_store, -1), 62 gotAddrRanges(p->port_master_connection_count), drainManager(NULL) 63{ 64 assert(m_version != -1); 65 66 // create the slave ports based on the number of connected ports 67 for (size_t i = 0; i < p->port_slave_connection_count; ++i) { 68 slave_ports.push_back(new MemSlavePort(csprintf("%s.slave%d", name(), 69 i), this, p->ruby_system, p->access_backing_store, i)); 70 } 71 72 // create the master ports based on the number of connected ports 73 for (size_t i = 0; i < p->port_master_connection_count; ++i) { 74 master_ports.push_back(new PioMasterPort(csprintf("%s.master%d", 75 name(), i), this)); 76 } 77} 78 79void 80RubyPort::init() 81{ 82 assert(m_controller != NULL); 83 m_mandatory_q_ptr = m_controller->getMandatoryQueue(); 84 m_mandatory_q_ptr->setSender(this); 85} 86 87BaseMasterPort & 88RubyPort::getMasterPort(const std::string &if_name, PortID idx) 89{ 90 if (if_name == "mem_master_port") { 91 return memMasterPort; 92 } 93 94 if (if_name == "pio_master_port") { 95 return pioMasterPort; 96 } 97 98 // used by the x86 CPUs to connect the interrupt PIO and interrupt slave 99 // port 100 if (if_name != "master") { 101 // pass it along to our super class 102 return MemObject::getMasterPort(if_name, idx); 103 } else { 104 if (idx >= static_cast<PortID>(master_ports.size())) { 105 panic("RubyPort::getMasterPort: unknown index %d\n", idx); 106 } 107 108 return *master_ports[idx]; 109 } 110} 111 112BaseSlavePort & 113RubyPort::getSlavePort(const std::string &if_name, PortID idx) 114{ 115 if (if_name == "mem_slave_port") { 116 return memSlavePort; 117 } 118 119 if (if_name == "pio_slave_port") 120 return pioSlavePort; 121 122 // used by the CPUs to connect the caches to the interconnect, and 123 // for the x86 case also the interrupt master 124 if (if_name != "slave") { 125 // pass it along to our super class 126 return MemObject::getSlavePort(if_name, idx); 127 } else { 128 if (idx >= static_cast<PortID>(slave_ports.size())) { 129 panic("RubyPort::getSlavePort: unknown index %d\n", idx); 130 } 131 132 return *slave_ports[idx]; 133 } 134} 135 136RubyPort::PioMasterPort::PioMasterPort(const std::string &_name, 137 RubyPort *_port) 138 : QueuedMasterPort(_name, _port, queue), queue(*_port, *this) 139{ 140 DPRINTF(RubyPort, "Created master pioport on sequencer %s\n", _name); 141} 142 143RubyPort::PioSlavePort::PioSlavePort(const std::string &_name, 144 RubyPort *_port) 145 : QueuedSlavePort(_name, _port, queue), queue(*_port, *this) 146{ 147 DPRINTF(RubyPort, "Created slave pioport on sequencer %s\n", _name); 148} 149 150RubyPort::MemMasterPort::MemMasterPort(const std::string &_name, 151 RubyPort *_port) 152 : QueuedMasterPort(_name, _port, queue), queue(*_port, *this) 153{ 154 DPRINTF(RubyPort, "Created master memport on ruby sequencer %s\n", _name); 155} 156 157RubyPort::MemSlavePort::MemSlavePort(const std::string &_name, RubyPort *_port, 158 RubySystem *_system, 159 bool _access_backing_store, PortID id) 160 : QueuedSlavePort(_name, _port, queue, id), queue(*_port, *this), 161 ruby_system(_system), access_backing_store(_access_backing_store) 162{ 163 DPRINTF(RubyPort, "Created slave memport on ruby sequencer %s\n", _name); 164} 165 166bool 167RubyPort::PioMasterPort::recvTimingResp(PacketPtr pkt) 168{ 169 RubyPort *ruby_port = static_cast<RubyPort *>(&owner); 170 DPRINTF(RubyPort, "Response for address: 0x%#x\n", pkt->getAddr()); 171 172 // send next cycle 173 ruby_port->pioSlavePort.schedTimingResp( 174 pkt, curTick() + g_system_ptr->clockPeriod()); 175 return true; 176} 177 178bool RubyPort::MemMasterPort::recvTimingResp(PacketPtr pkt) 179{ 180 // got a response from a device 181 assert(pkt->isResponse()); 182 183 // First we must retrieve the request port from the sender State 184 RubyPort::SenderState *senderState = 185 safe_cast<RubyPort::SenderState *>(pkt->popSenderState()); 186 MemSlavePort *port = senderState->port; 187 assert(port != NULL); 188 delete senderState; 189 190 // In FS mode, ruby memory will receive pio responses from devices 191 // and it must forward these responses back to the particular CPU. 192 DPRINTF(RubyPort, "Pio response for address %#x, going to %s\n", 193 pkt->getAddr(), port->name()); 194 195 // attempt to send the response in the next cycle 196 port->schedTimingResp(pkt, curTick() + g_system_ptr->clockPeriod()); 197 198 return true; 199} 200 201bool 202RubyPort::PioSlavePort::recvTimingReq(PacketPtr pkt) 203{ 204 RubyPort *ruby_port = static_cast<RubyPort *>(&owner); 205 206 for (size_t i = 0; i < ruby_port->master_ports.size(); ++i) { 207 AddrRangeList l = ruby_port->master_ports[i]->getAddrRanges(); 208 for (auto it = l.begin(); it != l.end(); ++it) { 209 if (it->contains(pkt->getAddr())) { 210 // generally it is not safe to assume success here as 211 // the port could be blocked 212 bool M5_VAR_USED success = 213 ruby_port->master_ports[i]->sendTimingReq(pkt); 214 assert(success); 215 return true; 216 } 217 } 218 } 219 panic("Should never reach here!\n"); 220} 221 222bool 223RubyPort::MemSlavePort::recvTimingReq(PacketPtr pkt) 224{ 225 DPRINTF(RubyPort, "Timing request for address %#x on port %d\n", 226 pkt->getAddr(), id); 227 RubyPort *ruby_port = static_cast<RubyPort *>(&owner); 228 229 if (pkt->memInhibitAsserted()) 230 panic("RubyPort should never see an inhibited request\n"); 231 232 // Check for pio requests and directly send them to the dedicated 233 // pio port. 234 if (!isPhysMemAddress(pkt->getAddr())) { 235 assert(ruby_port->memMasterPort.isConnected()); 236 DPRINTF(RubyPort, "Request address %#x assumed to be a pio address\n", 237 pkt->getAddr()); 238 239 // Save the port in the sender state object to be used later to 240 // route the response 241 pkt->pushSenderState(new SenderState(this)); 242 243 // send next cycle 244 ruby_port->memMasterPort.schedTimingReq(pkt, 245 curTick() + g_system_ptr->clockPeriod()); 246 return true; 247 } 248 249 assert(Address(pkt->getAddr()).getOffset() + pkt->getSize() <= 250 RubySystem::getBlockSizeBytes()); 251 252 // Submit the ruby request 253 RequestStatus requestStatus = ruby_port->makeRequest(pkt); 254 255 // If the request successfully issued then we should return true. 256 // Otherwise, we need to tell the port to retry at a later point 257 // and return false. 258 if (requestStatus == RequestStatus_Issued) { 259 // Save the port in the sender state object to be used later to 260 // route the response 261 pkt->pushSenderState(new SenderState(this)); 262 263 DPRINTF(RubyPort, "Request %s 0x%x issued\n", pkt->cmdString(), 264 pkt->getAddr()); 265 return true; 266 } 267 268 // 269 // Unless one is using the ruby tester, record the stalled M5 port for 270 // later retry when the sequencer becomes free. 271 // 272 if (!ruby_port->m_usingRubyTester) { 273 ruby_port->addToRetryList(this); 274 } 275 276 DPRINTF(RubyPort, "Request for address %#x did not issued because %s\n", 277 pkt->getAddr(), RequestStatus_to_string(requestStatus)); 278 279 return false; 280} 281 282void 283RubyPort::MemSlavePort::recvFunctional(PacketPtr pkt) 284{ 285 DPRINTF(RubyPort, "Functional access for address: %#x\n", pkt->getAddr()); 286 287 // Check for pio requests and directly send them to the dedicated 288 // pio port. 289 if (!isPhysMemAddress(pkt->getAddr())) { 290 RubyPort *ruby_port M5_VAR_USED = static_cast<RubyPort *>(&owner); 291 assert(ruby_port->memMasterPort.isConnected()); 292 DPRINTF(RubyPort, "Pio Request for address: 0x%#x\n", pkt->getAddr()); 293 panic("RubyPort::PioMasterPort::recvFunctional() not implemented!\n"); 294 } 295 296 assert(pkt->getAddr() + pkt->getSize() <= 297 line_address(Address(pkt->getAddr())).getAddress() + 298 RubySystem::getBlockSizeBytes()); 299 300 bool accessSucceeded = false; 301 bool needsResponse = pkt->needsResponse(); 302 303 // Do the functional access on ruby memory 304 if (pkt->isRead()) { 305 accessSucceeded = ruby_system->functionalRead(pkt); 306 } else if (pkt->isWrite()) { 307 accessSucceeded = ruby_system->functionalWrite(pkt); 308 } else { 309 panic("Unsupported functional command %s\n", pkt->cmdString()); 310 } 311 312 // Unless the requester explicitly said otherwise, generate an error if 313 // the functional request failed 314 if (!accessSucceeded && !pkt->suppressFuncError()) { 315 fatal("Ruby functional %s failed for address %#x\n", 316 pkt->isWrite() ? "write" : "read", pkt->getAddr()); 317 } 318 319 if (access_backing_store) { 320 // The attached physmem contains the official version of data. 321 // The following command performs the real functional access. 322 // This line should be removed once Ruby supplies the official version 323 // of data. 324 ruby_system->getPhysMem()->functionalAccess(pkt); 325 } 326 327 // turn packet around to go back to requester if response expected 328 if (needsResponse) { 329 pkt->setFunctionalResponseStatus(accessSucceeded); 330 } 331 332 DPRINTF(RubyPort, "Functional access %s!\n", 333 accessSucceeded ? "successful":"failed"); 334} 335 336void 337RubyPort::ruby_hit_callback(PacketPtr pkt) 338{ 339 DPRINTF(RubyPort, "Hit callback for %s 0x%x\n", pkt->cmdString(), 340 pkt->getAddr()); 341 342 // The packet was destined for memory and has not yet been turned 343 // into a response 344 assert(system->isMemAddr(pkt->getAddr())); 345 assert(pkt->isRequest()); 346 347 // First we must retrieve the request port from the sender State 348 RubyPort::SenderState *senderState = 349 safe_cast<RubyPort::SenderState *>(pkt->popSenderState()); 350 MemSlavePort *port = senderState->port; 351 assert(port != NULL); 352 delete senderState; 353 354 port->hitCallback(pkt); 355 356 // 357 // If we had to stall the MemSlavePorts, wake them up because the sequencer 358 // likely has free resources now. 359 // 360 if (!retryList.empty()) { 361 // 362 // Record the current list of ports to retry on a temporary list before 363 // calling sendRetry on those ports. sendRetry will cause an 364 // immediate retry, which may result in the ports being put back on the 365 // list. Therefore we want to clear the retryList before calling 366 // sendRetry. 367 // 368 std::vector<MemSlavePort *> curRetryList(retryList); 369 370 retryList.clear(); 371 372 for (auto i = curRetryList.begin(); i != curRetryList.end(); ++i) { 373 DPRINTF(RubyPort, 374 "Sequencer may now be free. SendRetry to port %s\n", 375 (*i)->name()); 376 (*i)->sendRetry(); 377 } 378 } 379 380 testDrainComplete(); 381} 382 383void 384RubyPort::testDrainComplete() 385{ 386 //If we weren't able to drain before, we might be able to now. 387 if (drainManager != NULL) { 388 unsigned int drainCount = outstandingCount(); 389 DPRINTF(Drain, "Drain count: %u\n", drainCount); 390 if (drainCount == 0) { 391 DPRINTF(Drain, "RubyPort done draining, signaling drain done\n"); 392 drainManager->signalDrainDone(); 393 // Clear the drain manager once we're done with it. 394 drainManager = NULL; 395 } 396 } 397} 398 399unsigned int 400RubyPort::getChildDrainCount(DrainManager *dm) 401{ 402 int count = 0; 403 404 if (memMasterPort.isConnected()) { 405 count += memMasterPort.drain(dm); 406 DPRINTF(Config, "count after pio check %d\n", count); 407 } 408 409 for (CpuPortIter p = slave_ports.begin(); p != slave_ports.end(); ++p) { 410 count += (*p)->drain(dm); 411 DPRINTF(Config, "count after slave port check %d\n", count); 412 } 413 414 for (std::vector<PioMasterPort *>::iterator p = master_ports.begin(); 415 p != master_ports.end(); ++p) { 416 count += (*p)->drain(dm); 417 DPRINTF(Config, "count after master port check %d\n", count); 418 } 419 420 DPRINTF(Config, "final count %d\n", count); 421 return count; 422} 423 424unsigned int 425RubyPort::drain(DrainManager *dm) 426{ 427 if (isDeadlockEventScheduled()) { 428 descheduleDeadlockEvent(); 429 } 430 431 // 432 // If the RubyPort is not empty, then it needs to clear all outstanding 433 // requests before it should call drainManager->signalDrainDone() 434 // 435 DPRINTF(Config, "outstanding count %d\n", outstandingCount()); 436 bool need_drain = outstandingCount() > 0; 437 438 // 439 // Also, get the number of child ports that will also need to clear 440 // their buffered requests before they call drainManager->signalDrainDone() 441 // 442 unsigned int child_drain_count = getChildDrainCount(dm); 443 444 // Set status 445 if (need_drain) { 446 drainManager = dm; 447 448 DPRINTF(Drain, "RubyPort not drained\n"); 449 setDrainState(Drainable::Draining); 450 return child_drain_count + 1; 451 } 452 453 drainManager = NULL; 454 setDrainState(Drainable::Drained); 455 return child_drain_count; 456} 457 458void 459RubyPort::MemSlavePort::hitCallback(PacketPtr pkt) 460{ 461 bool needsResponse = pkt->needsResponse(); 462 463 // Unless specified at configuraiton, all responses except failed SC 464 // and Flush operations access M5 physical memory. 465 bool accessPhysMem = access_backing_store; 466 467 if (pkt->isLLSC()) { 468 if (pkt->isWrite()) { 469 if (pkt->req->getExtraData() != 0) { 470 // 471 // Successful SC packets convert to normal writes 472 // 473 pkt->convertScToWrite(); 474 } else { 475 // 476 // Failed SC packets don't access physical memory and thus 477 // the RubyPort itself must convert it to a response. 478 // 479 accessPhysMem = false; 480 } 481 } else { 482 // 483 // All LL packets convert to normal loads so that M5 PhysMem does 484 // not lock the blocks. 485 // 486 pkt->convertLlToRead(); 487 } 488 } 489 490 // Flush requests don't access physical memory 491 if (pkt->isFlush()) { 492 accessPhysMem = false; 493 } 494 495 DPRINTF(RubyPort, "Hit callback needs response %d\n", needsResponse); 496 497 if (accessPhysMem) { 498 ruby_system->getPhysMem()->functionalAccess(pkt); 499 } else if (needsResponse) { 500 pkt->makeResponse(); 501 } 502 503 // turn packet around to go back to requester if response expected 504 if (needsResponse) { 505 DPRINTF(RubyPort, "Sending packet back over port\n"); 506 // send next cycle 507 schedTimingResp(pkt, curTick() + g_system_ptr->clockPeriod()); 508 } else { 509 delete pkt; 510 } 511 512 DPRINTF(RubyPort, "Hit callback done!\n"); 513} 514 515AddrRangeList 516RubyPort::PioSlavePort::getAddrRanges() const 517{ 518 // at the moment the assumption is that the master does not care 519 AddrRangeList ranges; 520 RubyPort *ruby_port = static_cast<RubyPort *>(&owner); 521 522 for (size_t i = 0; i < ruby_port->master_ports.size(); ++i) { 523 ranges.splice(ranges.begin(), 524 ruby_port->master_ports[i]->getAddrRanges()); 525 } 526 for (const auto M5_VAR_USED &r : ranges) 527 DPRINTF(RubyPort, "%s\n", r.to_string()); 528 return ranges; 529} 530 531bool 532RubyPort::MemSlavePort::isPhysMemAddress(Addr addr) const 533{ 534 RubyPort *ruby_port = static_cast<RubyPort *>(&owner); 535 return ruby_port->system->isMemAddr(addr); 536} 537 538void 539RubyPort::ruby_eviction_callback(const Address& address) 540{ 541 DPRINTF(RubyPort, "Sending invalidations.\n"); 542 // This request is deleted in the stack-allocated packet destructor 543 // when this function exits 544 // TODO: should this really be using funcMasterId? 545 RequestPtr req = 546 new Request(address.getAddress(), 0, 0, Request::funcMasterId); 547 // Use a single packet to signal all snooping ports of the invalidation. 548 // This assumes that snooping ports do NOT modify the packet/request 549 Packet pkt(req, MemCmd::InvalidationReq); 550 for (CpuPortIter p = slave_ports.begin(); p != slave_ports.end(); ++p) { 551 // check if the connected master port is snooping 552 if ((*p)->isSnooping()) { 553 // send as a snoop request 554 (*p)->sendTimingSnoopReq(&pkt); 555 } 556 } 557} 558 559void 560RubyPort::PioMasterPort::recvRangeChange() 561{ 562 RubyPort &r = static_cast<RubyPort &>(owner); 563 r.gotAddrRanges--; 564 if (r.gotAddrRanges == 0 && FullSystem) { 565 r.pioSlavePort.sendRangeChange(); 566 } 567} 568