PerfectCacheMemory.hh revision 6467
12810SN/A
29725Sandreas.hansson@arm.com/*
39347SAndreas.Sandberg@arm.com * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
49347SAndreas.Sandberg@arm.com * All rights reserved.
59347SAndreas.Sandberg@arm.com *
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79347SAndreas.Sandberg@arm.com * modification, are permitted provided that the following conditions are
89347SAndreas.Sandberg@arm.com * met: redistributions of source code must retain the above copyright
99347SAndreas.Sandberg@arm.com * notice, this list of conditions and the following disclaimer;
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142810SN/A * contributors may be used to endorse or promote products derived from
152810SN/A * this software without specific prior written permission.
162810SN/A *
172810SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
182810SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
192810SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
202810SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
212810SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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272810SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
282810SN/A */
292810SN/A
302810SN/A/*
312810SN/A * PerfectCacheMemory.hh
322810SN/A *
332810SN/A * Description:
342810SN/A *
352810SN/A * $Id$
362810SN/A *
372810SN/A */
382810SN/A
392810SN/A#ifndef PERFECTCACHEMEMORY_H
402810SN/A#define PERFECTCACHEMEMORY_H
419347SAndreas.Sandberg@arm.com
422810SN/A#include "mem/ruby/common/Global.hh"
432810SN/A#include "mem/gems_common/Map.hh"
442810SN/A#include "mem/protocol/AccessPermission.hh"
452810SN/A#include "mem/ruby/common/Address.hh"
462810SN/A
472810SN/Atemplate<class ENTRY>
484626SN/Aclass PerfectCacheLineState {
494626SN/Apublic:
502810SN/A  PerfectCacheLineState() { m_permission = AccessPermission_NUM; }
512810SN/A  AccessPermission m_permission;
524626SN/A  ENTRY m_entry;
538229Snate@binkert.org};
544626SN/A
559347SAndreas.Sandberg@arm.comtemplate<class ENTRY>
562810SN/Aextern inline
572810SN/Aostream& operator<<(ostream& out, const PerfectCacheLineState<ENTRY>& obj)
583374SN/A{
592810SN/A  return out;
609347SAndreas.Sandberg@arm.com}
614626SN/A
622810SN/Atemplate<class ENTRY>
635314SN/Aclass PerfectCacheMemory {
645314SN/Apublic:
655314SN/A
662810SN/A  // Constructors
672810SN/A  PerfectCacheMemory();
684626SN/A
694626SN/A  // Destructor
704626SN/A  //~PerfectCacheMemory();
712810SN/A
724626SN/A  // Public Methods
732810SN/A
742810SN/A  static void printConfig(ostream& out);
754626SN/A
764626SN/A  // perform a cache access and see if we hit or not.  Return true on
772810SN/A  // a hit.
782810SN/A  bool tryCacheAccess(const CacheMsg& msg, bool& block_stc, ENTRY*& entry);
792810SN/A
8010622Smitch.hayenga@arm.com  // tests to see if an address is present in the cache
8110622Smitch.hayenga@arm.com  bool isTagPresent(const Address& address) const;
8210622Smitch.hayenga@arm.com
8310622Smitch.hayenga@arm.com  // Returns true if there is:
8410622Smitch.hayenga@arm.com  //   a) a tag match on this address or there is
8510622Smitch.hayenga@arm.com  //   b) an Invalid line in the same cache "way"
869725Sandreas.hansson@arm.com  bool cacheAvail(const Address& address) const;
879725Sandreas.hansson@arm.com
889725Sandreas.hansson@arm.com  // find an Invalid entry and sets the tag appropriate for the address
899725Sandreas.hansson@arm.com  void allocate(const Address& address);
909725Sandreas.hansson@arm.com
919725Sandreas.hansson@arm.com  void deallocate(const Address& address);
929725Sandreas.hansson@arm.com
939725Sandreas.hansson@arm.com  // Returns with the physical address of the conflicting cache line
949725Sandreas.hansson@arm.com  Address cacheProbe(const Address& newAddress) const;
959347SAndreas.Sandberg@arm.com
969347SAndreas.Sandberg@arm.com  // looks an address up in the cache
979347SAndreas.Sandberg@arm.com  ENTRY& lookup(const Address& address);
984666SN/A  const ENTRY& lookup(const Address& address) const;
994666SN/A
1004666SN/A  // Get/Set permission of cache block
1012810SN/A  AccessPermission getPermission(const Address& address) const;
1024626SN/A  void changePermission(const Address& address, AccessPermission new_perm);
1032810SN/A
1044626SN/A  // Print cache contents
1054626SN/A  void print(ostream& out) const;
1064628SN/Aprivate:
1074628SN/A  // Private Methods
1084628SN/A
1092810SN/A  // Private copy constructor and assignment operator
1102810SN/A  PerfectCacheMemory(const PerfectCacheMemory& obj);
1114626SN/A  PerfectCacheMemory& operator=(const PerfectCacheMemory& obj);
1124626SN/A
1134626SN/A  // Data Members (m_prefix)
1144626SN/A  Map<Address, PerfectCacheLineState<ENTRY> > m_map;
11510622Smitch.hayenga@arm.com};
11610622Smitch.hayenga@arm.com
1172810SN/A// Output operator declaration
1185314SN/A//ostream& operator<<(ostream& out, const PerfectCacheMemory<ENTRY>& obj);
11910622Smitch.hayenga@arm.com
1202810SN/A// ******************* Definitions *******************
1212810SN/A
1224626SN/A// Output operator definition
1232810SN/Atemplate<class ENTRY>
12410028SGiacomo.Gabrielli@arm.comextern inline
1252810SN/Aostream& operator<<(ostream& out, const PerfectCacheMemory<ENTRY>& obj)
1262810SN/A{
12710028SGiacomo.Gabrielli@arm.com  obj.print(out);
1282810SN/A  out << flush;
1292810SN/A  return out;
1304626SN/A}
1312810SN/A
13210028SGiacomo.Gabrielli@arm.com
1334626SN/A// ****************************************************************
1342810SN/A
1352810SN/Atemplate<class ENTRY>
1362810SN/Aextern inline
13710028SGiacomo.Gabrielli@arm.comPerfectCacheMemory<ENTRY>::PerfectCacheMemory()
13810028SGiacomo.Gabrielli@arm.com{
1392810SN/A}
1402810SN/A
1413374SN/A// STATIC METHODS
1422982SN/A
14310028SGiacomo.Gabrielli@arm.comtemplate<class ENTRY>
1442810SN/Aextern inline
1452810SN/Avoid PerfectCacheMemory<ENTRY>::printConfig(ostream& out)
14610028SGiacomo.Gabrielli@arm.com{
1472810SN/A}
1484920SN/A
1494920SN/A// PUBLIC METHODS
1502810SN/A
1513374SN/Atemplate<class ENTRY>
1522810SN/Aextern inline
1532982SN/Abool PerfectCacheMemory<ENTRY>::tryCacheAccess(const CacheMsg& msg, bool& block_stc, ENTRY*& entry)
1542810SN/A{
1552810SN/A  ERROR_MSG("not implemented");
1562810SN/A}
1574626SN/A
1582810SN/A// tests to see if an address is present in the cache
1594666SN/Atemplate<class ENTRY>
1604666SN/Aextern inline
1612810SN/Abool PerfectCacheMemory<ENTRY>::isTagPresent(const Address& address) const
1622810SN/A{
1632810SN/A  return m_map.exist(line_address(address));
1642810SN/A}
1652810SN/A
1662810SN/Atemplate<class ENTRY>
1674626SN/Aextern inline
1682810SN/Abool PerfectCacheMemory<ENTRY>::cacheAvail(const Address& address) const
1692810SN/A{
1704626SN/A  return true;
1714626SN/A}
1722810SN/A
1732810SN/A// find an Invalid or already allocated entry and sets the tag
1742810SN/A// appropriate for the address
1754626SN/Atemplate<class ENTRY>
1762810SN/Aextern inline
1772810SN/Avoid PerfectCacheMemory<ENTRY>::allocate(const Address& address)
1784626SN/A{
1794626SN/A  PerfectCacheLineState<ENTRY> line_state;
1804626SN/A  line_state.m_permission = AccessPermission_Busy;
1812810SN/A  line_state.m_entry = ENTRY();
1822810SN/A  m_map.add(line_address(address), line_state);
1832810SN/A}
1842810SN/A
1852810SN/A// deallocate entry
18610679Sandreas.hansson@arm.comtemplate<class ENTRY>
18710679Sandreas.hansson@arm.comextern inline
1882810SN/Avoid PerfectCacheMemory<ENTRY>::deallocate(const Address& address)
18910679Sandreas.hansson@arm.com{
19010679Sandreas.hansson@arm.com  m_map.erase(line_address(address));
1912810SN/A}
19210679Sandreas.hansson@arm.com
1932810SN/A// Returns with the physical address of the conflicting cache line
1942810SN/Atemplate<class ENTRY>
1954626SN/Aextern inline
1962810SN/AAddress PerfectCacheMemory<ENTRY>::cacheProbe(const Address& newAddress) const
1972810SN/A{
1984626SN/A  ERROR_MSG("cacheProbe called in perfect cache");
1992810SN/A}
2002810SN/A
2013374SN/A// looks an address up in the cache
2022810SN/Atemplate<class ENTRY>
2032982SN/Aextern inline
2042810SN/AENTRY& PerfectCacheMemory<ENTRY>::lookup(const Address& address)
2052812SN/A{
2062810SN/A  return m_map.lookup(line_address(address)).m_entry;
2072810SN/A}
20810192Smitch.hayenga@arm.com
20910192Smitch.hayenga@arm.com// looks an address up in the cache
21010192Smitch.hayenga@arm.comtemplate<class ENTRY>
21110192Smitch.hayenga@arm.comextern inline
21210192Smitch.hayenga@arm.comconst ENTRY& PerfectCacheMemory<ENTRY>::lookup(const Address& address) const
21310192Smitch.hayenga@arm.com{
2142810SN/A  return m_map.lookup(line_address(address)).m_entry;
2153374SN/A}
2162810SN/A
2172810SN/Atemplate<class ENTRY>
2182810SN/Aextern inline
2194666SN/AAccessPermission PerfectCacheMemory<ENTRY>::getPermission(const Address& address) const
2202810SN/A{
2212810SN/A  return m_map.lookup(line_address(address)).m_permission;
2222810SN/A}
2234626SN/A
2242810SN/Atemplate<class ENTRY>
2252810SN/Aextern inline
2262810SN/Avoid PerfectCacheMemory<ENTRY>::changePermission(const Address& address, AccessPermission new_perm)
2272810SN/A{
2284626SN/A  Address line_address = address;
2292810SN/A  line_address.makeLineAddress();
2302810SN/A  PerfectCacheLineState<ENTRY>& line_state = m_map.lookup(line_address);
2312810SN/A  AccessPermission old_perm = line_state.m_permission;
23210622Smitch.hayenga@arm.com  line_state.m_permission = new_perm;
23310622Smitch.hayenga@arm.com}
23410622Smitch.hayenga@arm.com
23510622Smitch.hayenga@arm.comtemplate<class ENTRY>
23610622Smitch.hayenga@arm.comextern inline
23710622Smitch.hayenga@arm.comvoid PerfectCacheMemory<ENTRY>::print(ostream& out) const
23810622Smitch.hayenga@arm.com{
23910622Smitch.hayenga@arm.com}
24010622Smitch.hayenga@arm.com
2414666SN/A#endif //PERFECTCACHEMEMORY_H
2423374SN/A