PerfectCacheMemory.hh revision 6467 
1
2/*
3 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;
10 * redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution;
13 * neither the name of the copyright holders nor the names of its
14 * contributors may be used to endorse or promote products derived from
15 * this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 */
29
30/*
31 * PerfectCacheMemory.hh
32 *
33 * Description:
34 *
35 * $Id$
36 *
37 */
38
39#ifndef PERFECTCACHEMEMORY_H
40#define PERFECTCACHEMEMORY_H
41
42#include "mem/ruby/common/Global.hh"
43#include "mem/gems_common/Map.hh"
44#include "mem/protocol/AccessPermission.hh"
45#include "mem/ruby/common/Address.hh"
46
47template<class ENTRY>
48class PerfectCacheLineState {
49public:
50  PerfectCacheLineState() { m_permission = AccessPermission_NUM; }
51  AccessPermission m_permission;
52  ENTRY m_entry;
53};
54
55template<class ENTRY>
56extern inline
57ostream& operator<<(ostream& out, const PerfectCacheLineState<ENTRY>& obj)
58{
59  return out;
60}
61
62template<class ENTRY>
63class PerfectCacheMemory {
64public:
65
66  // Constructors
67  PerfectCacheMemory();
68
69  // Destructor
70  //~PerfectCacheMemory();
71
72  // Public Methods
73
74  static void printConfig(ostream& out);
75
76  // perform a cache access and see if we hit or not.  Return true on
77  // a hit.
78  bool tryCacheAccess(const CacheMsg& msg, bool& block_stc, ENTRY*& entry);
79
80  // tests to see if an address is present in the cache
81  bool isTagPresent(const Address& address) const;
82
83  // Returns true if there is:
84  //   a) a tag match on this address or there is
85  //   b) an Invalid line in the same cache "way"
86  bool cacheAvail(const Address& address) const;
87
88  // find an Invalid entry and sets the tag appropriate for the address
89  void allocate(const Address& address);
90
91  void deallocate(const Address& address);
92
93  // Returns with the physical address of the conflicting cache line
94  Address cacheProbe(const Address& newAddress) const;
95
96  // looks an address up in the cache
97  ENTRY& lookup(const Address& address);
98  const ENTRY& lookup(const Address& address) const;
99
100  // Get/Set permission of cache block
101  AccessPermission getPermission(const Address& address) const;
102  void changePermission(const Address& address, AccessPermission new_perm);
103
104  // Print cache contents
105  void print(ostream& out) const;
106private:
107  // Private Methods
108
109  // Private copy constructor and assignment operator
110  PerfectCacheMemory(const PerfectCacheMemory& obj);
111  PerfectCacheMemory& operator=(const PerfectCacheMemory& obj);
112
113  // Data Members (m_prefix)
114  Map<Address, PerfectCacheLineState<ENTRY> > m_map;
115};
116
117// Output operator declaration
118//ostream& operator<<(ostream& out, const PerfectCacheMemory<ENTRY>& obj);
119
120// ******************* Definitions *******************
121
122// Output operator definition
123template<class ENTRY>
124extern inline
125ostream& operator<<(ostream& out, const PerfectCacheMemory<ENTRY>& obj)
126{
127  obj.print(out);
128  out << flush;
129  return out;
130}
131
132
133// ****************************************************************
134
135template<class ENTRY>
136extern inline
137PerfectCacheMemory<ENTRY>::PerfectCacheMemory()
138{
139}
140
141// STATIC METHODS
142
143template<class ENTRY>
144extern inline
145void PerfectCacheMemory<ENTRY>::printConfig(ostream& out)
146{
147}
148
149// PUBLIC METHODS
150
151template<class ENTRY>
152extern inline
153bool PerfectCacheMemory<ENTRY>::tryCacheAccess(const CacheMsg& msg, bool& block_stc, ENTRY*& entry)
154{
155  ERROR_MSG("not implemented");
156}
157
158// tests to see if an address is present in the cache
159template<class ENTRY>
160extern inline
161bool PerfectCacheMemory<ENTRY>::isTagPresent(const Address& address) const
162{
163  return m_map.exist(line_address(address));
164}
165
166template<class ENTRY>
167extern inline
168bool PerfectCacheMemory<ENTRY>::cacheAvail(const Address& address) const
169{
170  return true;
171}
172
173// find an Invalid or already allocated entry and sets the tag
174// appropriate for the address
175template<class ENTRY>
176extern inline
177void PerfectCacheMemory<ENTRY>::allocate(const Address& address)
178{
179  PerfectCacheLineState<ENTRY> line_state;
180  line_state.m_permission = AccessPermission_Busy;
181  line_state.m_entry = ENTRY();
182  m_map.add(line_address(address), line_state);
183}
184
185// deallocate entry
186template<class ENTRY>
187extern inline
188void PerfectCacheMemory<ENTRY>::deallocate(const Address& address)
189{
190  m_map.erase(line_address(address));
191}
192
193// Returns with the physical address of the conflicting cache line
194template<class ENTRY>
195extern inline
196Address PerfectCacheMemory<ENTRY>::cacheProbe(const Address& newAddress) const
197{
198  ERROR_MSG("cacheProbe called in perfect cache");
199}
200
201// looks an address up in the cache
202template<class ENTRY>
203extern inline
204ENTRY& PerfectCacheMemory<ENTRY>::lookup(const Address& address)
205{
206  return m_map.lookup(line_address(address)).m_entry;
207}
208
209// looks an address up in the cache
210template<class ENTRY>
211extern inline
212const ENTRY& PerfectCacheMemory<ENTRY>::lookup(const Address& address) const
213{
214  return m_map.lookup(line_address(address)).m_entry;
215}
216
217template<class ENTRY>
218extern inline
219AccessPermission PerfectCacheMemory<ENTRY>::getPermission(const Address& address) const
220{
221  return m_map.lookup(line_address(address)).m_permission;
222}
223
224template<class ENTRY>
225extern inline
226void PerfectCacheMemory<ENTRY>::changePermission(const Address& address, AccessPermission new_perm)
227{
228  Address line_address = address;
229  line_address.makeLineAddress();
230  PerfectCacheLineState<ENTRY>& line_state = m_map.lookup(line_address);
231  AccessPermission old_perm = line_state.m_permission;
232  line_state.m_permission = new_perm;
233}
234
235template<class ENTRY>
236extern inline
237void PerfectCacheMemory<ENTRY>::print(ostream& out) const
238{
239}
240
241#endif //PERFECTCACHEMEMORY_H
242