BankedArray.hh revision 9184 
112771Sqtt2@cornell.edu/*
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2812771Sqtt2@cornell.edu * Author: Brad Beckmann
2912771Sqtt2@cornell.edu *
3012771Sqtt2@cornell.edu */
3112771Sqtt2@cornell.edu
3212771Sqtt2@cornell.edu#ifndef __MEM_RUBY_SYSTEM_BANKEDARRAY_HH__
3312771Sqtt2@cornell.edu#define __MEM_RUBY_SYSTEM_BANKEDARRAY_HH__
3412771Sqtt2@cornell.edu
3512771Sqtt2@cornell.edu#include <vector>
3612771Sqtt2@cornell.edu
3712771Sqtt2@cornell.edu#include "mem/ruby/common/TypeDefines.hh"
3812771Sqtt2@cornell.edu#include "sim/eventq.hh"
3912771Sqtt2@cornell.edu
4012771Sqtt2@cornell.edu
4112771Sqtt2@cornell.edu
4212771Sqtt2@cornell.educlass BankedArray : public EventManager
4312771Sqtt2@cornell.edu{
4412771Sqtt2@cornell.eduprivate:
4512771Sqtt2@cornell.edu    unsigned int banks;
4612771Sqtt2@cornell.edu    Cycles accessLatency;
4712771Sqtt2@cornell.edu    unsigned int bankBits;
4812771Sqtt2@cornell.edu    unsigned int startIndexBit;
49
50    //std::vector<bool> busyBanks;
51
52    class TickEvent : public Event
53    {
54    public:
55        TickEvent() : Event() {}
56        void process() {}
57        Index idx;
58        Tick startAccess;
59    };
60    friend class TickEvent;
61
62    // If the tick event is scheduled then the bank is busy
63    // otherwise, schedule the event and wait for it to complete
64    std::vector<TickEvent> busyBanks;
65
66    unsigned int mapIndexToBank(Index idx);
67
68public:
69    BankedArray(unsigned int banks, Cycles accessLatency, unsigned int startIndexBit);
70
71    // Note: We try the access based on the cache index, not the address
72    // This is so we don't get aliasing on blocks being replaced
73    bool tryAccess(Index idx);
74
75};
76
77#endif
78