BankedArray.cc revision 9155
12600SN/A/* 22600SN/A * Copyright (c) 2012 Advanced Micro Devices, Inc. 32600SN/A * All rights reserved. 42600SN/A * 52600SN/A * Redistribution and use in source and binary forms, with or without 62600SN/A * modification, are permitted provided that the following conditions are 72600SN/A * met: redistributions of source code must retain the above copyright 82600SN/A * notice, this list of conditions and the following disclaimer; 92600SN/A * redistributions in binary form must reproduce the above copyright 102600SN/A * notice, this list of conditions and the following disclaimer in the 112600SN/A * documentation and/or other materials provided with the distribution; 122600SN/A * neither the name of the copyright holders nor the names of its 132600SN/A * contributors may be used to endorse or promote products derived from 142600SN/A * this software without specific prior written permission. 152600SN/A * 162600SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172600SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182600SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192600SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202600SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212600SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222600SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232600SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242600SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252600SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262600SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Author: Brad Beckmann 292600SN/A * 302600SN/A */ 312600SN/A 322600SN/A#include <vector> 332600SN/A 342600SN/A#include "base/intmath.hh" 352600SN/A#include "mem/ruby/common/TypeDefines.hh" 362600SN/A#include "mem/ruby/system/BankedArray.hh" 372600SN/A#include "sim/eventq.hh" 382600SN/A 392600SN/ABankedArray::BankedArray(unsigned int banks, unsigned int accessLatency, unsigned int startIndexBit) : 402600SN/A EventManager(&mainEventQueue) 413113Sgblack@eecs.umich.edu{ 422600SN/A this->banks = banks; 433113Sgblack@eecs.umich.edu this->accessLatency = accessLatency; 442600SN/A this->startIndexBit = startIndexBit; 452600SN/A 462600SN/A if (banks != 0) { 472600SN/A bankBits = floorLog2(banks); 482600SN/A } 492600SN/A 502600SN/A busyBanks.resize(banks); 512600SN/A} 523113Sgblack@eecs.umich.edu 533113Sgblack@eecs.umich.edubool 542600SN/ABankedArray::tryAccess(Index idx) 552600SN/A{ 562600SN/A if (accessLatency == 0) 572600SN/A return true; 582600SN/A 593122Sgblack@eecs.umich.edu unsigned int bank = mapIndexToBank(idx); 602600SN/A assert(bank < banks); 612600SN/A 622600SN/A if (busyBanks[bank].scheduled()) { 632600SN/A if (!(busyBanks[bank].startAccess == curTick() && busyBanks[bank].idx == idx)) { 642600SN/A return false; 652600SN/A } else { 662600SN/A return true; // We tried to allocate resources twice in the same cycle for the same addr 672600SN/A } 683122Sgblack@eecs.umich.edu } 692600SN/A 702600SN/A busyBanks[bank].idx = idx; 712600SN/A busyBanks[bank].startAccess = curTick(); 722600SN/A 732600SN/A // substract 1 so that next cycle the resource available 742600SN/A schedule(busyBanks[bank], curTick()+accessLatency-1); 752600SN/A 762600SN/A return true; 772600SN/A} 783113Sgblack@eecs.umich.edu 795543Ssaidi@eecs.umich.eduunsigned int 805543Ssaidi@eecs.umich.eduBankedArray::mapIndexToBank(Index idx) 815543Ssaidi@eecs.umich.edu{ 825543Ssaidi@eecs.umich.edu if (banks == 1) { 835543Ssaidi@eecs.umich.edu return 0; 845543Ssaidi@eecs.umich.edu } 855543Ssaidi@eecs.umich.edu return idx % banks; 865543Ssaidi@eecs.umich.edu} 875543Ssaidi@eecs.umich.edu