AbstractController.hh revision 11448
1/* 2 * Copyright (c) 2009-2014 Mark D. Hill and David A. Wood 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29#ifndef __MEM_RUBY_SLICC_INTERFACE_ABSTRACTCONTROLLER_HH__ 30#define __MEM_RUBY_SLICC_INTERFACE_ABSTRACTCONTROLLER_HH__ 31 32#include <exception> 33#include <iostream> 34#include <string> 35 36#include "base/callback.hh" 37#include "mem/protocol/AccessPermission.hh" 38#include "mem/ruby/common/Address.hh" 39#include "mem/ruby/common/Consumer.hh" 40#include "mem/ruby/common/DataBlock.hh" 41#include "mem/ruby/common/Histogram.hh" 42#include "mem/ruby/common/MachineID.hh" 43#include "mem/ruby/network/MessageBuffer.hh" 44#include "mem/ruby/network/Network.hh" 45#include "mem/ruby/system/CacheRecorder.hh" 46#include "mem/packet.hh" 47#include "mem/qport.hh" 48#include "params/RubyController.hh" 49#include "mem/mem_object.hh" 50 51class Network; 52class GPUCoalescer; 53 54// used to communicate that an in_port peeked the wrong message type 55class RejectException: public std::exception 56{ 57 virtual const char* what() const throw() 58 { return "Port rejected message based on type"; } 59}; 60 61class AbstractController : public MemObject, public Consumer 62{ 63 public: 64 typedef RubyControllerParams Params; 65 AbstractController(const Params *p); 66 void init(); 67 const Params *params() const { return (const Params *)_params; } 68 69 NodeID getVersion() const { return m_machineID.getNum(); } 70 MachineType getType() const { return m_machineID.getType(); } 71 72 void initNetworkPtr(Network* net_ptr) { m_net_ptr = net_ptr; } 73 74 // return instance name 75 void blockOnQueue(Addr, MessageBuffer*); 76 bool isBlocked(Addr) const; 77 void unblock(Addr); 78 bool isBlocked(Addr); 79 80 virtual MessageBuffer* getMandatoryQueue() const = 0; 81 virtual MessageBuffer* getMemoryQueue() const = 0; 82 virtual AccessPermission getAccessPermission(const Addr &addr) = 0; 83 84 virtual void print(std::ostream & out) const = 0; 85 virtual void wakeup() = 0; 86 virtual void resetStats() = 0; 87 virtual void regStats(); 88 89 virtual void recordCacheTrace(int cntrl, CacheRecorder* tr) = 0; 90 virtual Sequencer* getCPUSequencer() const = 0; 91 virtual GPUCoalescer* getGPUCoalescer() const = 0; 92 93 //! These functions are used by ruby system to read/write the data blocks 94 //! that exist with in the controller. 95 virtual void functionalRead(const Addr &addr, PacketPtr) = 0; 96 void functionalMemoryRead(PacketPtr); 97 //! The return value indicates the number of messages written with the 98 //! data from the packet. 99 virtual int functionalWriteBuffers(PacketPtr&) = 0; 100 virtual int functionalWrite(const Addr &addr, PacketPtr) = 0; 101 int functionalMemoryWrite(PacketPtr); 102 103 //! Function for enqueuing a prefetch request 104 virtual void enqueuePrefetch(const Addr &, const RubyRequestType&) 105 { fatal("Prefetches not implemented!");} 106 107 //! Function for collating statistics from all the controllers of this 108 //! particular type. This function should only be called from the 109 //! version 0 of this controller type. 110 virtual void collateStats() 111 {fatal("collateStats() should be overridden!");} 112 113 //! Initialize the message buffers. 114 virtual void initNetQueues() = 0; 115 116 /** A function used to return the port associated with this bus object. */ 117 BaseMasterPort& getMasterPort(const std::string& if_name, 118 PortID idx = InvalidPortID); 119 120 void queueMemoryRead(const MachineID &id, Addr addr, Cycles latency); 121 void queueMemoryWrite(const MachineID &id, Addr addr, Cycles latency, 122 const DataBlock &block); 123 void queueMemoryWritePartial(const MachineID &id, Addr addr, Cycles latency, 124 const DataBlock &block, int size); 125 void recvTimingResp(PacketPtr pkt); 126 127 public: 128 MachineID getMachineID() const { return m_machineID; } 129 130 Stats::Histogram& getDelayHist() { return m_delayHistogram; } 131 Stats::Histogram& getDelayVCHist(uint32_t index) 132 { return *(m_delayVCHistogram[index]); } 133 134 protected: 135 //! Profiles original cache requests including PUTs 136 void profileRequest(const std::string &request); 137 //! Profiles the delay associated with messages. 138 void profileMsgDelay(uint32_t virtualNetwork, Cycles delay); 139 140 void stallBuffer(MessageBuffer* buf, Addr addr); 141 void wakeUpBuffers(Addr addr); 142 void wakeUpAllBuffers(Addr addr); 143 void wakeUpAllBuffers(); 144 145 protected: 146 const NodeID m_version; 147 MachineID m_machineID; 148 const NodeID m_clusterID; 149 150 // MasterID used by some components of gem5. 151 const MasterID m_masterId; 152 153 Network *m_net_ptr; 154 bool m_is_blocking; 155 std::map<Addr, MessageBuffer*> m_block_map; 156 157 typedef std::vector<MessageBuffer*> MsgVecType; 158 typedef std::set<MessageBuffer*> MsgBufType; 159 typedef std::map<Addr, MsgVecType* > WaitingBufType; 160 WaitingBufType m_waiting_buffers; 161 162 unsigned int m_in_ports; 163 unsigned int m_cur_in_port; 164 const int m_number_of_TBEs; 165 const int m_transitions_per_cycle; 166 const unsigned int m_buffer_size; 167 Cycles m_recycle_latency; 168 169 //! Counter for the number of cycles when the transitions carried out 170 //! were equal to the maximum allowed 171 Stats::Scalar m_fully_busy_cycles; 172 173 //! Histogram for profiling delay for the messages this controller 174 //! cares for 175 Stats::Histogram m_delayHistogram; 176 std::vector<Stats::Histogram *> m_delayVCHistogram; 177 178 //! Callback class used for collating statistics from all the 179 //! controller of this type. 180 class StatsCallback : public Callback 181 { 182 private: 183 AbstractController *ctr; 184 185 public: 186 virtual ~StatsCallback() {} 187 StatsCallback(AbstractController *_ctr) : ctr(_ctr) {} 188 void process() {ctr->collateStats();} 189 }; 190 191 /** 192 * Port that forwards requests and receives responses from the 193 * memory controller. It has a queue of packets not yet sent. 194 */ 195 class MemoryPort : public QueuedMasterPort 196 { 197 private: 198 // Packet queues used to store outgoing requests and snoop responses. 199 ReqPacketQueue reqQueue; 200 SnoopRespPacketQueue snoopRespQueue; 201 202 // Controller that operates this port. 203 AbstractController *controller; 204 205 public: 206 MemoryPort(const std::string &_name, AbstractController *_controller, 207 const std::string &_label); 208 209 // Function for receiving a timing response from the peer port. 210 // Currently the pkt is handed to the coherence controller 211 // associated with this port. 212 bool recvTimingResp(PacketPtr pkt); 213 }; 214 215 /* Master port to the memory controller. */ 216 MemoryPort memoryPort; 217 218 // State that is stored in packets sent to the memory controller. 219 struct SenderState : public Packet::SenderState 220 { 221 // Id of the machine from which the request originated. 222 MachineID id; 223 224 SenderState(MachineID _id) : id(_id) 225 {} 226 }; 227}; 228 229#endif // __MEM_RUBY_SLICC_INTERFACE_ABSTRACTCONTROLLER_HH__ 230