AbstractController.hh revision 11308
1/* 2 * Copyright (c) 2009-2014 Mark D. Hill and David A. Wood 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29#ifndef __MEM_RUBY_SLICC_INTERFACE_ABSTRACTCONTROLLER_HH__ 30#define __MEM_RUBY_SLICC_INTERFACE_ABSTRACTCONTROLLER_HH__ 31 32#include <exception> 33#include <iostream> 34#include <string> 35 36#include "base/callback.hh" 37#include "mem/protocol/AccessPermission.hh" 38#include "mem/ruby/common/Address.hh" 39#include "mem/ruby/common/Consumer.hh" 40#include "mem/ruby/common/DataBlock.hh" 41#include "mem/ruby/common/Histogram.hh" 42#include "mem/ruby/common/MachineID.hh" 43#include "mem/ruby/network/MessageBuffer.hh" 44#include "mem/ruby/network/Network.hh" 45#include "mem/ruby/system/CacheRecorder.hh" 46#include "mem/packet.hh" 47#include "mem/qport.hh" 48#include "params/RubyController.hh" 49#include "mem/mem_object.hh" 50 51class Network; 52 53// used to communicate that an in_port peeked the wrong message type 54class RejectException: public std::exception 55{ 56 virtual const char* what() const throw() 57 { return "Port rejected message based on type"; } 58}; 59 60class AbstractController : public MemObject, public Consumer 61{ 62 public: 63 typedef RubyControllerParams Params; 64 AbstractController(const Params *p); 65 void init(); 66 const Params *params() const { return (const Params *)_params; } 67 68 NodeID getVersion() const { return m_machineID.getNum(); } 69 MachineType getType() const { return m_machineID.getType(); } 70 71 void initNetworkPtr(Network* net_ptr) { m_net_ptr = net_ptr; } 72 73 // return instance name 74 void blockOnQueue(Addr, MessageBuffer*); 75 void unblock(Addr); 76 bool isBlocked(Addr); 77 78 virtual MessageBuffer* getMandatoryQueue() const = 0; 79 virtual MessageBuffer* getMemoryQueue() const = 0; 80 virtual AccessPermission getAccessPermission(const Addr &addr) = 0; 81 82 virtual void print(std::ostream & out) const = 0; 83 virtual void wakeup() = 0; 84 virtual void resetStats() = 0; 85 virtual void regStats(); 86 87 virtual void recordCacheTrace(int cntrl, CacheRecorder* tr) = 0; 88 virtual Sequencer* getCPUSequencer() const = 0; 89 90 //! These functions are used by ruby system to read/write the data blocks 91 //! that exist with in the controller. 92 virtual void functionalRead(const Addr &addr, PacketPtr) = 0; 93 void functionalMemoryRead(PacketPtr); 94 //! The return value indicates the number of messages written with the 95 //! data from the packet. 96 virtual int functionalWriteBuffers(PacketPtr&) = 0; 97 virtual int functionalWrite(const Addr &addr, PacketPtr) = 0; 98 int functionalMemoryWrite(PacketPtr); 99 100 //! Function for enqueuing a prefetch request 101 virtual void enqueuePrefetch(const Addr &, const RubyRequestType&) 102 { fatal("Prefetches not implemented!");} 103 104 //! Function for collating statistics from all the controllers of this 105 //! particular type. This function should only be called from the 106 //! version 0 of this controller type. 107 virtual void collateStats() 108 {fatal("collateStats() should be overridden!");} 109 110 //! Initialize the message buffers. 111 virtual void initNetQueues() = 0; 112 113 /** A function used to return the port associated with this bus object. */ 114 BaseMasterPort& getMasterPort(const std::string& if_name, 115 PortID idx = InvalidPortID); 116 117 void queueMemoryRead(const MachineID &id, Addr addr, Cycles latency); 118 void queueMemoryWrite(const MachineID &id, Addr addr, Cycles latency, 119 const DataBlock &block); 120 void queueMemoryWritePartial(const MachineID &id, Addr addr, Cycles latency, 121 const DataBlock &block, int size); 122 void recvTimingResp(PacketPtr pkt); 123 124 public: 125 MachineID getMachineID() const { return m_machineID; } 126 127 Stats::Histogram& getDelayHist() { return m_delayHistogram; } 128 Stats::Histogram& getDelayVCHist(uint32_t index) 129 { return *(m_delayVCHistogram[index]); } 130 131 protected: 132 //! Profiles original cache requests including PUTs 133 void profileRequest(const std::string &request); 134 //! Profiles the delay associated with messages. 135 void profileMsgDelay(uint32_t virtualNetwork, Cycles delay); 136 137 void stallBuffer(MessageBuffer* buf, Addr addr); 138 void wakeUpBuffers(Addr addr); 139 void wakeUpAllBuffers(Addr addr); 140 void wakeUpAllBuffers(); 141 142 protected: 143 const NodeID m_version; 144 MachineID m_machineID; 145 const NodeID m_clusterID; 146 147 // MasterID used by some components of gem5. 148 const MasterID m_masterId; 149 150 Network *m_net_ptr; 151 bool m_is_blocking; 152 std::map<Addr, MessageBuffer*> m_block_map; 153 154 typedef std::vector<MessageBuffer*> MsgVecType; 155 typedef std::set<MessageBuffer*> MsgBufType; 156 typedef std::map<Addr, MsgVecType* > WaitingBufType; 157 WaitingBufType m_waiting_buffers; 158 159 unsigned int m_in_ports; 160 unsigned int m_cur_in_port; 161 const int m_number_of_TBEs; 162 const int m_transitions_per_cycle; 163 const unsigned int m_buffer_size; 164 Cycles m_recycle_latency; 165 166 //! Counter for the number of cycles when the transitions carried out 167 //! were equal to the maximum allowed 168 Stats::Scalar m_fully_busy_cycles; 169 170 //! Histogram for profiling delay for the messages this controller 171 //! cares for 172 Stats::Histogram m_delayHistogram; 173 std::vector<Stats::Histogram *> m_delayVCHistogram; 174 175 //! Callback class used for collating statistics from all the 176 //! controller of this type. 177 class StatsCallback : public Callback 178 { 179 private: 180 AbstractController *ctr; 181 182 public: 183 virtual ~StatsCallback() {} 184 StatsCallback(AbstractController *_ctr) : ctr(_ctr) {} 185 void process() {ctr->collateStats();} 186 }; 187 188 /** 189 * Port that forwards requests and receives responses from the 190 * memory controller. It has a queue of packets not yet sent. 191 */ 192 class MemoryPort : public QueuedMasterPort 193 { 194 private: 195 // Packet queues used to store outgoing requests and snoop responses. 196 ReqPacketQueue reqQueue; 197 SnoopRespPacketQueue snoopRespQueue; 198 199 // Controller that operates this port. 200 AbstractController *controller; 201 202 public: 203 MemoryPort(const std::string &_name, AbstractController *_controller, 204 const std::string &_label); 205 206 // Function for receiving a timing response from the peer port. 207 // Currently the pkt is handed to the coherence controller 208 // associated with this port. 209 bool recvTimingResp(PacketPtr pkt); 210 }; 211 212 /* Master port to the memory controller. */ 213 MemoryPort memoryPort; 214 215 // State that is stored in packets sent to the memory controller. 216 struct SenderState : public Packet::SenderState 217 { 218 // Id of the machine from which the request originated. 219 MachineID id; 220 221 SenderState(MachineID _id) : id(_id) 222 {} 223 }; 224}; 225 226#endif // __MEM_RUBY_SLICC_INTERFACE_ABSTRACTCONTROLLER_HH__ 227