AbstractController.hh revision 10977:9b3b9be42dd9
18745Sgblack@eecs.umich.edu/* 28745Sgblack@eecs.umich.edu * Copyright (c) 2009-2014 Mark D. Hill and David A. Wood 38745Sgblack@eecs.umich.edu * All rights reserved. 48745Sgblack@eecs.umich.edu * 58745Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 68745Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are 78745Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright 88745Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 98745Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 108745Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 118745Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution; 128745Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its 138745Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 148745Sgblack@eecs.umich.edu * this software without specific prior written permission. 158745Sgblack@eecs.umich.edu * 168745Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 178745Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 188745Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 198745Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 208745Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 218745Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 228745Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 238745Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 248745Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 258745Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 268745Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 278745Sgblack@eecs.umich.edu */ 288745Sgblack@eecs.umich.edu 298745Sgblack@eecs.umich.edu#ifndef __MEM_RUBY_SLICC_INTERFACE_ABSTRACTCONTROLLER_HH__ 308745Sgblack@eecs.umich.edu#define __MEM_RUBY_SLICC_INTERFACE_ABSTRACTCONTROLLER_HH__ 318745Sgblack@eecs.umich.edu 328745Sgblack@eecs.umich.edu#include <exception> 338745Sgblack@eecs.umich.edu#include <iostream> 348745Sgblack@eecs.umich.edu#include <string> 358745Sgblack@eecs.umich.edu 368745Sgblack@eecs.umich.edu#include "base/callback.hh" 378745Sgblack@eecs.umich.edu#include "mem/protocol/AccessPermission.hh" 3811800Sbrandon.potter@amd.com#include "mem/ruby/common/Address.hh" 398745Sgblack@eecs.umich.edu#include "mem/ruby/common/Consumer.hh" 408745Sgblack@eecs.umich.edu#include "mem/ruby/common/DataBlock.hh" 418745Sgblack@eecs.umich.edu#include "mem/ruby/common/Histogram.hh" 428745Sgblack@eecs.umich.edu#include "mem/ruby/common/MachineID.hh" 438745Sgblack@eecs.umich.edu#include "mem/ruby/network/MessageBuffer.hh" 448745Sgblack@eecs.umich.edu#include "mem/ruby/network/Network.hh" 458745Sgblack@eecs.umich.edu#include "mem/ruby/system/CacheRecorder.hh" 468745Sgblack@eecs.umich.edu#include "mem/packet.hh" 478745Sgblack@eecs.umich.edu#include "mem/qport.hh" 488745Sgblack@eecs.umich.edu#include "params/RubyController.hh" 498745Sgblack@eecs.umich.edu#include "mem/mem_object.hh" 508745Sgblack@eecs.umich.edu 518745Sgblack@eecs.umich.educlass Network; 528745Sgblack@eecs.umich.edu 538745Sgblack@eecs.umich.edu// used to communicate that an in_port peeked the wrong message type 548745Sgblack@eecs.umich.educlass RejectException: public std::exception 558745Sgblack@eecs.umich.edu{ 568745Sgblack@eecs.umich.edu virtual const char* what() const throw() 578745Sgblack@eecs.umich.edu { return "Port rejected message based on type"; } 588745Sgblack@eecs.umich.edu}; 598745Sgblack@eecs.umich.edu 608745Sgblack@eecs.umich.educlass AbstractController : public MemObject, public Consumer 618745Sgblack@eecs.umich.edu{ 628745Sgblack@eecs.umich.edu public: 638745Sgblack@eecs.umich.edu typedef RubyControllerParams Params; 648745Sgblack@eecs.umich.edu AbstractController(const Params *p); 658745Sgblack@eecs.umich.edu void init(); 668745Sgblack@eecs.umich.edu const Params *params() const { return (const Params *)_params; } 678745Sgblack@eecs.umich.edu 688745Sgblack@eecs.umich.edu const NodeID getVersion() const { return m_machineID.getNum(); } 698745Sgblack@eecs.umich.edu const MachineType getType() const { return m_machineID.getType(); } 708745Sgblack@eecs.umich.edu 718745Sgblack@eecs.umich.edu void initNetworkPtr(Network* net_ptr) { m_net_ptr = net_ptr; } 728745Sgblack@eecs.umich.edu 738745Sgblack@eecs.umich.edu // return instance name 748745Sgblack@eecs.umich.edu void blockOnQueue(Address, MessageBuffer*); 758745Sgblack@eecs.umich.edu void unblock(Address); 768745Sgblack@eecs.umich.edu 778745Sgblack@eecs.umich.edu virtual MessageBuffer* getMandatoryQueue() const = 0; 788745Sgblack@eecs.umich.edu virtual AccessPermission getAccessPermission(const Address& addr) = 0; 798745Sgblack@eecs.umich.edu 808745Sgblack@eecs.umich.edu virtual void print(std::ostream & out) const = 0; 818745Sgblack@eecs.umich.edu virtual void wakeup() = 0; 828745Sgblack@eecs.umich.edu virtual void resetStats() = 0; 838745Sgblack@eecs.umich.edu virtual void regStats(); 848745Sgblack@eecs.umich.edu 858745Sgblack@eecs.umich.edu virtual void recordCacheTrace(int cntrl, CacheRecorder* tr) = 0; 868745Sgblack@eecs.umich.edu virtual Sequencer* getSequencer() const = 0; 878745Sgblack@eecs.umich.edu 888745Sgblack@eecs.umich.edu //! These functions are used by ruby system to read/write the data blocks 898745Sgblack@eecs.umich.edu //! that exist with in the controller. 908745Sgblack@eecs.umich.edu virtual void functionalRead(const Address &addr, PacketPtr) = 0; 918745Sgblack@eecs.umich.edu void functionalMemoryRead(PacketPtr); 928745Sgblack@eecs.umich.edu //! The return value indicates the number of messages written with the 9311566Smitch.hayenga@arm.com //! data from the packet. 948745Sgblack@eecs.umich.edu virtual int functionalWriteBuffers(PacketPtr&) = 0; 958745Sgblack@eecs.umich.edu virtual int functionalWrite(const Address &addr, PacketPtr) = 0; 968745Sgblack@eecs.umich.edu int functionalMemoryWrite(PacketPtr); 978745Sgblack@eecs.umich.edu 988745Sgblack@eecs.umich.edu //! Function for enqueuing a prefetch request 998745Sgblack@eecs.umich.edu virtual void enqueuePrefetch(const Address&, const RubyRequestType&) 1008745Sgblack@eecs.umich.edu { fatal("Prefetches not implemented!");} 1018745Sgblack@eecs.umich.edu 1028745Sgblack@eecs.umich.edu //! Function for collating statistics from all the controllers of this 1038745Sgblack@eecs.umich.edu //! particular type. This function should only be called from the 1048745Sgblack@eecs.umich.edu //! version 0 of this controller type. 1058745Sgblack@eecs.umich.edu virtual void collateStats() 1068745Sgblack@eecs.umich.edu {fatal("collateStats() should be overridden!");} 1078745Sgblack@eecs.umich.edu 108 //! Set the message buffer with given name. 109 virtual void setNetQueue(const std::string& name, MessageBuffer *b) = 0; 110 111 /** A function used to return the port associated with this bus object. */ 112 BaseMasterPort& getMasterPort(const std::string& if_name, 113 PortID idx = InvalidPortID); 114 115 void queueMemoryRead(const MachineID &id, Address addr, Cycles latency); 116 void queueMemoryWrite(const MachineID &id, Address addr, Cycles latency, 117 const DataBlock &block); 118 void queueMemoryWritePartial(const MachineID &id, Address addr, Cycles latency, 119 const DataBlock &block, int size); 120 void recvTimingResp(PacketPtr pkt); 121 122 public: 123 MachineID getMachineID() const { return m_machineID; } 124 125 Stats::Histogram& getDelayHist() { return m_delayHistogram; } 126 Stats::Histogram& getDelayVCHist(uint32_t index) 127 { return *(m_delayVCHistogram[index]); } 128 129 protected: 130 //! Profiles original cache requests including PUTs 131 void profileRequest(const std::string &request); 132 //! Profiles the delay associated with messages. 133 void profileMsgDelay(uint32_t virtualNetwork, Cycles delay); 134 135 void stallBuffer(MessageBuffer* buf, Address addr); 136 void wakeUpBuffers(Address addr); 137 void wakeUpAllBuffers(Address addr); 138 void wakeUpAllBuffers(); 139 140 protected: 141 NodeID m_version; 142 MachineID m_machineID; 143 NodeID m_clusterID; 144 145 // MasterID used by some components of gem5. 146 MasterID m_masterId; 147 148 Network* m_net_ptr; 149 bool m_is_blocking; 150 std::map<Address, MessageBuffer*> m_block_map; 151 152 typedef std::vector<MessageBuffer*> MsgVecType; 153 typedef std::set<MessageBuffer*> MsgBufType; 154 typedef std::map< Address, MsgVecType* > WaitingBufType; 155 WaitingBufType m_waiting_buffers; 156 157 unsigned int m_in_ports; 158 unsigned int m_cur_in_port; 159 int m_number_of_TBEs; 160 int m_transitions_per_cycle; 161 unsigned int m_buffer_size; 162 Cycles m_recycle_latency; 163 164 //! Counter for the number of cycles when the transitions carried out 165 //! were equal to the maximum allowed 166 Stats::Scalar m_fully_busy_cycles; 167 168 //! Histogram for profiling delay for the messages this controller 169 //! cares for 170 Stats::Histogram m_delayHistogram; 171 std::vector<Stats::Histogram *> m_delayVCHistogram; 172 173 //! Callback class used for collating statistics from all the 174 //! controller of this type. 175 class StatsCallback : public Callback 176 { 177 private: 178 AbstractController *ctr; 179 180 public: 181 virtual ~StatsCallback() {} 182 StatsCallback(AbstractController *_ctr) : ctr(_ctr) {} 183 void process() {ctr->collateStats();} 184 }; 185 186 /** 187 * Port that forwards requests and receives responses from the 188 * memory controller. It has a queue of packets not yet sent. 189 */ 190 class MemoryPort : public QueuedMasterPort 191 { 192 private: 193 // Packet queues used to store outgoing requests and snoop responses. 194 ReqPacketQueue reqQueue; 195 SnoopRespPacketQueue snoopRespQueue; 196 197 // Controller that operates this port. 198 AbstractController *controller; 199 200 public: 201 MemoryPort(const std::string &_name, AbstractController *_controller, 202 const std::string &_label); 203 204 // Function for receiving a timing response from the peer port. 205 // Currently the pkt is handed to the coherence controller 206 // associated with this port. 207 bool recvTimingResp(PacketPtr pkt); 208 }; 209 210 /* Master port to the memory controller. */ 211 MemoryPort memoryPort; 212 213 // Message Buffer for storing the response received from the 214 // memory controller. 215 MessageBuffer *m_responseFromMemory_ptr; 216 217 // State that is stored in packets sent to the memory controller. 218 struct SenderState : public Packet::SenderState 219 { 220 // Id of the machine from which the request originated. 221 MachineID id; 222 223 SenderState(MachineID _id) : id(_id) 224 {} 225 }; 226}; 227 228#endif // __MEM_RUBY_SLICC_INTERFACE_ABSTRACTCONTROLLER_HH__ 229