AbstractController.hh revision 11294
17008Snate@binkert.org/* 210524Snilay@cs.wisc.edu * Copyright (c) 2009-2014 Mark D. Hill and David A. Wood 37008Snate@binkert.org * All rights reserved. 47008Snate@binkert.org * 57008Snate@binkert.org * Redistribution and use in source and binary forms, with or without 67008Snate@binkert.org * modification, are permitted provided that the following conditions are 77008Snate@binkert.org * met: redistributions of source code must retain the above copyright 87008Snate@binkert.org * notice, this list of conditions and the following disclaimer; 97008Snate@binkert.org * redistributions in binary form must reproduce the above copyright 107008Snate@binkert.org * notice, this list of conditions and the following disclaimer in the 117008Snate@binkert.org * documentation and/or other materials provided with the distribution; 127008Snate@binkert.org * neither the name of the copyright holders nor the names of its 137008Snate@binkert.org * contributors may be used to endorse or promote products derived from 147008Snate@binkert.org * this software without specific prior written permission. 157008Snate@binkert.org * 167008Snate@binkert.org * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 177008Snate@binkert.org * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 187008Snate@binkert.org * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 197008Snate@binkert.org * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 207008Snate@binkert.org * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 217008Snate@binkert.org * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 227008Snate@binkert.org * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 237008Snate@binkert.org * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 247008Snate@binkert.org * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 257008Snate@binkert.org * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 267008Snate@binkert.org * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 277008Snate@binkert.org */ 286285Snate@binkert.org 297039Snate@binkert.org#ifndef __MEM_RUBY_SLICC_INTERFACE_ABSTRACTCONTROLLER_HH__ 307039Snate@binkert.org#define __MEM_RUBY_SLICC_INTERFACE_ABSTRACTCONTROLLER_HH__ 316285Snate@binkert.org 3210963Sdavid.hashe@amd.com#include <exception> 337055Snate@binkert.org#include <iostream> 347055Snate@binkert.org#include <string> 356876Ssteve.reinhardt@amd.com 369745Snilay@cs.wisc.edu#include "base/callback.hh" 378341Snilay@cs.wisc.edu#include "mem/protocol/AccessPermission.hh" 386506Spdudnik@gmail.com#include "mem/ruby/common/Address.hh" 397055Snate@binkert.org#include "mem/ruby/common/Consumer.hh" 408436SBrad.Beckmann@amd.com#include "mem/ruby/common/DataBlock.hh" 419497Snilay@cs.wisc.edu#include "mem/ruby/common/Histogram.hh" 4210301Snilay@cs.wisc.edu#include "mem/ruby/common/MachineID.hh" 4310301Snilay@cs.wisc.edu#include "mem/ruby/network/MessageBuffer.hh" 446881SBrad.Beckmann@amd.com#include "mem/ruby/network/Network.hh" 4510301Snilay@cs.wisc.edu#include "mem/ruby/system/CacheRecorder.hh" 469364Snilay@cs.wisc.edu#include "mem/packet.hh" 4710524Snilay@cs.wisc.edu#include "mem/qport.hh" 487055Snate@binkert.org#include "params/RubyController.hh" 4910524Snilay@cs.wisc.edu#include "mem/mem_object.hh" 506285Snate@binkert.org 516285Snate@binkert.orgclass Network; 526285Snate@binkert.org 5310963Sdavid.hashe@amd.com// used to communicate that an in_port peeked the wrong message type 5410963Sdavid.hashe@amd.comclass RejectException: public std::exception 5510963Sdavid.hashe@amd.com{ 5610963Sdavid.hashe@amd.com virtual const char* what() const throw() 5710963Sdavid.hashe@amd.com { return "Port rejected message based on type"; } 5810963Sdavid.hashe@amd.com}; 5910963Sdavid.hashe@amd.com 6010524Snilay@cs.wisc.educlass AbstractController : public MemObject, public Consumer 617039Snate@binkert.org{ 627039Snate@binkert.org public: 636876Ssteve.reinhardt@amd.com typedef RubyControllerParams Params; 648436SBrad.Beckmann@amd.com AbstractController(const Params *p); 659496Snilay@cs.wisc.edu void init(); 668257SBrad.Beckmann@amd.com const Params *params() const { return (const Params *)_params; } 679745Snilay@cs.wisc.edu 6811294Sandreas.hansson@arm.com NodeID getVersion() const { return m_machineID.getNum(); } 6911294Sandreas.hansson@arm.com MachineType getType() const { return m_machineID.getType(); } 7010078Snilay@cs.wisc.edu 719819Snilay@cs.wisc.edu void initNetworkPtr(Network* net_ptr) { m_net_ptr = net_ptr; } 729819Snilay@cs.wisc.edu 739819Snilay@cs.wisc.edu // return instance name 7411025Snilay@cs.wisc.edu void blockOnQueue(Addr, MessageBuffer*); 7511025Snilay@cs.wisc.edu void unblock(Addr); 769819Snilay@cs.wisc.edu 777039Snate@binkert.org virtual MessageBuffer* getMandatoryQueue() const = 0; 7811021Sjthestness@gmail.com virtual MessageBuffer* getMemoryQueue() const = 0; 7911025Snilay@cs.wisc.edu virtual AccessPermission getAccessPermission(const Addr &addr) = 0; 806285Snate@binkert.org 817055Snate@binkert.org virtual void print(std::ostream & out) const = 0; 827039Snate@binkert.org virtual void wakeup() = 0; 8310012Snilay@cs.wisc.edu virtual void resetStats() = 0; 8410012Snilay@cs.wisc.edu virtual void regStats(); 859745Snilay@cs.wisc.edu 868683Snilay@cs.wisc.edu virtual void recordCacheTrace(int cntrl, CacheRecorder* tr) = 0; 878683Snilay@cs.wisc.edu virtual Sequencer* getSequencer() const = 0; 889302Snilay@cs.wisc.edu 8910523Snilay@cs.wisc.edu //! These functions are used by ruby system to read/write the data blocks 9010523Snilay@cs.wisc.edu //! that exist with in the controller. 9111025Snilay@cs.wisc.edu virtual void functionalRead(const Addr &addr, PacketPtr) = 0; 9210524Snilay@cs.wisc.edu void functionalMemoryRead(PacketPtr); 939302Snilay@cs.wisc.edu //! The return value indicates the number of messages written with the 949302Snilay@cs.wisc.edu //! data from the packet. 9510524Snilay@cs.wisc.edu virtual int functionalWriteBuffers(PacketPtr&) = 0; 9611025Snilay@cs.wisc.edu virtual int functionalWrite(const Addr &addr, PacketPtr) = 0; 9710524Snilay@cs.wisc.edu int functionalMemoryWrite(PacketPtr); 989363Snilay@cs.wisc.edu 999363Snilay@cs.wisc.edu //! Function for enqueuing a prefetch request 10011025Snilay@cs.wisc.edu virtual void enqueuePrefetch(const Addr &, const RubyRequestType&) 1019363Snilay@cs.wisc.edu { fatal("Prefetches not implemented!");} 1029364Snilay@cs.wisc.edu 1039745Snilay@cs.wisc.edu //! Function for collating statistics from all the controllers of this 1049745Snilay@cs.wisc.edu //! particular type. This function should only be called from the 1059745Snilay@cs.wisc.edu //! version 0 of this controller type. 1069745Snilay@cs.wisc.edu virtual void collateStats() 1079745Snilay@cs.wisc.edu {fatal("collateStats() should be overridden!");} 1089745Snilay@cs.wisc.edu 10911021Sjthestness@gmail.com //! Initialize the message buffers. 11011021Sjthestness@gmail.com virtual void initNetQueues() = 0; 11110311Snilay@cs.wisc.edu 11210524Snilay@cs.wisc.edu /** A function used to return the port associated with this bus object. */ 11310524Snilay@cs.wisc.edu BaseMasterPort& getMasterPort(const std::string& if_name, 11410524Snilay@cs.wisc.edu PortID idx = InvalidPortID); 11510524Snilay@cs.wisc.edu 11611025Snilay@cs.wisc.edu void queueMemoryRead(const MachineID &id, Addr addr, Cycles latency); 11711025Snilay@cs.wisc.edu void queueMemoryWrite(const MachineID &id, Addr addr, Cycles latency, 11810524Snilay@cs.wisc.edu const DataBlock &block); 11911025Snilay@cs.wisc.edu void queueMemoryWritePartial(const MachineID &id, Addr addr, Cycles latency, 12010524Snilay@cs.wisc.edu const DataBlock &block, int size); 12110524Snilay@cs.wisc.edu void recvTimingResp(PacketPtr pkt); 12210524Snilay@cs.wisc.edu 1239496Snilay@cs.wisc.edu public: 1249496Snilay@cs.wisc.edu MachineID getMachineID() const { return m_machineID; } 1259496Snilay@cs.wisc.edu 12610012Snilay@cs.wisc.edu Stats::Histogram& getDelayHist() { return m_delayHistogram; } 12710012Snilay@cs.wisc.edu Stats::Histogram& getDelayVCHist(uint32_t index) 12810012Snilay@cs.wisc.edu { return *(m_delayVCHistogram[index]); } 1299497Snilay@cs.wisc.edu 1309496Snilay@cs.wisc.edu protected: 1319496Snilay@cs.wisc.edu //! Profiles original cache requests including PUTs 1329496Snilay@cs.wisc.edu void profileRequest(const std::string &request); 1339497Snilay@cs.wisc.edu //! Profiles the delay associated with messages. 1349507Snilay@cs.wisc.edu void profileMsgDelay(uint32_t virtualNetwork, Cycles delay); 1359496Snilay@cs.wisc.edu 13611025Snilay@cs.wisc.edu void stallBuffer(MessageBuffer* buf, Addr addr); 13711025Snilay@cs.wisc.edu void wakeUpBuffers(Addr addr); 13811025Snilay@cs.wisc.edu void wakeUpAllBuffers(Addr addr); 1399596Snilay@cs.wisc.edu void wakeUpAllBuffers(); 1409596Snilay@cs.wisc.edu 1419364Snilay@cs.wisc.edu protected: 14211121Snilay@cs.wisc.edu const NodeID m_version; 14310005Snilay@cs.wisc.edu MachineID m_machineID; 14411121Snilay@cs.wisc.edu const NodeID m_clusterID; 14510005Snilay@cs.wisc.edu 14610524Snilay@cs.wisc.edu // MasterID used by some components of gem5. 14711121Snilay@cs.wisc.edu const MasterID m_masterId; 14810524Snilay@cs.wisc.edu 14911121Snilay@cs.wisc.edu Network *m_net_ptr; 1509364Snilay@cs.wisc.edu bool m_is_blocking; 15111025Snilay@cs.wisc.edu std::map<Addr, MessageBuffer*> m_block_map; 15210087Snilay@cs.wisc.edu 1539364Snilay@cs.wisc.edu typedef std::vector<MessageBuffer*> MsgVecType; 15410977Sdavid.hashe@amd.com typedef std::set<MessageBuffer*> MsgBufType; 15511025Snilay@cs.wisc.edu typedef std::map<Addr, MsgVecType* > WaitingBufType; 1569364Snilay@cs.wisc.edu WaitingBufType m_waiting_buffers; 15710087Snilay@cs.wisc.edu 1589996Snilay@cs.wisc.edu unsigned int m_in_ports; 1599996Snilay@cs.wisc.edu unsigned int m_cur_in_port; 16011121Snilay@cs.wisc.edu const int m_number_of_TBEs; 16111121Snilay@cs.wisc.edu const int m_transitions_per_cycle; 16211121Snilay@cs.wisc.edu const unsigned int m_buffer_size; 16310005Snilay@cs.wisc.edu Cycles m_recycle_latency; 1649496Snilay@cs.wisc.edu 1659496Snilay@cs.wisc.edu //! Counter for the number of cycles when the transitions carried out 1669496Snilay@cs.wisc.edu //! were equal to the maximum allowed 16710012Snilay@cs.wisc.edu Stats::Scalar m_fully_busy_cycles; 1689497Snilay@cs.wisc.edu 1699497Snilay@cs.wisc.edu //! Histogram for profiling delay for the messages this controller 1709497Snilay@cs.wisc.edu //! cares for 17110012Snilay@cs.wisc.edu Stats::Histogram m_delayHistogram; 17210012Snilay@cs.wisc.edu std::vector<Stats::Histogram *> m_delayVCHistogram; 1739745Snilay@cs.wisc.edu 1749745Snilay@cs.wisc.edu //! Callback class used for collating statistics from all the 1759745Snilay@cs.wisc.edu //! controller of this type. 1769745Snilay@cs.wisc.edu class StatsCallback : public Callback 1779745Snilay@cs.wisc.edu { 1789745Snilay@cs.wisc.edu private: 1799745Snilay@cs.wisc.edu AbstractController *ctr; 1809745Snilay@cs.wisc.edu 1819745Snilay@cs.wisc.edu public: 1829745Snilay@cs.wisc.edu virtual ~StatsCallback() {} 18310012Snilay@cs.wisc.edu StatsCallback(AbstractController *_ctr) : ctr(_ctr) {} 1849745Snilay@cs.wisc.edu void process() {ctr->collateStats();} 1859745Snilay@cs.wisc.edu }; 18610524Snilay@cs.wisc.edu 18710524Snilay@cs.wisc.edu /** 18810524Snilay@cs.wisc.edu * Port that forwards requests and receives responses from the 18910524Snilay@cs.wisc.edu * memory controller. It has a queue of packets not yet sent. 19010524Snilay@cs.wisc.edu */ 19110524Snilay@cs.wisc.edu class MemoryPort : public QueuedMasterPort 19210524Snilay@cs.wisc.edu { 19310524Snilay@cs.wisc.edu private: 19410713Sandreas.hansson@arm.com // Packet queues used to store outgoing requests and snoop responses. 19510713Sandreas.hansson@arm.com ReqPacketQueue reqQueue; 19610713Sandreas.hansson@arm.com SnoopRespPacketQueue snoopRespQueue; 19710524Snilay@cs.wisc.edu 19810524Snilay@cs.wisc.edu // Controller that operates this port. 19910524Snilay@cs.wisc.edu AbstractController *controller; 20010524Snilay@cs.wisc.edu 20110524Snilay@cs.wisc.edu public: 20210524Snilay@cs.wisc.edu MemoryPort(const std::string &_name, AbstractController *_controller, 20310524Snilay@cs.wisc.edu const std::string &_label); 20410524Snilay@cs.wisc.edu 20510524Snilay@cs.wisc.edu // Function for receiving a timing response from the peer port. 20610524Snilay@cs.wisc.edu // Currently the pkt is handed to the coherence controller 20710524Snilay@cs.wisc.edu // associated with this port. 20810524Snilay@cs.wisc.edu bool recvTimingResp(PacketPtr pkt); 20910524Snilay@cs.wisc.edu }; 21010524Snilay@cs.wisc.edu 21110524Snilay@cs.wisc.edu /* Master port to the memory controller. */ 21210524Snilay@cs.wisc.edu MemoryPort memoryPort; 21310524Snilay@cs.wisc.edu 21410524Snilay@cs.wisc.edu // State that is stored in packets sent to the memory controller. 21510524Snilay@cs.wisc.edu struct SenderState : public Packet::SenderState 21610524Snilay@cs.wisc.edu { 21710524Snilay@cs.wisc.edu // Id of the machine from which the request originated. 21810524Snilay@cs.wisc.edu MachineID id; 21910524Snilay@cs.wisc.edu 22010524Snilay@cs.wisc.edu SenderState(MachineID _id) : id(_id) 22110524Snilay@cs.wisc.edu {} 22210524Snilay@cs.wisc.edu }; 2236285Snate@binkert.org}; 2246285Snate@binkert.org 2257039Snate@binkert.org#endif // __MEM_RUBY_SLICC_INTERFACE_ABSTRACTCONTROLLER_HH__ 226