AbstractController.hh revision 10713
17008Snate@binkert.org/* 210524Snilay@cs.wisc.edu * Copyright (c) 2009-2014 Mark D. Hill and David A. Wood 37008Snate@binkert.org * All rights reserved. 47008Snate@binkert.org * 57008Snate@binkert.org * Redistribution and use in source and binary forms, with or without 67008Snate@binkert.org * modification, are permitted provided that the following conditions are 77008Snate@binkert.org * met: redistributions of source code must retain the above copyright 87008Snate@binkert.org * notice, this list of conditions and the following disclaimer; 97008Snate@binkert.org * redistributions in binary form must reproduce the above copyright 107008Snate@binkert.org * notice, this list of conditions and the following disclaimer in the 117008Snate@binkert.org * documentation and/or other materials provided with the distribution; 127008Snate@binkert.org * neither the name of the copyright holders nor the names of its 137008Snate@binkert.org * contributors may be used to endorse or promote products derived from 147008Snate@binkert.org * this software without specific prior written permission. 157008Snate@binkert.org * 167008Snate@binkert.org * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 177008Snate@binkert.org * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 187008Snate@binkert.org * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 197008Snate@binkert.org * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 207008Snate@binkert.org * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 217008Snate@binkert.org * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 227008Snate@binkert.org * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 237008Snate@binkert.org * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 247008Snate@binkert.org * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 257008Snate@binkert.org * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 267008Snate@binkert.org * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 277008Snate@binkert.org */ 286285Snate@binkert.org 297039Snate@binkert.org#ifndef __MEM_RUBY_SLICC_INTERFACE_ABSTRACTCONTROLLER_HH__ 307039Snate@binkert.org#define __MEM_RUBY_SLICC_INTERFACE_ABSTRACTCONTROLLER_HH__ 316285Snate@binkert.org 327055Snate@binkert.org#include <iostream> 337055Snate@binkert.org#include <string> 346876Ssteve.reinhardt@amd.com 359745Snilay@cs.wisc.edu#include "base/callback.hh" 368341Snilay@cs.wisc.edu#include "mem/protocol/AccessPermission.hh" 376506Spdudnik@gmail.com#include "mem/ruby/common/Address.hh" 387055Snate@binkert.org#include "mem/ruby/common/Consumer.hh" 398436SBrad.Beckmann@amd.com#include "mem/ruby/common/DataBlock.hh" 409497Snilay@cs.wisc.edu#include "mem/ruby/common/Histogram.hh" 4110301Snilay@cs.wisc.edu#include "mem/ruby/common/MachineID.hh" 4210301Snilay@cs.wisc.edu#include "mem/ruby/network/MessageBuffer.hh" 436881SBrad.Beckmann@amd.com#include "mem/ruby/network/Network.hh" 4410301Snilay@cs.wisc.edu#include "mem/ruby/system/CacheRecorder.hh" 459364Snilay@cs.wisc.edu#include "mem/packet.hh" 4610524Snilay@cs.wisc.edu#include "mem/qport.hh" 477055Snate@binkert.org#include "params/RubyController.hh" 4810524Snilay@cs.wisc.edu#include "mem/mem_object.hh" 496285Snate@binkert.org 506285Snate@binkert.orgclass Network; 516285Snate@binkert.org 5210524Snilay@cs.wisc.educlass AbstractController : public MemObject, public Consumer 537039Snate@binkert.org{ 547039Snate@binkert.org public: 556876Ssteve.reinhardt@amd.com typedef RubyControllerParams Params; 568436SBrad.Beckmann@amd.com AbstractController(const Params *p); 579496Snilay@cs.wisc.edu void init(); 588257SBrad.Beckmann@amd.com const Params *params() const { return (const Params *)_params; } 599745Snilay@cs.wisc.edu 6010078Snilay@cs.wisc.edu const NodeID getVersion() const { return m_machineID.getNum(); } 6110078Snilay@cs.wisc.edu const MachineType getType() const { return m_machineID.getType(); } 6210078Snilay@cs.wisc.edu 639819Snilay@cs.wisc.edu void initNetworkPtr(Network* net_ptr) { m_net_ptr = net_ptr; } 649819Snilay@cs.wisc.edu 659819Snilay@cs.wisc.edu // return instance name 669819Snilay@cs.wisc.edu void blockOnQueue(Address, MessageBuffer*); 679819Snilay@cs.wisc.edu void unblock(Address); 689819Snilay@cs.wisc.edu 697039Snate@binkert.org virtual MessageBuffer* getMandatoryQueue() const = 0; 708531Snilay@cs.wisc.edu virtual AccessPermission getAccessPermission(const Address& addr) = 0; 716285Snate@binkert.org 727055Snate@binkert.org virtual void print(std::ostream & out) const = 0; 737039Snate@binkert.org virtual void wakeup() = 0; 7410012Snilay@cs.wisc.edu virtual void resetStats() = 0; 7510012Snilay@cs.wisc.edu virtual void regStats(); 769745Snilay@cs.wisc.edu 778683Snilay@cs.wisc.edu virtual void recordCacheTrace(int cntrl, CacheRecorder* tr) = 0; 788683Snilay@cs.wisc.edu virtual Sequencer* getSequencer() const = 0; 799302Snilay@cs.wisc.edu 8010523Snilay@cs.wisc.edu //! These functions are used by ruby system to read/write the data blocks 8110523Snilay@cs.wisc.edu //! that exist with in the controller. 8210522Snilay@cs.wisc.edu virtual void functionalRead(const Address &addr, PacketPtr) = 0; 8310524Snilay@cs.wisc.edu void functionalMemoryRead(PacketPtr); 849302Snilay@cs.wisc.edu //! The return value indicates the number of messages written with the 859302Snilay@cs.wisc.edu //! data from the packet. 8610524Snilay@cs.wisc.edu virtual int functionalWriteBuffers(PacketPtr&) = 0; 8710522Snilay@cs.wisc.edu virtual int functionalWrite(const Address &addr, PacketPtr) = 0; 8810524Snilay@cs.wisc.edu int functionalMemoryWrite(PacketPtr); 899363Snilay@cs.wisc.edu 909363Snilay@cs.wisc.edu //! Function for enqueuing a prefetch request 919363Snilay@cs.wisc.edu virtual void enqueuePrefetch(const Address&, const RubyRequestType&) 929363Snilay@cs.wisc.edu { fatal("Prefetches not implemented!");} 939364Snilay@cs.wisc.edu 949745Snilay@cs.wisc.edu //! Function for collating statistics from all the controllers of this 959745Snilay@cs.wisc.edu //! particular type. This function should only be called from the 969745Snilay@cs.wisc.edu //! version 0 of this controller type. 979745Snilay@cs.wisc.edu virtual void collateStats() 989745Snilay@cs.wisc.edu {fatal("collateStats() should be overridden!");} 999745Snilay@cs.wisc.edu 10010311Snilay@cs.wisc.edu //! Set the message buffer with given name. 10110311Snilay@cs.wisc.edu virtual void setNetQueue(const std::string& name, MessageBuffer *b) = 0; 10210311Snilay@cs.wisc.edu 10310524Snilay@cs.wisc.edu /** A function used to return the port associated with this bus object. */ 10410524Snilay@cs.wisc.edu BaseMasterPort& getMasterPort(const std::string& if_name, 10510524Snilay@cs.wisc.edu PortID idx = InvalidPortID); 10610524Snilay@cs.wisc.edu 10710524Snilay@cs.wisc.edu void queueMemoryRead(const MachineID &id, Address addr, Cycles latency); 10810524Snilay@cs.wisc.edu void queueMemoryWrite(const MachineID &id, Address addr, Cycles latency, 10910524Snilay@cs.wisc.edu const DataBlock &block); 11010524Snilay@cs.wisc.edu void queueMemoryWritePartial(const MachineID &id, Address addr, Cycles latency, 11110524Snilay@cs.wisc.edu const DataBlock &block, int size); 11210524Snilay@cs.wisc.edu void recvTimingResp(PacketPtr pkt); 11310524Snilay@cs.wisc.edu 1149496Snilay@cs.wisc.edu public: 1159496Snilay@cs.wisc.edu MachineID getMachineID() const { return m_machineID; } 1169496Snilay@cs.wisc.edu 11710012Snilay@cs.wisc.edu Stats::Histogram& getDelayHist() { return m_delayHistogram; } 11810012Snilay@cs.wisc.edu Stats::Histogram& getDelayVCHist(uint32_t index) 11910012Snilay@cs.wisc.edu { return *(m_delayVCHistogram[index]); } 1209497Snilay@cs.wisc.edu 1219496Snilay@cs.wisc.edu protected: 1229496Snilay@cs.wisc.edu //! Profiles original cache requests including PUTs 1239496Snilay@cs.wisc.edu void profileRequest(const std::string &request); 1249497Snilay@cs.wisc.edu //! Profiles the delay associated with messages. 1259507Snilay@cs.wisc.edu void profileMsgDelay(uint32_t virtualNetwork, Cycles delay); 1269496Snilay@cs.wisc.edu 1279596Snilay@cs.wisc.edu void stallBuffer(MessageBuffer* buf, Address addr); 1289596Snilay@cs.wisc.edu void wakeUpBuffers(Address addr); 1299596Snilay@cs.wisc.edu void wakeUpAllBuffers(Address addr); 1309596Snilay@cs.wisc.edu void wakeUpAllBuffers(); 1319596Snilay@cs.wisc.edu 1329364Snilay@cs.wisc.edu protected: 1339364Snilay@cs.wisc.edu NodeID m_version; 13410005Snilay@cs.wisc.edu MachineID m_machineID; 13510005Snilay@cs.wisc.edu NodeID m_clusterID; 13610005Snilay@cs.wisc.edu 13710524Snilay@cs.wisc.edu // MasterID used by some components of gem5. 13810524Snilay@cs.wisc.edu MasterID m_masterId; 13910524Snilay@cs.wisc.edu 1409364Snilay@cs.wisc.edu Network* m_net_ptr; 1419364Snilay@cs.wisc.edu bool m_is_blocking; 1429364Snilay@cs.wisc.edu std::map<Address, MessageBuffer*> m_block_map; 14310087Snilay@cs.wisc.edu 1449364Snilay@cs.wisc.edu typedef std::vector<MessageBuffer*> MsgVecType; 1459364Snilay@cs.wisc.edu typedef std::map< Address, MsgVecType* > WaitingBufType; 1469364Snilay@cs.wisc.edu WaitingBufType m_waiting_buffers; 14710087Snilay@cs.wisc.edu 1489996Snilay@cs.wisc.edu unsigned int m_in_ports; 1499996Snilay@cs.wisc.edu unsigned int m_cur_in_port; 1509364Snilay@cs.wisc.edu int m_number_of_TBEs; 15110005Snilay@cs.wisc.edu int m_transitions_per_cycle; 15210096Snilay@cs.wisc.edu unsigned int m_buffer_size; 15310005Snilay@cs.wisc.edu Cycles m_recycle_latency; 1549496Snilay@cs.wisc.edu 1559496Snilay@cs.wisc.edu //! Counter for the number of cycles when the transitions carried out 1569496Snilay@cs.wisc.edu //! were equal to the maximum allowed 15710012Snilay@cs.wisc.edu Stats::Scalar m_fully_busy_cycles; 1589497Snilay@cs.wisc.edu 1599497Snilay@cs.wisc.edu //! Histogram for profiling delay for the messages this controller 1609497Snilay@cs.wisc.edu //! cares for 16110012Snilay@cs.wisc.edu Stats::Histogram m_delayHistogram; 16210012Snilay@cs.wisc.edu std::vector<Stats::Histogram *> m_delayVCHistogram; 1639745Snilay@cs.wisc.edu 1649745Snilay@cs.wisc.edu //! Callback class used for collating statistics from all the 1659745Snilay@cs.wisc.edu //! controller of this type. 1669745Snilay@cs.wisc.edu class StatsCallback : public Callback 1679745Snilay@cs.wisc.edu { 1689745Snilay@cs.wisc.edu private: 1699745Snilay@cs.wisc.edu AbstractController *ctr; 1709745Snilay@cs.wisc.edu 1719745Snilay@cs.wisc.edu public: 1729745Snilay@cs.wisc.edu virtual ~StatsCallback() {} 17310012Snilay@cs.wisc.edu StatsCallback(AbstractController *_ctr) : ctr(_ctr) {} 1749745Snilay@cs.wisc.edu void process() {ctr->collateStats();} 1759745Snilay@cs.wisc.edu }; 17610524Snilay@cs.wisc.edu 17710524Snilay@cs.wisc.edu /** 17810524Snilay@cs.wisc.edu * Port that forwards requests and receives responses from the 17910524Snilay@cs.wisc.edu * memory controller. It has a queue of packets not yet sent. 18010524Snilay@cs.wisc.edu */ 18110524Snilay@cs.wisc.edu class MemoryPort : public QueuedMasterPort 18210524Snilay@cs.wisc.edu { 18310524Snilay@cs.wisc.edu private: 18410713Sandreas.hansson@arm.com // Packet queues used to store outgoing requests and snoop responses. 18510713Sandreas.hansson@arm.com ReqPacketQueue reqQueue; 18610713Sandreas.hansson@arm.com SnoopRespPacketQueue snoopRespQueue; 18710524Snilay@cs.wisc.edu 18810524Snilay@cs.wisc.edu // Controller that operates this port. 18910524Snilay@cs.wisc.edu AbstractController *controller; 19010524Snilay@cs.wisc.edu 19110524Snilay@cs.wisc.edu public: 19210524Snilay@cs.wisc.edu MemoryPort(const std::string &_name, AbstractController *_controller, 19310524Snilay@cs.wisc.edu const std::string &_label); 19410524Snilay@cs.wisc.edu 19510524Snilay@cs.wisc.edu // Function for receiving a timing response from the peer port. 19610524Snilay@cs.wisc.edu // Currently the pkt is handed to the coherence controller 19710524Snilay@cs.wisc.edu // associated with this port. 19810524Snilay@cs.wisc.edu bool recvTimingResp(PacketPtr pkt); 19910524Snilay@cs.wisc.edu }; 20010524Snilay@cs.wisc.edu 20110524Snilay@cs.wisc.edu /* Master port to the memory controller. */ 20210524Snilay@cs.wisc.edu MemoryPort memoryPort; 20310524Snilay@cs.wisc.edu 20410524Snilay@cs.wisc.edu // Message Buffer for storing the response received from the 20510524Snilay@cs.wisc.edu // memory controller. 20610524Snilay@cs.wisc.edu MessageBuffer *m_responseFromMemory_ptr; 20710524Snilay@cs.wisc.edu 20810524Snilay@cs.wisc.edu // State that is stored in packets sent to the memory controller. 20910524Snilay@cs.wisc.edu struct SenderState : public Packet::SenderState 21010524Snilay@cs.wisc.edu { 21110524Snilay@cs.wisc.edu // Id of the machine from which the request originated. 21210524Snilay@cs.wisc.edu MachineID id; 21310524Snilay@cs.wisc.edu 21410524Snilay@cs.wisc.edu SenderState(MachineID _id) : id(_id) 21510524Snilay@cs.wisc.edu {} 21610524Snilay@cs.wisc.edu }; 2176285Snate@binkert.org}; 2186285Snate@binkert.org 2197039Snate@binkert.org#endif // __MEM_RUBY_SLICC_INTERFACE_ABSTRACTCONTROLLER_HH__ 220