1/*
2 * Copyright (c) 2010-2015 Advanced Micro Devices, Inc.
3 * All rights reserved.
4 *
5 * For use for simulation and test purposes only
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
9 *
10 * 1. Redistributions of source code must retain the above copyright notice,
11 * this list of conditions and the following disclaimer.
12 *
13 * 2. Redistributions in binary form must reproduce the above copyright notice,
14 * this list of conditions and the following disclaimer in the documentation
15 * and/or other materials provided with the distribution.
16 *
17 * 3. Neither the name of the copyright holder nor the names of its
18 * contributors may be used to endorse or promote products derived from this
19 * software without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
32 *
33 * Authors: Lisa Hsu
34 */
35
36enumeration(CoherenceRequestType, desc="Coherence Request Types") {
37  // CPU Request Types ONLY
38  RdBlk,        desc="Read Blk";
39  RdBlkM,       desc="Read Blk Modified";
40  RdBlkS,       desc="Read Blk Shared";
41  VicClean,     desc="L2 clean eviction";
42  VicDirty,     desc="L2 dirty eviction";
43
44  WrCancel,     desc="want to cancel WB to Memory"; // should this be here?
45
46  WBApproval,   desc="WB Approval";
47
48  // Messages between Dir and R-Dir
49  ForceInv,     desc="Send invalide to the block";
50  ForceDowngrade, desc="Send downgrade to the block";
51  Unblock,      desc="Used to let the dir know a message has been sunk";
52
53  // Messages between R-Dir and R-Buffer
54  PrivateNotify, desc="Let region buffer know it has private access";
55  SharedNotify,  desc="Let region buffer know it has shared access";
56  WbNotify,      desc="Let region buffer know it saw its wb request";
57  Downgrade,     desc="Force the region buffer to downgrade to shared";
58  // Response to R-Dir (probably should be on a different network, but
59  // I need it to be ordered with respect to requests)
60  InvAck,       desc="Let the R-Dir know when the inv has occured";
61
62  PrivateRequest, desc="R-buf wants the region in private";
63  UpgradeRequest, desc="R-buf wants the region in private";
64  SharedRequest,  desc="R-buf wants the region in shared (could respond with private)";
65  CleanWbRequest, desc="R-buf wants to deallocate clean region";
66
67  NA,             desc="So we don't get segfaults";
68}
69
70enumeration(ProbeRequestType, desc="Probe Request Types") {
71  PrbDowngrade,    desc="Probe for Status";  // EtoS, MtoO, StoS
72  PrbInv,       desc="Probe to Invalidate";
73
74  // For regions
75  PrbRepl,      desc="Force the cache to do a replacement";
76  PrbRegDowngrade, desc="Probe for Status";  // EtoS, MtoO, StoS
77}
78
79
80enumeration(CoherenceResponseType, desc="Coherence Response Types") {
81  NBSysResp,       desc="Northbridge response to CPU Rd request";
82  NBSysWBAck,      desc="Northbridge response ok to WB";
83  TDSysResp,       desc="TCCdirectory response to CPU Rd request";
84  TDSysWBAck,      desc="TCCdirectory response ok to WB";
85  TDSysWBNack,      desc="TCCdirectory response ok to drop";
86  CPUPrbResp,      desc="CPU Probe Response";
87  CPUData,         desc="CPU Data";
88  StaleNotif,      desc="Notification of Stale WBAck, No data to writeback";
89  CPUCancelWB,     desc="want to cancel WB to Memory";
90  MemData,         desc="Data from Memory";
91
92  // for regions
93  PrivateAck,      desc="Ack that r-buf received private notify";
94  RegionWbAck, desc="Writeback Ack that r-buf completed deallocation";
95  DirReadyAck, desc="Directory (mem ctrl)<->region dir handshake";
96}
97
98enumeration(CoherenceState, default="CoherenceState_NA", desc="Coherence State") {
99  Modified,             desc="Modified";
100  Owned,                desc="Owned state";
101  Exclusive,            desc="Exclusive";
102  Shared,               desc="Shared";
103  NA,                   desc="NA";
104}
105
106structure(CPURequestMsg, desc="...", interface="Message") {
107  Addr addr,             desc="Physical address for this request";
108  Addr DemandAddress,       desc="Physical block address for this request";
109  CoherenceRequestType Type,   desc="Type of request";
110  DataBlock DataBlk,           desc="data for the cache line";  // only for WB
111  bool Dirty,                   desc="whether WB data is dirty";  // only for WB
112  MachineID Requestor,            desc="Node who initiated the request";
113  NetDest Destination,             desc="Multicast destination mask";
114  bool Shared,                  desc="For CPU_WrVicBlk, vic is O not M.  For CPU_ClVicBlk, vic is S";
115  MessageSizeType MessageSize, desc="size category of the message";
116  Cycles InitialRequestTime, default="0", desc="time the initial requests was sent from the L1Cache";
117  Cycles ForwardRequestTime, default="0", desc="time the dir forwarded the request";
118  Cycles ProbeRequestStartTime, default="0", desc="the time the dir started the probe request";
119  bool DemandRequest, default="false", desc="For profiling purposes";
120
121  NetDest Sharers,              desc="Caches that may have a valid copy of the data";
122  bool ForceShared,             desc="R-dir knows it is shared, pass on so it sends an S copy, not E";
123  bool Private, default="false", desc="Requestor already has private permissions, no need for dir check";
124  bool CtoDSinked, default="false", desc="This is true if the CtoD previously sent must have been sunk";
125
126  bool NoAckNeeded, default="false", desc="True if region buffer doesn't need to ack";
127  int Acks, default="0", desc="Acks that the dir (mem ctrl) should expect to receive";
128  CoherenceRequestType OriginalType, default="CoherenceRequestType_NA",  desc="Type of request from core fwded through region buffer";
129
130  bool functionalRead(Packet *pkt) {
131    // Only PUTX messages contains the data block
132    if (Type == CoherenceRequestType:VicDirty) {
133        return testAndRead(addr, DataBlk, pkt);
134    }
135
136    return false;
137  }
138
139  bool functionalWrite(Packet *pkt) {
140    // No check on message type required since the protocol should
141    // read data from those messages that contain the block
142    return testAndWrite(addr, DataBlk, pkt);
143  }
144}
145
146structure(NBProbeRequestMsg, desc="...", interface="Message") {
147  Addr addr,              desc="Physical address for this request";
148  ProbeRequestType Type,             desc="probe signal";
149  bool ReturnData,              desc="Indicates CPU should return data";
150  NetDest Destination,             desc="Node to whom the data is sent";
151  MessageSizeType MessageSize, desc="size category of the message";
152  bool DemandRequest, default="false", desc="demand request, requesting 3-hop transfer";
153  Addr DemandAddress,        desc="Demand block address for a region request";
154  MachineID Requestor,          desc="Requestor id for 3-hop requests";
155  bool NoAckNeeded, default="false", desc="For short circuting acks";
156
157  bool functionalRead(Packet *pkt) {
158    return false;
159  }
160
161  bool functionalWrite(Packet *pkt) {
162    // No check on message type required since the protocol should
163    // read data from those messages that contain the block
164    return false;
165  }
166
167}
168
169structure(TDProbeRequestMsg, desc="...", interface="Message") {
170  Addr addr,              desc="Physical address for this request";
171  ProbeRequestType Type,             desc="TD_PrbNxtState signal";
172  bool ReturnData,              desc="Indicates CPU should return data";
173  bool localCtoD,              desc="Indicates CtoD is within the GPU hierarchy (aka TCC subtree)";
174  NetDest Destination,             desc="Node to whom the data is sent";
175  MessageSizeType MessageSize, desc="size category of the message";
176  MachineID Sender,               desc="Node who sent the data";
177  bool currentOwner, default="false", desc="Is the sender the current owner";
178  bool DoneAck, default="false", desc="Is this a done ack?";
179  bool Dirty, default="false", desc="Was block dirty when evicted";
180  bool wasValid, default="false", desc="Was block valid when evicted";
181  bool valid, default="false", desc="Is block valid";
182  bool validToInvalid, default="false", desc="Was block valid when evicted";
183
184  bool functionalRead(Packet *pkt) {
185    return false;
186  }
187
188  bool functionalWrite(Packet *pkt) {
189    // No check on message type required since the protocol should
190    // read data from those messages that contain the block
191    return false;
192  }
193}
194
195// Response Messages seemed to be easily munged into one type
196structure(ResponseMsg, desc="...", interface="Message") {
197  Addr addr,             desc="Physical address for this request";
198  CoherenceResponseType Type,  desc="NB Sys Resp or CPU Response to Probe";
199  MachineID Sender,               desc="Node who sent the data";
200  NetDest Destination,             desc="Node to whom the data is sent";
201  // Begin Used Only By CPU Response
202  DataBlock DataBlk,           desc="data for the cache line";
203  bool Hit,                    desc="probe hit valid line";
204  bool Shared,                 desc="True if S, or if NB Probe ReturnData==1 && O";
205  bool Dirty,                  desc="Is the data dirty (different than memory)?";
206  bool Ntsl,                   desc="indicates probed lin will be invalid after probe";
207  bool UntransferredOwner,     desc="pending confirmation of ownership change";
208  // End Used Only By CPU Response
209
210  // Begin NB Response Only
211  CoherenceState State, default=CoherenceState_NA,        desc="What returned data from NB should be in";
212  bool CtoD,                    desc="was the originator a CtoD?";
213  // End NB Response Only
214
215  bool NbReqShared,             desc="modification of Shared field from initial request, e.g. hit by shared probe";
216
217  MessageSizeType MessageSize, desc="size category of the message";
218  Cycles InitialRequestTime, default="0", desc="time the initial requests was sent from the L1Cache";
219  Cycles ForwardRequestTime, default="0", desc="time the dir forwarded the request";
220  Cycles ProbeRequestStartTime, default="0", desc="the time the dir started the probe request";
221  bool DemandRequest, default="false", desc="For profiling purposes";
222
223  bool L3Hit, default="false", desc="Did memory or L3 supply the data?";
224  MachineID OriginalResponder, desc="Mach which wrote the data to the L3";
225
226  bool NotCached, default="false", desc="True when the Region buffer has already evicted the line";
227
228  bool NoAckNeeded, default="false", desc="For short circuting acks";
229  bool isValid, default="false", desc="Is acked block valid";
230
231  bool functionalRead(Packet *pkt) {
232    // Only PUTX messages contains the data block
233    if (Type == CoherenceResponseType:CPUData ||
234        Type == CoherenceResponseType:MemData) {
235        return testAndRead(addr, DataBlk, pkt);
236    }
237
238    return false;
239  }
240
241  bool functionalWrite(Packet *pkt) {
242    // No check on message type required since the protocol should
243    // read data from those messages that contain the block
244    return testAndWrite(addr, DataBlk, pkt);
245  }
246}
247
248structure(UnblockMsg, desc="...", interface="Message") {
249  Addr addr,              desc="Physical address for this request";
250  NetDest Destination,          desc="Destination (always directory)";
251  MessageSizeType MessageSize, desc="size category of the message";
252}
253
254enumeration(TriggerType, desc="Trigger Type") {
255  L2_to_L1,             desc="L2 to L1 fill";
256  AcksComplete,         desc="NB received all needed Acks";
257
258  // For regions
259  InvNext,              desc="Invalidate the next block";
260  PrivateAck,           desc="Loopback ack for machines with no Region Buffer";
261  AllOutstanding,       desc="All outstanding requests have finished";
262  L3Hit,                desc="L3 hit in dir";
263
264  // For region directory once the directory is blocked
265  InvRegion,            desc="Invalidate region";
266  DowngradeRegion,      desc="downgrade region";
267}
268
269enumeration(CacheId, desc="Which Cache in the Core") {
270  L1I,          desc="L1 I-cache";
271  L1D0,         desc="L1 D-cache cluster 0";
272  L1D1,         desc="L1 D-cache cluster 1";
273  NA,           desc="Default";
274}
275
276structure(TriggerMsg, desc="...", interface="Message") {
277  Addr addr,              desc="Address";
278  TriggerType Type,             desc="Type of trigger";
279  CacheId Dest,         default="CacheId_NA", desc="Cache to invalidate";
280
281  bool functionalRead(Packet *pkt) {
282    return false;
283  }
284
285  bool functionalWrite(Packet *pkt) {
286    // No check on message type required since the protocol should
287    // read data from those messages that contain the block
288    return false;
289  }
290
291}
292