1/* 2 * Copyright (c) 2010-2015 Advanced Micro Devices, Inc. 3 * All rights reserved. 4 * 5 * For use for simulation and test purposes only 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions are met: 9 * 10 * 1. Redistributions of source code must retain the above copyright notice, 11 * this list of conditions and the following disclaimer. 12 * 13 * 2. Redistributions in binary form must reproduce the above copyright notice, 14 * this list of conditions and the following disclaimer in the documentation 15 * and/or other materials provided with the distribution. 16 * 17 * 3. Neither the name of the copyright holder nor the names of its 18 * contributors may be used to endorse or promote products derived from this 19 * software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 * 33 * Authors: Lisa Hsu 34 */ 35 36machine(MachineType:CorePair, "CP-like Core Coherence") 37 : Sequencer * sequencer; 38 Sequencer * sequencer1; 39 CacheMemory * L1Icache; 40 CacheMemory * L1D0cache; 41 CacheMemory * L1D1cache; 42 CacheMemory * L2cache; // func mem logic looks in this CacheMemory 43 bool send_evictions := "False"; 44 Cycles issue_latency := 5; // time to send data down to NB 45 Cycles l2_hit_latency := 18; 46 47 // BEGIN Core Buffers 48 49 // To the Network 50 MessageBuffer * requestFromCore, network="To", virtual_network="0", vnet_type="request"; 51 MessageBuffer * responseFromCore, network="To", virtual_network="2", vnet_type="response"; 52 MessageBuffer * unblockFromCore, network="To", virtual_network="4", vnet_type="unblock"; 53 54 // From the Network 55 MessageBuffer * probeToCore, network="From", virtual_network="0", vnet_type="request"; 56 MessageBuffer * responseToCore, network="From", virtual_network="2", vnet_type="response"; 57 58 MessageBuffer * mandatoryQueue; 59 60 MessageBuffer * triggerQueue, ordered="true"; 61 62 // END Core Buffers 63 64{ 65 // BEGIN STATES 66 state_declaration(State, desc="Cache states", default="CorePair_State_I") { 67 68 // Base States 69 I, AccessPermission:Invalid, desc="Invalid"; 70 S, AccessPermission:Read_Only, desc="Shared"; 71 E0, AccessPermission:Read_Write, desc="Exclusive with Cluster 0 ownership"; 72 E1, AccessPermission:Read_Write, desc="Exclusive with Cluster 1 ownership"; 73 Es, AccessPermission:Read_Write, desc="Exclusive in core"; 74 O, AccessPermission:Read_Only, desc="Owner state in core, both clusters and other cores may be sharing line"; 75 Ms, AccessPermission:Read_Write, desc="Modified in core, both clusters may be sharing line"; 76 M0, AccessPermission:Read_Write, desc="Modified with cluster ownership"; 77 M1, AccessPermission:Read_Write, desc="Modified with cluster ownership"; 78 79 // Transient States 80 I_M0, AccessPermission:Busy, desc="Invalid, issued RdBlkM, have not seen response yet"; 81 I_M1, AccessPermission:Busy, desc="Invalid, issued RdBlkM, have not seen response yet"; 82 I_M0M1, AccessPermission:Busy, desc="Was in I_M0, got a store request from other cluster as well"; 83 I_M1M0, AccessPermission:Busy, desc="Was in I_M1, got a store request from other cluster as well"; 84 I_M0Ms, AccessPermission:Busy, desc="Was in I_M0, got a load request from other cluster as well"; 85 I_M1Ms, AccessPermission:Busy, desc="Was in I_M1, got a load request from other cluster as well"; 86 I_E0S, AccessPermission:Busy, desc="Invalid, issued RdBlk, have not seen response yet"; 87 I_E1S, AccessPermission:Busy, desc="Invalid, issued RdBlk, have not seen response yet"; 88 I_ES, AccessPermission:Busy, desc="S_F got hit by invalidating probe, RdBlk response needs to go to both clusters"; 89 90 IF_E0S, AccessPermission:Busy, desc="something got hit with Probe Invalidate, now just I_E0S but expecting a L2_to_L1D0 trigger, just drop when receive"; 91 IF_E1S, AccessPermission:Busy, desc="something got hit with Probe Invalidate, now just I_E1S but expecting a L2_to_L1D1 trigger, just drop when receive"; 92 IF_ES, AccessPermission:Busy, desc="same, but waiting for two fills"; 93 IF0_ES, AccessPermission:Busy, desc="same, but waiting for two fills, got one"; 94 IF1_ES, AccessPermission:Busy, desc="same, but waiting for two fills, got one"; 95 F_S0, AccessPermission:Busy, desc="same, but going to S0 when trigger received"; 96 F_S1, AccessPermission:Busy, desc="same, but going to S1 when trigger received"; 97 98 ES_I, AccessPermission:Read_Only, desc="L2 replacement, waiting for clean writeback ack"; 99 MO_I, AccessPermission:Read_Only, desc="L2 replacement, waiting for dirty writeback ack"; 100 MO_S0, AccessPermission:Read_Only, desc="M/O got Ifetch Miss, must write back first, then send RdBlkS"; 101 MO_S1, AccessPermission:Read_Only, desc="M/O got Ifetch Miss, must write back first, then send RdBlkS"; 102 S_F0, AccessPermission:Read_Only, desc="Shared, filling L1"; 103 S_F1, AccessPermission:Read_Only, desc="Shared, filling L1"; 104 S_F, AccessPermission:Read_Only, desc="Shared, filling L1"; 105 O_F0, AccessPermission:Read_Only, desc="Owned, filling L1"; 106 O_F1, AccessPermission:Read_Only, desc="Owned, filling L1"; 107 O_F, AccessPermission:Read_Only, desc="Owned, filling L1"; 108 Si_F0, AccessPermission:Read_Only, desc="Shared, filling icache"; 109 Si_F1, AccessPermission:Read_Only, desc="Shared, filling icache"; 110 S_M0, AccessPermission:Read_Only, desc="Shared, issued CtoD, have not seen response yet"; 111 S_M1, AccessPermission:Read_Only, desc="Shared, issued CtoD, have not seen response yet"; 112 O_M0, AccessPermission:Read_Only, desc="Shared, issued CtoD, have not seen response yet"; 113 O_M1, AccessPermission:Read_Only, desc="Shared, issued CtoD, have not seen response yet"; 114 S0, AccessPermission:Busy, desc="RdBlkS on behalf of cluster 0, waiting for response"; 115 S1, AccessPermission:Busy, desc="RdBlkS on behalf of cluster 1, waiting for response"; 116 117 Es_F0, AccessPermission:Read_Write, desc="Es, Cluster read, filling"; 118 Es_F1, AccessPermission:Read_Write, desc="Es, Cluster read, filling"; 119 Es_F, AccessPermission:Read_Write, desc="Es, other cluster read, filling"; 120 E0_F, AccessPermission:Read_Write, desc="E0, cluster read, filling"; 121 E1_F, AccessPermission:Read_Write, desc="..."; 122 E0_Es, AccessPermission:Read_Write, desc="..."; 123 E1_Es, AccessPermission:Read_Write, desc="..."; 124 Ms_F0, AccessPermission:Read_Write, desc="..."; 125 Ms_F1, AccessPermission:Read_Write, desc="..."; 126 Ms_F, AccessPermission:Read_Write, desc="..."; 127 M0_F, AccessPermission:Read_Write, desc="..."; 128 M0_Ms, AccessPermission:Read_Write, desc="..."; 129 M1_F, AccessPermission:Read_Write, desc="..."; 130 M1_Ms, AccessPermission:Read_Write, desc="..."; 131 132 I_C, AccessPermission:Invalid, desc="Invalid, but waiting for WBAck from NB from canceled writeback"; 133 S0_C, AccessPermission:Busy, desc="MO_S0 hit by invalidating probe, waiting for WBAck form NB for canceled WB"; 134 S1_C, AccessPermission:Busy, desc="MO_S1 hit by invalidating probe, waiting for WBAck form NB for canceled WB"; 135 S_C, AccessPermission:Busy, desc="S*_C got NB_AckS, still waiting for WBAck"; 136 137 } // END STATES 138 139 // BEGIN EVENTS 140 enumeration(Event, desc="CP Events") { 141 // CP Initiated events 142 C0_Load_L1miss, desc="Cluster 0 load, L1 missed"; 143 C0_Load_L1hit, desc="Cluster 0 load, L1 hit"; 144 C1_Load_L1miss, desc="Cluster 1 load L1 missed"; 145 C1_Load_L1hit, desc="Cluster 1 load L1 hit"; 146 Ifetch0_L1hit, desc="Instruction fetch, hit in the L1"; 147 Ifetch1_L1hit, desc="Instruction fetch, hit in the L1"; 148 Ifetch0_L1miss, desc="Instruction fetch, missed in the L1"; 149 Ifetch1_L1miss, desc="Instruction fetch, missed in the L1"; 150 C0_Store_L1miss, desc="Cluster 0 store missed in L1"; 151 C0_Store_L1hit, desc="Cluster 0 store hit in L1"; 152 C1_Store_L1miss, desc="Cluster 1 store missed in L1"; 153 C1_Store_L1hit, desc="Cluster 1 store hit in L1"; 154 // NB Initiated events 155 NB_AckS, desc="NB Ack to Core Request"; 156 NB_AckM, desc="NB Ack to Core Request"; 157 NB_AckE, desc="NB Ack to Core Request"; 158 159 NB_AckWB, desc="NB Ack for writeback"; 160 161 // Memory System initiatied events 162 L1I_Repl, desc="Replace address from L1I"; // Presumed clean 163 L1D0_Repl, desc="Replace address from L1D0"; // Presumed clean 164 L1D1_Repl, desc="Replace address from L1D1"; // Presumed clean 165 L2_Repl, desc="Replace address from L2"; 166 167 L2_to_L1D0, desc="L1 fill from L2"; 168 L2_to_L1D1, desc="L1 fill from L2"; 169 L2_to_L1I, desc="L1 fill from L2"; 170 171 // Probe Events 172 PrbInvData, desc="probe, return O or M data"; 173 PrbInv, desc="probe, no need for data"; 174 PrbShrData, desc="probe downgrade, return O or M data"; 175 176 } // END EVENTS 177 178 enumeration(RequestType, desc="To communicate stats from transitions to recordStats") { 179 L1D0DataArrayRead, desc="Read the data array"; 180 L1D0DataArrayWrite, desc="Write the data array"; 181 L1D0TagArrayRead, desc="Read the data array"; 182 L1D0TagArrayWrite, desc="Write the data array"; 183 L1D1DataArrayRead, desc="Read the data array"; 184 L1D1DataArrayWrite, desc="Write the data array"; 185 L1D1TagArrayRead, desc="Read the data array"; 186 L1D1TagArrayWrite, desc="Write the data array"; 187 L1IDataArrayRead, desc="Read the data array"; 188 L1IDataArrayWrite, desc="Write the data array"; 189 L1ITagArrayRead, desc="Read the data array"; 190 L1ITagArrayWrite, desc="Write the data array"; 191 L2DataArrayRead, desc="Read the data array"; 192 L2DataArrayWrite, desc="Write the data array"; 193 L2TagArrayRead, desc="Read the data array"; 194 L2TagArrayWrite, desc="Write the data array"; 195 } 196 197 198 // BEGIN STRUCTURE DEFINITIONS 199 200 201 // Cache Entry 202 structure(Entry, desc="...", interface="AbstractCacheEntry") { 203 State CacheState, desc="cache state"; 204 bool Dirty, desc="Is the data dirty (diff than memory)?"; 205 DataBlock DataBlk, desc="data for the block"; 206 bool FromL2, default="false", desc="block just moved from L2"; 207 } 208 209 structure(TBE, desc="...") { 210 State TBEState, desc="Transient state"; 211 DataBlock DataBlk, desc="data for the block, required for concurrent writebacks"; 212 bool Dirty, desc="Is the data dirty (different than memory)?"; 213 int NumPendingMsgs, desc="Number of acks/data messages that this processor is waiting for"; 214 bool Shared, desc="Victim hit by shared probe"; 215 } 216 217 structure(TBETable, external="yes") { 218 TBE lookup(Addr); 219 void allocate(Addr); 220 void deallocate(Addr); 221 bool isPresent(Addr); 222 } 223 224 TBETable TBEs, template="<CorePair_TBE>", constructor="m_number_of_TBEs"; 225 226 void set_cache_entry(AbstractCacheEntry b); 227 void unset_cache_entry(); 228 void set_tbe(TBE b); 229 void unset_tbe(); 230 void wakeUpAllBuffers(); 231 void wakeUpBuffers(Addr a); 232 Cycles curCycle(); 233 MachineID mapAddressToMachine(Addr addr, MachineType mtype); 234 235 // END STRUCTURE DEFINITIONS 236 237 // BEGIN INTERNAL FUNCTIONS 238 239 Tick clockEdge(); 240 Tick cyclesToTicks(Cycles c); 241 242 bool addressInCore(Addr addr) { 243 return (L2cache.isTagPresent(addr) || L1Icache.isTagPresent(addr) || L1D0cache.isTagPresent(addr) || L1D1cache.isTagPresent(addr)); 244 } 245 246 Entry getCacheEntry(Addr address), return_by_pointer="yes" { 247 Entry L2cache_entry := static_cast(Entry, "pointer", L2cache.lookup(address)); 248 return L2cache_entry; 249 } 250 251 DataBlock getDataBlock(Addr addr), return_by_ref="yes" { 252 TBE tbe := TBEs.lookup(addr); 253 if(is_valid(tbe)) { 254 return tbe.DataBlk; 255 } else { 256 return getCacheEntry(addr).DataBlk; 257 } 258 } 259 260 Entry getL1CacheEntry(Addr addr, int cluster), return_by_pointer="yes" { 261 if (cluster == 0) { 262 Entry L1D0_entry := static_cast(Entry, "pointer", L1D0cache.lookup(addr)); 263 return L1D0_entry; 264 } else { 265 Entry L1D1_entry := static_cast(Entry, "pointer", L1D1cache.lookup(addr)); 266 return L1D1_entry; 267 } 268 } 269 270 Entry getICacheEntry(Addr addr), return_by_pointer="yes" { 271 Entry c_entry := static_cast(Entry, "pointer", L1Icache.lookup(addr)); 272 return c_entry; 273 } 274 275 bool presentOrAvail2(Addr addr) { 276 return L2cache.isTagPresent(addr) || L2cache.cacheAvail(addr); 277 } 278 279 bool presentOrAvailI(Addr addr) { 280 return L1Icache.isTagPresent(addr) || L1Icache.cacheAvail(addr); 281 } 282 283 bool presentOrAvailD0(Addr addr) { 284 return L1D0cache.isTagPresent(addr) || L1D0cache.cacheAvail(addr); 285 } 286 287 bool presentOrAvailD1(Addr addr) { 288 return L1D1cache.isTagPresent(addr) || L1D1cache.cacheAvail(addr); 289 } 290 291 State getState(TBE tbe, Entry cache_entry, Addr addr) { 292 if(is_valid(tbe)) { 293 return tbe.TBEState; 294 } else if (is_valid(cache_entry)) { 295 return cache_entry.CacheState; 296 } 297 return State:I; 298 } 299 300 void setState(TBE tbe, Entry cache_entry, Addr addr, State state) { 301 if (is_valid(tbe)) { 302 tbe.TBEState := state; 303 } 304 305 if (is_valid(cache_entry)) { 306 cache_entry.CacheState := state; 307 } 308 } 309 310 AccessPermission getAccessPermission(Addr addr) { 311 TBE tbe := TBEs.lookup(addr); 312 if(is_valid(tbe)) { 313 return CorePair_State_to_permission(tbe.TBEState); 314 } 315 316 Entry cache_entry := getCacheEntry(addr); 317 if(is_valid(cache_entry)) { 318 return CorePair_State_to_permission(cache_entry.CacheState); 319 } 320 321 return AccessPermission:NotPresent; 322 } 323 324 void functionalRead(Addr addr, Packet *pkt) { 325 TBE tbe := TBEs.lookup(addr); 326 if(is_valid(tbe)) { 327 testAndRead(addr, tbe.DataBlk, pkt); 328 } else { 329 functionalMemoryRead(pkt); 330 } 331 } 332 333 int functionalWrite(Addr addr, Packet *pkt) { 334 int num_functional_writes := 0; 335 336 TBE tbe := TBEs.lookup(addr); 337 if(is_valid(tbe)) { 338 num_functional_writes := num_functional_writes + 339 testAndWrite(addr, tbe.DataBlk, pkt); 340 } 341 342 num_functional_writes := num_functional_writes + functionalMemoryWrite(pkt); 343 return num_functional_writes; 344 } 345 346 void setAccessPermission(Entry cache_entry, Addr addr, State state) { 347 if (is_valid(cache_entry)) { 348 cache_entry.changePermission(CorePair_State_to_permission(state)); 349 } 350 } 351 352 MachineType testAndClearLocalHit(Entry cache_entry) { 353 assert(is_valid(cache_entry)); 354 if (cache_entry.FromL2) { 355 cache_entry.FromL2 := false; 356 return MachineType:L2Cache; 357 } else { 358 return MachineType:L1Cache; 359 } 360 } 361 362 void recordRequestType(RequestType request_type, Addr addr) { 363 if (request_type == RequestType:L1D0DataArrayRead) { 364 L1D0cache.recordRequestType(CacheRequestType:DataArrayRead, addr); 365 } else if (request_type == RequestType:L1D0DataArrayWrite) { 366 L1D0cache.recordRequestType(CacheRequestType:DataArrayWrite, addr); 367 } else if (request_type == RequestType:L1D0TagArrayRead) { 368 L1D0cache.recordRequestType(CacheRequestType:TagArrayRead, addr); 369 } else if (request_type == RequestType:L1D0TagArrayWrite) { 370 L1D0cache.recordRequestType(CacheRequestType:TagArrayWrite, addr); 371 } else if (request_type == RequestType:L1D1DataArrayRead) { 372 L1D1cache.recordRequestType(CacheRequestType:DataArrayRead, addr); 373 } else if (request_type == RequestType:L1D1DataArrayWrite) { 374 L1D1cache.recordRequestType(CacheRequestType:DataArrayWrite, addr); 375 } else if (request_type == RequestType:L1D1TagArrayRead) { 376 L1D1cache.recordRequestType(CacheRequestType:TagArrayRead, addr); 377 } else if (request_type == RequestType:L1D1TagArrayWrite) { 378 L1D1cache.recordRequestType(CacheRequestType:TagArrayWrite, addr); 379 } else if (request_type == RequestType:L1IDataArrayRead) { 380 L1Icache.recordRequestType(CacheRequestType:DataArrayRead, addr); 381 } else if (request_type == RequestType:L1IDataArrayWrite) { 382 L1Icache.recordRequestType(CacheRequestType:DataArrayWrite, addr); 383 } else if (request_type == RequestType:L1ITagArrayRead) { 384 L1Icache.recordRequestType(CacheRequestType:TagArrayRead, addr); 385 } else if (request_type == RequestType:L1ITagArrayWrite) { 386 L1Icache.recordRequestType(CacheRequestType:TagArrayWrite, addr); 387 } else if (request_type == RequestType:L2DataArrayRead) { 388 L2cache.recordRequestType(CacheRequestType:DataArrayRead, addr); 389 } else if (request_type == RequestType:L2DataArrayWrite) { 390 L2cache.recordRequestType(CacheRequestType:DataArrayWrite, addr); 391 } else if (request_type == RequestType:L2TagArrayRead) { 392 L2cache.recordRequestType(CacheRequestType:TagArrayRead, addr); 393 } else if (request_type == RequestType:L2TagArrayWrite) { 394 L2cache.recordRequestType(CacheRequestType:TagArrayWrite, addr); 395 } 396 } 397 398 bool checkResourceAvailable(RequestType request_type, Addr addr) { 399 if (request_type == RequestType:L2DataArrayRead) { 400 return L2cache.checkResourceAvailable(CacheResourceType:DataArray, addr); 401 } else if (request_type == RequestType:L2DataArrayWrite) { 402 return L2cache.checkResourceAvailable(CacheResourceType:DataArray, addr); 403 } else if (request_type == RequestType:L2TagArrayRead) { 404 return L2cache.checkResourceAvailable(CacheResourceType:TagArray, addr); 405 } else if (request_type == RequestType:L2TagArrayWrite) { 406 return L2cache.checkResourceAvailable(CacheResourceType:TagArray, addr); 407 } else if (request_type == RequestType:L1D0DataArrayRead) { 408 return L1D0cache.checkResourceAvailable(CacheResourceType:DataArray, addr); 409 } else if (request_type == RequestType:L1D0DataArrayWrite) { 410 return L1D0cache.checkResourceAvailable(CacheResourceType:DataArray, addr); 411 } else if (request_type == RequestType:L1D0TagArrayRead) { 412 return L1D0cache.checkResourceAvailable(CacheResourceType:TagArray, addr); 413 } else if (request_type == RequestType:L1D0TagArrayWrite) { 414 return L1D0cache.checkResourceAvailable(CacheResourceType:TagArray, addr); 415 } else if (request_type == RequestType:L1D1DataArrayRead) { 416 return L1D1cache.checkResourceAvailable(CacheResourceType:DataArray, addr); 417 } else if (request_type == RequestType:L1D1DataArrayWrite) { 418 return L1D1cache.checkResourceAvailable(CacheResourceType:DataArray, addr); 419 } else if (request_type == RequestType:L1D1TagArrayRead) { 420 return L1D1cache.checkResourceAvailable(CacheResourceType:TagArray, addr); 421 } else if (request_type == RequestType:L1D1TagArrayWrite) { 422 return L1D1cache.checkResourceAvailable(CacheResourceType:TagArray, addr); 423 } else if (request_type == RequestType:L1IDataArrayRead) { 424 return L1Icache.checkResourceAvailable(CacheResourceType:DataArray, addr); 425 } else if (request_type == RequestType:L1IDataArrayWrite) { 426 return L1Icache.checkResourceAvailable(CacheResourceType:DataArray, addr); 427 } else if (request_type == RequestType:L1ITagArrayRead) { 428 return L1Icache.checkResourceAvailable(CacheResourceType:TagArray, addr); 429 } else if (request_type == RequestType:L1ITagArrayWrite) { 430 return L1Icache.checkResourceAvailable(CacheResourceType:TagArray, addr); 431 432 } else { 433 return true; 434 } 435 } 436 437 // END INTERNAL FUNCTIONS 438 439 // ** OUT_PORTS ** 440 441 out_port(requestNetwork_out, CPURequestMsg, requestFromCore); 442 out_port(responseNetwork_out, ResponseMsg, responseFromCore); 443 out_port(triggerQueue_out, TriggerMsg, triggerQueue); 444 out_port(unblockNetwork_out, UnblockMsg, unblockFromCore); 445 446 // ** IN_PORTS ** 447 448 in_port(triggerQueue_in, TriggerMsg, triggerQueue, block_on="addr") { 449 if (triggerQueue_in.isReady(clockEdge())) { 450 peek(triggerQueue_in, TriggerMsg) { 451 Entry cache_entry := getCacheEntry(in_msg.addr); 452 TBE tbe := TBEs.lookup(in_msg.addr); 453 454 if (in_msg.Type == TriggerType:L2_to_L1) { 455 if (in_msg.Dest == CacheId:L1I) { 456 trigger(Event:L2_to_L1I, in_msg.addr, cache_entry, tbe); 457 } else if (in_msg.Dest == CacheId:L1D0) { 458 trigger(Event:L2_to_L1D0, in_msg.addr, cache_entry, tbe); 459 } else if (in_msg.Dest == CacheId:L1D1) { 460 trigger(Event:L2_to_L1D1, in_msg.addr, cache_entry, tbe); 461 } else { 462 error("unexpected trigger dest"); 463 } 464 } 465 } 466 } 467 } 468 469 470 in_port(probeNetwork_in, NBProbeRequestMsg, probeToCore) { 471 if (probeNetwork_in.isReady(clockEdge())) { 472 peek(probeNetwork_in, NBProbeRequestMsg, block_on="addr") { 473 Entry cache_entry := getCacheEntry(in_msg.addr); 474 TBE tbe := TBEs.lookup(in_msg.addr); 475 476 if (in_msg.Type == ProbeRequestType:PrbInv) { 477 if (in_msg.ReturnData) { 478 trigger(Event:PrbInvData, in_msg.addr, cache_entry, tbe); 479 } else { 480 trigger(Event:PrbInv, in_msg.addr, cache_entry, tbe); 481 } 482 } else if (in_msg.Type == ProbeRequestType:PrbDowngrade) { 483 assert(in_msg.ReturnData); 484 trigger(Event:PrbShrData, in_msg.addr, cache_entry, tbe); 485 } 486 } 487 } 488 } 489 490 491 // ResponseNetwork 492 in_port(responseToCore_in, ResponseMsg, responseToCore) { 493 if (responseToCore_in.isReady(clockEdge())) { 494 peek(responseToCore_in, ResponseMsg, block_on="addr") { 495 496 Entry cache_entry := getCacheEntry(in_msg.addr); 497 TBE tbe := TBEs.lookup(in_msg.addr); 498 499 if (in_msg.Type == CoherenceResponseType:NBSysResp) { 500 if (in_msg.State == CoherenceState:Modified) { 501 trigger(Event:NB_AckM, in_msg.addr, cache_entry, tbe); 502 } else if (in_msg.State == CoherenceState:Shared) { 503 trigger(Event:NB_AckS, in_msg.addr, cache_entry, tbe); 504 } else if (in_msg.State == CoherenceState:Exclusive) { 505 trigger(Event:NB_AckE, in_msg.addr, cache_entry, tbe); 506 } 507 } else if (in_msg.Type == CoherenceResponseType:NBSysWBAck) { 508 trigger(Event:NB_AckWB, in_msg.addr, cache_entry, tbe); 509 } else { 510 error("Unexpected Response Message to Core"); 511 } 512 } 513 } 514 } 515 516 // Nothing from the Unblock Network 517 518 // Mandatory Queue 519 in_port(mandatoryQueue_in, RubyRequest, mandatoryQueue, desc="...") { 520 if (mandatoryQueue_in.isReady(clockEdge())) { 521 peek(mandatoryQueue_in, RubyRequest, block_on="LineAddress") { 522 523 Entry cache_entry := getCacheEntry(in_msg.LineAddress); 524 TBE tbe := TBEs.lookup(in_msg.LineAddress); 525 526 if (in_msg.Type == RubyRequestType:IFETCH) { 527 // FETCH ACCESS 528 529 if (L1Icache.isTagPresent(in_msg.LineAddress)) { 530 if (mod(in_msg.contextId, 2) == 0) { 531 trigger(Event:Ifetch0_L1hit, in_msg.LineAddress, cache_entry, tbe); 532 } else { 533 trigger(Event:Ifetch1_L1hit, in_msg.LineAddress, cache_entry, tbe); 534 } 535 } else { 536 if (presentOrAvail2(in_msg.LineAddress)) { 537 if (presentOrAvailI(in_msg.LineAddress)) { 538 if (mod(in_msg.contextId, 2) == 0) { 539 trigger(Event:Ifetch0_L1miss, in_msg.LineAddress, cache_entry, 540 tbe); 541 } else { 542 trigger(Event:Ifetch1_L1miss, in_msg.LineAddress, cache_entry, 543 tbe); 544 } 545 } else { 546 // Check if the line we want to evict is not locked 547 Addr victim := L1Icache.cacheProbe(in_msg.LineAddress); 548 check_on_cache_probe(mandatoryQueue_in, victim); 549 trigger(Event:L1I_Repl, victim, 550 getCacheEntry(victim), TBEs.lookup(victim)); 551 } 552 } else { // Not present or avail in L2 553 Addr victim := L2cache.cacheProbe(in_msg.LineAddress); 554 trigger(Event:L2_Repl, victim, getCacheEntry(victim), 555 TBEs.lookup(victim)); 556 } 557 } 558 } else { 559 // DATA ACCESS 560 if (mod(in_msg.contextId, 2) == 1) { 561 if (L1D1cache.isTagPresent(in_msg.LineAddress)) { 562 if (in_msg.Type == RubyRequestType:LD) { 563 trigger(Event:C1_Load_L1hit, in_msg.LineAddress, cache_entry, 564 tbe); 565 } else { 566 // Stores must write through, make sure L2 avail. 567 if (presentOrAvail2(in_msg.LineAddress)) { 568 trigger(Event:C1_Store_L1hit, in_msg.LineAddress, cache_entry, 569 tbe); 570 } else { 571 Addr victim := L2cache.cacheProbe(in_msg.LineAddress); 572 trigger(Event:L2_Repl, victim, getCacheEntry(victim), 573 TBEs.lookup(victim)); 574 } 575 } 576 } else { 577 if (presentOrAvail2(in_msg.LineAddress)) { 578 if (presentOrAvailD1(in_msg.LineAddress)) { 579 if (in_msg.Type == RubyRequestType:LD) { 580 trigger(Event:C1_Load_L1miss, in_msg.LineAddress, 581 cache_entry, tbe); 582 } else { 583 trigger(Event:C1_Store_L1miss, in_msg.LineAddress, 584 cache_entry, tbe); 585 } 586 } else { 587 // Check if the line we want to evict is not locked 588 Addr victim := L1D1cache.cacheProbe(in_msg.LineAddress); 589 check_on_cache_probe(mandatoryQueue_in, victim); 590 trigger(Event:L1D1_Repl, victim, 591 getCacheEntry(victim), TBEs.lookup(victim)); 592 } 593 } else { // not present or avail in L2 594 Addr victim := L2cache.cacheProbe(in_msg.LineAddress); 595 trigger(Event:L2_Repl, victim, getCacheEntry(victim), TBEs.lookup(victim)); 596 } 597 } 598 } else { 599 Entry L1D0cache_entry := getL1CacheEntry(in_msg.LineAddress, 0); 600 if (is_valid(L1D0cache_entry)) { 601 if (in_msg.Type == RubyRequestType:LD) { 602 trigger(Event:C0_Load_L1hit, in_msg.LineAddress, cache_entry, 603 tbe); 604 } else { 605 if (presentOrAvail2(in_msg.LineAddress)) { 606 trigger(Event:C0_Store_L1hit, in_msg.LineAddress, cache_entry, 607 tbe); 608 } else { 609 Addr victim := L2cache.cacheProbe(in_msg.LineAddress); 610 trigger(Event:L2_Repl, victim, getCacheEntry(victim), 611 TBEs.lookup(victim)); 612 } 613 } 614 } else { 615 if (presentOrAvail2(in_msg.LineAddress)) { 616 if (presentOrAvailD0(in_msg.LineAddress)) { 617 if (in_msg.Type == RubyRequestType:LD) { 618 trigger(Event:C0_Load_L1miss, in_msg.LineAddress, 619 cache_entry, tbe); 620 } else { 621 trigger(Event:C0_Store_L1miss, in_msg.LineAddress, 622 cache_entry, tbe); 623 } 624 } else { 625 // Check if the line we want to evict is not locked 626 Addr victim := L1D0cache.cacheProbe(in_msg.LineAddress); 627 check_on_cache_probe(mandatoryQueue_in, victim); 628 trigger(Event:L1D0_Repl, victim, getCacheEntry(victim), 629 TBEs.lookup(victim)); 630 } 631 } else { 632 Addr victim := L2cache.cacheProbe(in_msg.LineAddress); 633 trigger(Event:L2_Repl, victim, getCacheEntry(victim), 634 TBEs.lookup(victim)); 635 } 636 } 637 } 638 } 639 } 640 } 641 } 642 643 644 // ACTIONS 645 action(ii_invIcache, "ii", desc="invalidate iCache") { 646 if (L1Icache.isTagPresent(address)) { 647 L1Icache.deallocate(address); 648 } 649 } 650 651 action(i0_invCluster, "i0", desc="invalidate cluster 0") { 652 if (L1D0cache.isTagPresent(address)) { 653 L1D0cache.deallocate(address); 654 } 655 } 656 657 action(i1_invCluster, "i1", desc="invalidate cluster 1") { 658 if (L1D1cache.isTagPresent(address)) { 659 L1D1cache.deallocate(address); 660 } 661 } 662 663 action(ib_invBothClusters, "ib", desc="invalidate both clusters") { 664 if (L1D0cache.isTagPresent(address)) { 665 L1D0cache.deallocate(address); 666 } 667 if (L1D1cache.isTagPresent(address)) { 668 L1D1cache.deallocate(address); 669 } 670 } 671 672 action(i2_invL2, "i2", desc="invalidate L2") { 673 if(is_valid(cache_entry)) { 674 L2cache.deallocate(address); 675 } 676 unset_cache_entry(); 677 } 678 679 action(mru_setMRU, "mru", desc="Update LRU state") { 680 L2cache.setMRU(address); 681 } 682 683 action(mruD1_setD1cacheMRU, "mruD1", desc="Update LRU state") { 684 L1D1cache.setMRU(address); 685 } 686 687 action(mruD0_setD0cacheMRU, "mruD0", desc="Update LRU state") { 688 L1D0cache.setMRU(address); 689 } 690 691 action(mruI_setIcacheMRU, "mruI", desc="Update LRU state") { 692 L1Icache.setMRU(address); 693 } 694 695 action(n_issueRdBlk, "n", desc="Issue RdBlk") { 696 enqueue(requestNetwork_out, CPURequestMsg, issue_latency) { 697 out_msg.addr := address; 698 out_msg.Type := CoherenceRequestType:RdBlk; 699 out_msg.Requestor := machineID; 700 out_msg.Destination.add(mapAddressToMachine(address, MachineType:Directory)); 701 DPRINTF(RubySlicc,"%s\n",out_msg.Destination); 702 out_msg.MessageSize := MessageSizeType:Request_Control; 703 out_msg.InitialRequestTime := curCycle(); 704 } 705 } 706 707 action(nM_issueRdBlkM, "nM", desc="Issue RdBlkM") { 708 enqueue(requestNetwork_out, CPURequestMsg, issue_latency) { 709 out_msg.addr := address; 710 out_msg.Type := CoherenceRequestType:RdBlkM; 711 out_msg.Requestor := machineID; 712 out_msg.Destination.add(mapAddressToMachine(address, MachineType:Directory)); 713 out_msg.MessageSize := MessageSizeType:Request_Control; 714 out_msg.InitialRequestTime := curCycle(); 715 } 716 } 717 718 action(nS_issueRdBlkS, "nS", desc="Issue RdBlkS") { 719 enqueue(requestNetwork_out, CPURequestMsg, issue_latency) { 720 out_msg.addr := address; 721 out_msg.Type := CoherenceRequestType:RdBlkS; 722 out_msg.Requestor := machineID; 723 out_msg.Destination.add(mapAddressToMachine(address, MachineType:Directory)); 724 out_msg.MessageSize := MessageSizeType:Request_Control; 725 out_msg.InitialRequestTime := curCycle(); 726 } 727 } 728 729 action(vd_victim, "vd", desc="Victimize M/O L2 Data") { 730 enqueue(requestNetwork_out, CPURequestMsg, issue_latency) { 731 out_msg.addr := address; 732 out_msg.Requestor := machineID; 733 assert(is_valid(cache_entry)); 734 out_msg.DataBlk := cache_entry.DataBlk; 735 assert(cache_entry.Dirty); 736 out_msg.Destination.add(mapAddressToMachine(address, MachineType:Directory)); 737 out_msg.MessageSize := MessageSizeType:Request_Control; 738 out_msg.Type := CoherenceRequestType:VicDirty; 739 out_msg.InitialRequestTime := curCycle(); 740 if (cache_entry.CacheState == State:O) { 741 out_msg.Shared := true; 742 } else { 743 out_msg.Shared := false; 744 } 745 } 746 } 747 748 action(vc_victim, "vc", desc="Victimize E/S L2 Data") { 749 enqueue(requestNetwork_out, CPURequestMsg, issue_latency) { 750 out_msg.addr := address; 751 out_msg.Requestor := machineID; 752 out_msg.Destination.add(mapAddressToMachine(address, MachineType:Directory)); 753 out_msg.MessageSize := MessageSizeType:Request_Control; 754 out_msg.Type := CoherenceRequestType:VicClean; 755 out_msg.InitialRequestTime := curCycle(); 756 if (cache_entry.CacheState == State:S) { 757 out_msg.Shared := true; 758 } else { 759 out_msg.Shared := false; 760 } 761 } 762 } 763 764 action(a0_allocateL1D, "a0", desc="Allocate L1D0 Block") { 765 if (L1D0cache.isTagPresent(address) == false) { 766 L1D0cache.allocateVoid(address, new Entry); 767 } 768 } 769 770 action(a1_allocateL1D, "a1", desc="Allocate L1D1 Block") { 771 if (L1D1cache.isTagPresent(address) == false) { 772 L1D1cache.allocateVoid(address, new Entry); 773 } 774 } 775 776 action(ai_allocateL1I, "ai", desc="Allocate L1I Block") { 777 if (L1Icache.isTagPresent(address) == false) { 778 L1Icache.allocateVoid(address, new Entry); 779 } 780 } 781 782 action(a2_allocateL2, "a2", desc="Allocate L2 Block") { 783 if (is_invalid(cache_entry)) { 784 set_cache_entry(L2cache.allocate(address, new Entry)); 785 } 786 } 787 788 action(t_allocateTBE, "t", desc="allocate TBE Entry") { 789 check_allocate(TBEs); 790 assert(is_valid(cache_entry)); 791 TBEs.allocate(address); 792 set_tbe(TBEs.lookup(address)); 793 tbe.DataBlk := cache_entry.DataBlk; // Data only used for WBs 794 tbe.Dirty := cache_entry.Dirty; 795 tbe.Shared := false; 796 } 797 798 action(d_deallocateTBE, "d", desc="Deallocate TBE") { 799 TBEs.deallocate(address); 800 unset_tbe(); 801 } 802 803 action(p_popMandatoryQueue, "pm", desc="Pop Mandatory Queue") { 804 mandatoryQueue_in.dequeue(clockEdge()); 805 } 806 807 action(pr_popResponseQueue, "pr", desc="Pop Response Queue") { 808 responseToCore_in.dequeue(clockEdge()); 809 } 810 811 action(pt_popTriggerQueue, "pt", desc="Pop Trigger Queue") { 812 triggerQueue_in.dequeue(clockEdge()); 813 } 814 815 action(pp_popProbeQueue, "pp", desc="pop probe queue") { 816 probeNetwork_in.dequeue(clockEdge()); 817 } 818 819 action(il0_loadDone, "il0", desc="Cluster 0 i load done") { 820 Entry entry := getICacheEntry(address); 821 Entry l2entry := getCacheEntry(address); // Used for functional accesses 822 assert(is_valid(entry)); 823 // L2 supplies data (functional accesses only look in L2, ok because L1 824 // writes through to L2) 825 sequencer.readCallback(address, 826 l2entry.DataBlk, 827 true, 828 testAndClearLocalHit(entry)); 829 } 830 831 action(il1_loadDone, "il1", desc="Cluster 1 i load done") { 832 Entry entry := getICacheEntry(address); 833 Entry l2entry := getCacheEntry(address); // Used for functional accesses 834 assert(is_valid(entry)); 835 // L2 supplies data (functional accesses only look in L2, ok because L1 836 // writes through to L2) 837 sequencer1.readCallback(address, 838 l2entry.DataBlk, 839 true, 840 testAndClearLocalHit(entry)); 841 } 842 843 action(l0_loadDone, "l0", desc="Cluster 0 load done") { 844 Entry entry := getL1CacheEntry(address, 0); 845 Entry l2entry := getCacheEntry(address); // Used for functional accesses 846 assert(is_valid(entry)); 847 // L2 supplies data (functional accesses only look in L2, ok because L1 848 // writes through to L2) 849 sequencer.readCallback(address, 850 l2entry.DataBlk, 851 true, 852 testAndClearLocalHit(entry)); 853 } 854 855 action(l1_loadDone, "l1", desc="Cluster 1 load done") { 856 Entry entry := getL1CacheEntry(address, 1); 857 Entry l2entry := getCacheEntry(address); // Used for functional accesses 858 assert(is_valid(entry)); 859 // L2 supplies data (functional accesses only look in L2, ok because L1 860 // writes through to L2) 861 sequencer1.readCallback(address, 862 l2entry.DataBlk, 863 true, 864 testAndClearLocalHit(entry)); 865 } 866 867 action(xl0_loadDone, "xl0", desc="Cluster 0 load done") { 868 peek(responseToCore_in, ResponseMsg) { 869 assert((machineIDToMachineType(in_msg.Sender) == MachineType:Directory) || 870 (machineIDToMachineType(in_msg.Sender) == MachineType:L3Cache)); 871 Entry l2entry := getCacheEntry(address); // Used for functional accesses 872 DPRINTF(ProtocolTrace, "CP Load Done 0 -- address %s, data: %s\n", address, l2entry.DataBlk); 873 // L2 supplies data (functional accesses only look in L2, ok because L1 874 // writes through to L2) 875 sequencer.readCallback(address, 876 l2entry.DataBlk, 877 false, 878 machineIDToMachineType(in_msg.Sender), 879 in_msg.InitialRequestTime, 880 in_msg.ForwardRequestTime, 881 in_msg.ProbeRequestStartTime); 882 } 883 } 884 885 action(xl1_loadDone, "xl1", desc="Cluster 1 load done") { 886 peek(responseToCore_in, ResponseMsg) { 887 assert((machineIDToMachineType(in_msg.Sender) == MachineType:Directory) || 888 (machineIDToMachineType(in_msg.Sender) == MachineType:L3Cache)); 889 Entry l2entry := getCacheEntry(address); // Used for functional accesses 890 // L2 supplies data (functional accesses only look in L2, ok because L1 891 // writes through to L2) 892 sequencer1.readCallback(address, 893 l2entry.DataBlk, 894 false, 895 machineIDToMachineType(in_msg.Sender), 896 in_msg.InitialRequestTime, 897 in_msg.ForwardRequestTime, 898 in_msg.ProbeRequestStartTime); 899 } 900 } 901 902 action(xi0_loadDone, "xi0", desc="Cluster 0 i-load done") { 903 peek(responseToCore_in, ResponseMsg) { 904 assert((machineIDToMachineType(in_msg.Sender) == MachineType:Directory) || 905 (machineIDToMachineType(in_msg.Sender) == MachineType:L3Cache)); 906 Entry l2entry := getCacheEntry(address); // Used for functional accesses 907 // L2 supplies data (functional accesses only look in L2, ok because L1 908 // writes through to L2) 909 sequencer.readCallback(address, 910 l2entry.DataBlk, 911 false, 912 machineIDToMachineType(in_msg.Sender), 913 in_msg.InitialRequestTime, 914 in_msg.ForwardRequestTime, 915 in_msg.ProbeRequestStartTime); 916 } 917 } 918 919 action(xi1_loadDone, "xi1", desc="Cluster 1 i-load done") { 920 peek(responseToCore_in, ResponseMsg) { 921 assert((machineIDToMachineType(in_msg.Sender) == MachineType:Directory) || 922 (machineIDToMachineType(in_msg.Sender) == MachineType:L3Cache)); 923 Entry l2entry := getCacheEntry(address); // Used for functional accesses 924 // L2 supplies data (functional accesses only look in L2, ok because L1 925 // writes through to L2) 926 sequencer1.readCallback(address, 927 l2entry.DataBlk, 928 false, 929 machineIDToMachineType(in_msg.Sender), 930 in_msg.InitialRequestTime, 931 in_msg.ForwardRequestTime, 932 in_msg.ProbeRequestStartTime); 933 } 934 } 935 936 action(s0_storeDone, "s0", desc="Cluster 0 store done") { 937 Entry entry := getL1CacheEntry(address, 0); 938 assert(is_valid(entry)); 939 assert(is_valid(cache_entry)); 940 sequencer.writeCallback(address, 941 cache_entry.DataBlk, 942 true, 943 testAndClearLocalHit(entry)); 944 cache_entry.Dirty := true; 945 entry.DataBlk := cache_entry.DataBlk; 946 entry.Dirty := true; 947 DPRINTF(RubySlicc, "%s\n", cache_entry.DataBlk); 948 } 949 950 action(s1_storeDone, "s1", desc="Cluster 1 store done") { 951 Entry entry := getL1CacheEntry(address, 1); 952 assert(is_valid(entry)); 953 assert(is_valid(cache_entry)); 954 sequencer1.writeCallback(address, 955 cache_entry.DataBlk, 956 true, 957 testAndClearLocalHit(entry)); 958 cache_entry.Dirty := true; 959 entry.Dirty := true; 960 entry.DataBlk := cache_entry.DataBlk; 961 DPRINTF(RubySlicc, "%s\n", cache_entry.DataBlk); 962 } 963 964 action(xs0_storeDone, "xs0", desc="Cluster 0 store done") { 965 peek(responseToCore_in, ResponseMsg) { 966 Entry entry := getL1CacheEntry(address, 0); 967 assert(is_valid(entry)); 968 assert(is_valid(cache_entry)); 969 assert((machineIDToMachineType(in_msg.Sender) == MachineType:Directory) || 970 (machineIDToMachineType(in_msg.Sender) == MachineType:L3Cache)); 971 sequencer.writeCallback(address, 972 cache_entry.DataBlk, 973 false, 974 machineIDToMachineType(in_msg.Sender), 975 in_msg.InitialRequestTime, 976 in_msg.ForwardRequestTime, 977 in_msg.ProbeRequestStartTime); 978 cache_entry.Dirty := true; 979 entry.Dirty := true; 980 entry.DataBlk := cache_entry.DataBlk; 981 DPRINTF(RubySlicc, "%s\n", cache_entry.DataBlk); 982 } 983 } 984 985 action(xs1_storeDone, "xs1", desc="Cluster 1 store done") { 986 peek(responseToCore_in, ResponseMsg) { 987 Entry entry := getL1CacheEntry(address, 1); 988 assert(is_valid(entry)); 989 assert(is_valid(cache_entry)); 990 assert((machineIDToMachineType(in_msg.Sender) == MachineType:Directory) || 991 (machineIDToMachineType(in_msg.Sender) == MachineType:L3Cache)); 992 sequencer1.writeCallback(address, 993 cache_entry.DataBlk, 994 false, 995 machineIDToMachineType(in_msg.Sender), 996 in_msg.InitialRequestTime, 997 in_msg.ForwardRequestTime, 998 in_msg.ProbeRequestStartTime); 999 cache_entry.Dirty := true; 1000 entry.Dirty := true; 1001 entry.DataBlk := cache_entry.DataBlk; 1002 DPRINTF(RubySlicc, "%s\n", cache_entry.DataBlk); 1003 } 1004 } 1005 1006 action(forward_eviction_to_cpu0, "fec0", desc="sends eviction information to processor0") { 1007 if (send_evictions) { 1008 DPRINTF(RubySlicc, "Sending invalidation for %s to the CPU\n", address); 1009 sequencer.evictionCallback(address); 1010 } 1011 } 1012 1013 action(forward_eviction_to_cpu1, "fec1", desc="sends eviction information to processor1") { 1014 if (send_evictions) { 1015 DPRINTF(RubySlicc, "Sending invalidation for %s to the CPU\n", address); 1016 sequencer1.evictionCallback(address); 1017 } 1018 } 1019 1020 action(ci_copyL2ToL1, "ci", desc="copy L2 data to L1") { 1021 Entry entry := getICacheEntry(address); 1022 assert(is_valid(entry)); 1023 assert(is_valid(cache_entry)); 1024 entry.Dirty := cache_entry.Dirty; 1025 entry.DataBlk := cache_entry.DataBlk; 1026 entry.FromL2 := true; 1027 } 1028 1029 action(c0_copyL2ToL1, "c0", desc="copy L2 data to L1") { 1030 Entry entry := getL1CacheEntry(address, 0); 1031 assert(is_valid(entry)); 1032 assert(is_valid(cache_entry)); 1033 entry.Dirty := cache_entry.Dirty; 1034 entry.DataBlk := cache_entry.DataBlk; 1035 entry.FromL2 := true; 1036 } 1037 1038 action(c1_copyL2ToL1, "c1", desc="copy L2 data to L1") { 1039 Entry entry := getL1CacheEntry(address, 1); 1040 assert(is_valid(entry)); 1041 assert(is_valid(cache_entry)); 1042 entry.Dirty := cache_entry.Dirty; 1043 entry.DataBlk := cache_entry.DataBlk; 1044 entry.FromL2 := true; 1045 } 1046 1047 action(fi_L2ToL1, "fi", desc="L2 to L1 inst fill") { 1048 enqueue(triggerQueue_out, TriggerMsg, l2_hit_latency) { 1049 out_msg.addr := address; 1050 out_msg.Type := TriggerType:L2_to_L1; 1051 out_msg.Dest := CacheId:L1I; 1052 } 1053 } 1054 1055 action(f0_L2ToL1, "f0", desc="L2 to L1 data fill") { 1056 enqueue(triggerQueue_out, TriggerMsg, l2_hit_latency) { 1057 out_msg.addr := address; 1058 out_msg.Type := TriggerType:L2_to_L1; 1059 out_msg.Dest := CacheId:L1D0; 1060 } 1061 } 1062 1063 action(f1_L2ToL1, "f1", desc="L2 to L1 data fill") { 1064 enqueue(triggerQueue_out, TriggerMsg, l2_hit_latency) { 1065 out_msg.addr := address; 1066 out_msg.Type := TriggerType:L2_to_L1; 1067 out_msg.Dest := CacheId:L1D1; 1068 } 1069 } 1070 1071 action(wi_writeIcache, "wi", desc="write data to icache (and l2)") { 1072 peek(responseToCore_in, ResponseMsg) { 1073 Entry entry := getICacheEntry(address); 1074 assert(is_valid(entry)); 1075 assert(is_valid(cache_entry)); 1076 entry.DataBlk := in_msg.DataBlk; 1077 entry.Dirty := in_msg.Dirty; 1078 cache_entry.DataBlk := in_msg.DataBlk; 1079 cache_entry.Dirty := in_msg.Dirty; 1080 } 1081 } 1082 1083 action(w0_writeDcache, "w0", desc="write data to dcache 0 (and l2)") { 1084 peek(responseToCore_in, ResponseMsg) { 1085 Entry entry := getL1CacheEntry(address, 0); 1086 assert(is_valid(entry)); 1087 assert(is_valid(cache_entry)); 1088 DPRINTF(ProtocolTrace, "CP writeD0: address %s, data: %s\n", address, in_msg.DataBlk); 1089 entry.DataBlk := in_msg.DataBlk; 1090 entry.Dirty := in_msg.Dirty; 1091 cache_entry.DataBlk := in_msg.DataBlk; 1092 cache_entry.Dirty := in_msg.Dirty; 1093 } 1094 } 1095 1096 action(w1_writeDcache, "w1", desc="write data to dcache 1 (and l2)") { 1097 peek(responseToCore_in, ResponseMsg) { 1098 Entry entry := getL1CacheEntry(address, 1); 1099 assert(is_valid(entry)); 1100 assert(is_valid(cache_entry)); 1101 entry.DataBlk := in_msg.DataBlk; 1102 entry.Dirty := in_msg.Dirty; 1103 cache_entry.DataBlk := in_msg.DataBlk; 1104 cache_entry.Dirty := in_msg.Dirty; 1105 } 1106 } 1107 1108 action(ss_sendStaleNotification, "ss", desc="stale data; nothing to writeback") { 1109 peek(responseToCore_in, ResponseMsg) { 1110 enqueue(responseNetwork_out, ResponseMsg, issue_latency) { 1111 out_msg.addr := address; 1112 out_msg.Type := CoherenceResponseType:StaleNotif; 1113 out_msg.Sender := machineID; 1114 out_msg.Destination.add(mapAddressToMachine(address, MachineType:Directory)); 1115 out_msg.MessageSize := MessageSizeType:Response_Control; 1116 DPRINTF(RubySlicc, "%s\n", out_msg); 1117 } 1118 } 1119 } 1120 1121 action(wb_data, "wb", desc="write back data") { 1122 peek(responseToCore_in, ResponseMsg) { 1123 enqueue(responseNetwork_out, ResponseMsg, issue_latency) { 1124 out_msg.addr := address; 1125 out_msg.Type := CoherenceResponseType:CPUData; 1126 out_msg.Sender := machineID; 1127 out_msg.Destination.add(mapAddressToMachine(address, MachineType:Directory)); 1128 out_msg.DataBlk := tbe.DataBlk; 1129 out_msg.Dirty := tbe.Dirty; 1130 if (tbe.Shared) { 1131 out_msg.NbReqShared := true; 1132 } else { 1133 out_msg.NbReqShared := false; 1134 } 1135 out_msg.State := CoherenceState:Shared; // faux info 1136 out_msg.MessageSize := MessageSizeType:Writeback_Data; 1137 DPRINTF(RubySlicc, "%s\n", out_msg); 1138 } 1139 } 1140 } 1141 1142 action(pi_sendProbeResponseInv, "pi", desc="send probe ack inv, no data") { 1143 enqueue(responseNetwork_out, ResponseMsg, issue_latency) { 1144 out_msg.addr := address; 1145 out_msg.Type := CoherenceResponseType:CPUPrbResp; // L3 and CPUs respond in same way to probes 1146 out_msg.Sender := machineID; 1147 // will this always be ok? probably not for multisocket 1148 out_msg.Destination.add(mapAddressToMachine(address, MachineType:Directory)); 1149 out_msg.Dirty := false; 1150 out_msg.Hit := false; 1151 out_msg.Ntsl := true; 1152 out_msg.State := CoherenceState:NA; 1153 out_msg.MessageSize := MessageSizeType:Response_Control; 1154 } 1155 } 1156 1157 action(pim_sendProbeResponseInvMs, "pim", desc="send probe ack inv, no data") { 1158 enqueue(responseNetwork_out, ResponseMsg, issue_latency) { 1159 out_msg.addr := address; 1160 out_msg.Type := CoherenceResponseType:CPUPrbResp; // L3 and CPUs respond in same way to probes 1161 out_msg.Sender := machineID; 1162 // will this always be ok? probably not for multisocket 1163 out_msg.Destination.add(mapAddressToMachine(address, MachineType:Directory)); 1164 out_msg.Dirty := false; 1165 out_msg.Ntsl := true; 1166 out_msg.Hit := false; 1167 out_msg.State := CoherenceState:NA; 1168 out_msg.MessageSize := MessageSizeType:Response_Control; 1169 } 1170 } 1171 1172 action(ph_sendProbeResponseHit, "ph", desc="send probe ack PrbShrData, no data") { 1173 enqueue(responseNetwork_out, ResponseMsg, issue_latency) { 1174 out_msg.addr := address; 1175 out_msg.Type := CoherenceResponseType:CPUPrbResp; // L3 and CPUs respond in same way to probes 1176 out_msg.Sender := machineID; 1177 // will this always be ok? probably not for multisocket 1178 out_msg.Destination.add(mapAddressToMachine(address, MachineType:Directory)); 1179 assert(addressInCore(address) || is_valid(tbe)); 1180 out_msg.Dirty := false; // only true if sending back data i think 1181 out_msg.Hit := true; 1182 out_msg.Ntsl := false; 1183 out_msg.State := CoherenceState:NA; 1184 out_msg.MessageSize := MessageSizeType:Response_Control; 1185 } 1186 } 1187 1188 action(pb_sendProbeResponseBackprobe, "pb", desc="send probe ack PrbShrData, no data, check for L1 residence") { 1189 enqueue(responseNetwork_out, ResponseMsg, issue_latency) { 1190 out_msg.addr := address; 1191 out_msg.Type := CoherenceResponseType:CPUPrbResp; // L3 and CPUs respond in same way to probes 1192 out_msg.Sender := machineID; 1193 // will this always be ok? probably not for multisocket 1194 out_msg.Destination.add(mapAddressToMachine(address, MachineType:Directory)); 1195 if (addressInCore(address)) { 1196 out_msg.Hit := true; 1197 } else { 1198 out_msg.Hit := false; 1199 } 1200 out_msg.Dirty := false; // not sending back data, so def. not dirty 1201 out_msg.Ntsl := false; 1202 out_msg.State := CoherenceState:NA; 1203 out_msg.MessageSize := MessageSizeType:Response_Control; 1204 } 1205 } 1206 1207 action(pd_sendProbeResponseData, "pd", desc="send probe ack, with data") { 1208 enqueue(responseNetwork_out, ResponseMsg, issue_latency) { 1209 assert(is_valid(cache_entry)); 1210 out_msg.addr := address; 1211 out_msg.Type := CoherenceResponseType:CPUPrbResp; 1212 out_msg.Sender := machineID; 1213 // will this always be ok? probably not for multisocket 1214 out_msg.Destination.add(mapAddressToMachine(address, MachineType:Directory)); 1215 out_msg.DataBlk := cache_entry.DataBlk; 1216 assert(cache_entry.Dirty); 1217 out_msg.Dirty := true; 1218 out_msg.Hit := true; 1219 out_msg.State := CoherenceState:NA; 1220 out_msg.MessageSize := MessageSizeType:Response_Data; 1221 } 1222 } 1223 1224 action(pdm_sendProbeResponseDataMs, "pdm", desc="send probe ack, with data") { 1225 enqueue(responseNetwork_out, ResponseMsg, issue_latency) { 1226 assert(is_valid(cache_entry)); 1227 out_msg.addr := address; 1228 out_msg.Type := CoherenceResponseType:CPUPrbResp; 1229 out_msg.Sender := machineID; 1230 // will this always be ok? probably not for multisocket 1231 out_msg.Destination.add(mapAddressToMachine(address, MachineType:Directory)); 1232 out_msg.DataBlk := cache_entry.DataBlk; 1233 assert(cache_entry.Dirty); 1234 out_msg.Dirty := true; 1235 out_msg.Hit := true; 1236 out_msg.State := CoherenceState:NA; 1237 out_msg.MessageSize := MessageSizeType:Response_Data; 1238 } 1239 } 1240 1241 action(pdt_sendProbeResponseDataFromTBE, "pdt", desc="send probe ack with data") { 1242 enqueue(responseNetwork_out, ResponseMsg, issue_latency) { 1243 assert(is_valid(tbe)); 1244 out_msg.addr := address; 1245 out_msg.Type := CoherenceResponseType:CPUPrbResp; 1246 out_msg.Sender := machineID; 1247 out_msg.Destination.add(mapAddressToMachine(address, MachineType:Directory)); 1248 out_msg.DataBlk := tbe.DataBlk; 1249 assert(tbe.Dirty); 1250 out_msg.Dirty := true; 1251 out_msg.Hit := true; 1252 out_msg.State := CoherenceState:NA; 1253 out_msg.MessageSize := MessageSizeType:Response_Data; 1254 } 1255 } 1256 1257 action(s_setSharedFlip, "s", desc="hit by shared probe, status may be different") { 1258 assert(is_valid(tbe)); 1259 tbe.Shared := true; 1260 } 1261 1262 action(uu_sendUnblock, "uu", desc="state changed, unblock") { 1263 enqueue(unblockNetwork_out, UnblockMsg, issue_latency) { 1264 out_msg.addr := address; 1265 out_msg.Destination.add(mapAddressToMachine(address, MachineType:Directory)); 1266 out_msg.MessageSize := MessageSizeType:Unblock_Control; 1267 DPRINTF(RubySlicc, "%s\n", out_msg); 1268 } 1269 } 1270 1271 action(l2m_profileMiss, "l2m", desc="l2m miss profile") { 1272 ++L2cache.demand_misses; 1273 } 1274 1275 action(l10m_profileMiss, "l10m", desc="l10m miss profile") { 1276 ++L1D0cache.demand_misses; 1277 } 1278 1279 action(l11m_profileMiss, "l11m", desc="l11m miss profile") { 1280 ++L1D1cache.demand_misses; 1281 } 1282 1283 action(l1im_profileMiss, "l1lm", desc="l1im miss profile") { 1284 ++L1Icache.demand_misses; 1285 } 1286 1287 action(yy_recycleProbeQueue, "yy", desc="recycle probe queue") { 1288 probeNetwork_in.recycle(clockEdge(), cyclesToTicks(recycle_latency)); 1289 } 1290 1291 action(xx_recycleResponseQueue, "xx", desc="recycle response queue") { 1292 responseToCore_in.recycle(clockEdge(), cyclesToTicks(recycle_latency)); 1293 } 1294 1295 action(zz_recycleMandatoryQueue, "\z", desc="recycle mandatory queue") { 1296 mandatoryQueue_in.recycle(clockEdge(), cyclesToTicks(recycle_latency)); 1297 } 1298 1299 // END ACTIONS 1300 1301 // BEGIN TRANSITIONS 1302 1303 // transitions from base 1304 transition(I, C0_Load_L1miss, I_E0S) {L1D0TagArrayRead, L2TagArrayRead} { 1305 // track misses, if implemented 1306 // since in I state, L2 miss as well 1307 l2m_profileMiss; 1308 l10m_profileMiss; 1309 a0_allocateL1D; 1310 a2_allocateL2; 1311 i1_invCluster; 1312 ii_invIcache; 1313 n_issueRdBlk; 1314 p_popMandatoryQueue; 1315 } 1316 1317 transition(I, C1_Load_L1miss, I_E1S) {L1D1TagArrayRead, L2TagArrayRead} { 1318 // track misses, if implemented 1319 // since in I state, L2 miss as well 1320 l2m_profileMiss; 1321 l11m_profileMiss; 1322 a1_allocateL1D; 1323 a2_allocateL2; 1324 i0_invCluster; 1325 ii_invIcache; 1326 n_issueRdBlk; 1327 p_popMandatoryQueue; 1328 } 1329 1330 transition(I, Ifetch0_L1miss, S0) {L1ITagArrayRead,L2TagArrayRead} { 1331 // track misses, if implemented 1332 // L2 miss as well 1333 l2m_profileMiss; 1334 l1im_profileMiss; 1335 ai_allocateL1I; 1336 a2_allocateL2; 1337 ib_invBothClusters; 1338 nS_issueRdBlkS; 1339 p_popMandatoryQueue; 1340 } 1341 1342 transition(I, Ifetch1_L1miss, S1) {L1ITagArrayRead, L2TagArrayRead} { 1343 // track misses, if implemented 1344 // L2 miss as well 1345 l2m_profileMiss; 1346 l1im_profileMiss; 1347 ai_allocateL1I; 1348 a2_allocateL2; 1349 ib_invBothClusters; 1350 nS_issueRdBlkS; 1351 p_popMandatoryQueue; 1352 } 1353 1354 transition(I, C0_Store_L1miss, I_M0) {L1D0TagArrayRead, L2TagArrayRead} { 1355 l2m_profileMiss; 1356 l10m_profileMiss; 1357 a0_allocateL1D; 1358 a2_allocateL2; 1359 i1_invCluster; 1360 ii_invIcache; 1361 nM_issueRdBlkM; 1362 p_popMandatoryQueue; 1363 } 1364 1365 transition(I, C1_Store_L1miss, I_M1) {L1D0TagArrayRead, L2TagArrayRead} { 1366 l2m_profileMiss; 1367 l11m_profileMiss; 1368 a1_allocateL1D; 1369 a2_allocateL2; 1370 i0_invCluster; 1371 ii_invIcache; 1372 nM_issueRdBlkM; 1373 p_popMandatoryQueue; 1374 } 1375 1376 transition(S, C0_Load_L1miss, S_F0) {L1D0TagArrayRead, L2TagArrayRead, L2DataArrayRead} { 1377 l10m_profileMiss; 1378 a0_allocateL1D; 1379 f0_L2ToL1; 1380 mru_setMRU; 1381 p_popMandatoryQueue; 1382 } 1383 1384 transition(S, C1_Load_L1miss, S_F1) {L1D1TagArrayRead,L2TagArrayRead, L2DataArrayRead} { 1385 l11m_profileMiss; 1386 a1_allocateL1D; 1387 f1_L2ToL1; 1388 mru_setMRU; 1389 p_popMandatoryQueue; 1390 } 1391 1392 transition(S, Ifetch0_L1miss, Si_F0) {L1ITagArrayRead, L2TagArrayRead, L2DataArrayRead} { 1393 l1im_profileMiss; 1394 ai_allocateL1I; 1395 fi_L2ToL1; 1396 mru_setMRU; 1397 p_popMandatoryQueue; 1398 } 1399 1400 transition(S, Ifetch1_L1miss, Si_F1) {L1ITagArrayRead,L2TagArrayRead, L2DataArrayRead} { 1401 l1im_profileMiss; 1402 ai_allocateL1I; 1403 fi_L2ToL1; 1404 mru_setMRU; 1405 p_popMandatoryQueue; 1406 } 1407 1408 transition({S}, {C0_Store_L1hit, C0_Store_L1miss}, S_M0) {L1D0TagArrayRead, L2TagArrayRead} { 1409 l2m_profileMiss; 1410 l10m_profileMiss; 1411 a0_allocateL1D; 1412 mruD0_setD0cacheMRU; 1413 i1_invCluster; 1414 ii_invIcache; 1415 nM_issueRdBlkM; 1416 p_popMandatoryQueue; 1417 } 1418 1419 transition({S}, {C1_Store_L1hit, C1_Store_L1miss}, S_M1) {L1D1TagArrayRead, L2TagArrayRead} { 1420 l2m_profileMiss; 1421 l11m_profileMiss; 1422 a1_allocateL1D; 1423 mruD1_setD1cacheMRU; 1424 i0_invCluster; 1425 ii_invIcache; 1426 nM_issueRdBlkM; 1427 p_popMandatoryQueue; 1428 } 1429 1430 transition(Es, C0_Load_L1miss, Es_F0) {L1D0TagArrayRead, L2TagArrayRead, L2DataArrayRead} { // can this be folded with S_F? 1431 a0_allocateL1D; 1432 l10m_profileMiss; 1433 f0_L2ToL1; 1434 mru_setMRU; 1435 p_popMandatoryQueue; 1436 } 1437 1438 transition(Es, C1_Load_L1miss, Es_F1) {L1D1TagArrayRead, L2TagArrayRead, L2DataArrayRead} { // can this be folded with S_F? 1439 l11m_profileMiss; 1440 a1_allocateL1D; 1441 f1_L2ToL1; 1442 mru_setMRU; 1443 p_popMandatoryQueue; 1444 } 1445 1446 transition(Es, Ifetch0_L1miss, S0) {L1ITagArrayRead, L1ITagArrayWrite, L2TagArrayRead, L2TagArrayWrite} { 1447 l1im_profileMiss; 1448 i2_invL2; 1449 ai_allocateL1I; 1450 a2_allocateL2; 1451 ib_invBothClusters; 1452 nS_issueRdBlkS; 1453 p_popMandatoryQueue; 1454 } 1455 1456 transition(Es, Ifetch1_L1miss, S1) {L1ITagArrayRead, L2TagArrayRead} { 1457 l1im_profileMiss; 1458 i2_invL2; 1459 ai_allocateL1I; 1460 a2_allocateL2; 1461 ib_invBothClusters; 1462 nS_issueRdBlkS; 1463 p_popMandatoryQueue; 1464 } 1465 1466 // THES SHOULD NOT BE INSTANTANEOUS BUT OH WELL FOR NOW 1467 transition(Es, {C0_Store_L1hit, C0_Store_L1miss}, M0) {L1D0TagArrayRead, L1D0TagArrayWrite, L1D0DataArrayWrite, L2TagArrayRead, L2TagArrayWrite, L2DataArrayWrite} { 1468 a0_allocateL1D; 1469 i1_invCluster; 1470 s0_storeDone; // instantaneous L1/L2 dirty - no writethrough delay 1471 mruD0_setD0cacheMRU; 1472 mru_setMRU; 1473 p_popMandatoryQueue; 1474 } 1475 1476 transition(Es, {C1_Store_L1hit, C1_Store_L1miss}, M1) {L1D1TagArrayRead, L1D1TagArrayWrite, L1D1DataArrayWrite, L2TagArrayRead, L2TagArrayWrite, L2DataArrayWrite} { 1477 a1_allocateL1D; 1478 i0_invCluster; 1479 s1_storeDone; 1480 mruD1_setD1cacheMRU; 1481 mru_setMRU; 1482 p_popMandatoryQueue; 1483 } 1484 1485 transition(E0, C0_Load_L1miss, E0_F) {L1D0TagArrayRead,L2TagArrayRead, L2DataArrayRead} { 1486 l10m_profileMiss; 1487 a0_allocateL1D; 1488 f0_L2ToL1; 1489 mru_setMRU; 1490 p_popMandatoryQueue; 1491 } 1492 1493 transition(E0, C1_Load_L1miss, E0_Es) {L1D1TagArrayRead, L2TagArrayRead, L2DataArrayRead} { 1494 l11m_profileMiss; 1495 a1_allocateL1D; 1496 f1_L2ToL1; 1497 mru_setMRU; 1498 p_popMandatoryQueue; 1499 } 1500 1501 transition(E0, Ifetch0_L1miss, S0) {L2TagArrayRead, L1ITagArrayRead} { 1502 l2m_profileMiss; // permissions miss, still issue RdBlkS 1503 l1im_profileMiss; 1504 i2_invL2; 1505 ai_allocateL1I; 1506 a2_allocateL2; 1507 i0_invCluster; 1508 nS_issueRdBlkS; 1509 p_popMandatoryQueue; 1510 } 1511 1512 transition(E0, Ifetch1_L1miss, S1) {L2TagArrayRead, L1ITagArrayRead} { 1513 l2m_profileMiss; // permissions miss, still issue RdBlkS 1514 l1im_profileMiss; 1515 i2_invL2; 1516 ai_allocateL1I; 1517 a2_allocateL2; 1518 i0_invCluster; 1519 nS_issueRdBlkS; 1520 p_popMandatoryQueue; 1521 } 1522 1523 transition(E0, {C0_Store_L1hit, C0_Store_L1miss}, M0) {L1D0TagArrayRead, L1D0DataArrayWrite, L1D0TagArrayWrite, L2TagArrayRead, L2DataArrayWrite, L2TagArrayWrite} { 1524 a0_allocateL1D; 1525 s0_storeDone; 1526 mruD0_setD0cacheMRU; 1527 mru_setMRU; 1528 p_popMandatoryQueue; 1529 } 1530 1531 transition(E0, C1_Store_L1miss, M1) {L1D1TagArrayRead, L1D1TagArrayWrite, L1D1TagArrayWrite, L2TagArrayRead, L2TagArrayWrite, L2DataArrayWrite} { 1532 l11m_profileMiss; 1533 a1_allocateL1D; 1534 i0_invCluster; 1535 s1_storeDone; 1536 mru_setMRU; 1537 p_popMandatoryQueue; 1538 } 1539 1540 transition(E1, C1_Load_L1miss, E1_F) {L1D1TagArrayRead, L2TagArrayRead, L2DataArrayRead} { 1541 l11m_profileMiss; 1542 a1_allocateL1D; 1543 f1_L2ToL1; 1544 mru_setMRU; 1545 p_popMandatoryQueue; 1546 } 1547 1548 transition(E1, C0_Load_L1miss, E1_Es) {L1D0TagArrayRead, L2TagArrayRead, L2DataArrayRead} { 1549 l11m_profileMiss; 1550 a0_allocateL1D; 1551 f0_L2ToL1; 1552 mru_setMRU; 1553 p_popMandatoryQueue; 1554 } 1555 1556 transition(E1, Ifetch1_L1miss, S1) {L2TagArrayRead, L1ITagArrayRead} { 1557 l2m_profileMiss; // permissions miss, still issue RdBlkS 1558 l1im_profileMiss; 1559 i2_invL2; 1560 ai_allocateL1I; 1561 a2_allocateL2; 1562 i1_invCluster; 1563 nS_issueRdBlkS; 1564 p_popMandatoryQueue; 1565 } 1566 1567 transition(E1, Ifetch0_L1miss, S0) {L2TagArrayRead, L1ITagArrayRead} { 1568 l2m_profileMiss; // permissions miss, still issue RdBlkS 1569 l1im_profileMiss; 1570 i2_invL2; 1571 ai_allocateL1I; 1572 a2_allocateL2; 1573 i1_invCluster; 1574 nS_issueRdBlkS; 1575 p_popMandatoryQueue; 1576 } 1577 1578 transition(E1, {C1_Store_L1hit, C1_Store_L1miss}, M1) {L1D1TagArrayRead, L2TagArrayRead, L2DataArrayWrite, L1D1TagArrayWrite, L2TagArrayWrite} { 1579 a1_allocateL1D; 1580 s1_storeDone; 1581 mruD1_setD1cacheMRU; 1582 mru_setMRU; 1583 p_popMandatoryQueue; 1584 } 1585 1586 transition(E1, C0_Store_L1miss, M0) {L1D0TagArrayRead, L2TagArrayRead, L2TagArrayWrite, L1D0TagArrayWrite, L1D0DataArrayWrite, L2DataArrayWrite} { 1587 l10m_profileMiss; 1588 a0_allocateL1D; 1589 i1_invCluster; 1590 s0_storeDone; 1591 mru_setMRU; 1592 p_popMandatoryQueue; 1593 } 1594 1595 transition({O}, {C0_Store_L1hit, C0_Store_L1miss}, O_M0) {L1D0TagArrayRead,L2TagArrayRead} { 1596 l2m_profileMiss; // permissions miss, still issue CtoD 1597 l10m_profileMiss; 1598 a0_allocateL1D; 1599 mruD0_setD0cacheMRU; 1600 i1_invCluster; 1601 ii_invIcache; 1602 nM_issueRdBlkM; 1603 p_popMandatoryQueue; 1604 } 1605 1606 transition({O}, {C1_Store_L1hit, C1_Store_L1miss}, O_M1) {L1D1TagArrayRead, L2TagArrayRead} { 1607 l2m_profileMiss; // permissions miss, still issue RdBlkS 1608 l11m_profileMiss; 1609 a1_allocateL1D; 1610 mruD1_setD1cacheMRU; 1611 i0_invCluster; 1612 ii_invIcache; 1613 nM_issueRdBlkM; 1614 p_popMandatoryQueue; 1615 } 1616 1617 transition(O, C0_Load_L1miss, O_F0) {L2TagArrayRead, L2DataArrayRead, L1D0TagArrayRead} { 1618 l10m_profileMiss; 1619 a0_allocateL1D; 1620 f0_L2ToL1; 1621 mru_setMRU; 1622 p_popMandatoryQueue; 1623 } 1624 1625 transition(O, C1_Load_L1miss, O_F1) {L2TagArrayRead, L2DataArrayRead, L1D1TagArrayRead} { 1626 l11m_profileMiss; 1627 a1_allocateL1D; 1628 f1_L2ToL1; 1629 mru_setMRU; 1630 p_popMandatoryQueue; 1631 } 1632 1633 transition(Ms, C0_Load_L1miss, Ms_F0) {L2TagArrayRead, L2DataArrayRead, L1D0TagArrayRead} { 1634 l10m_profileMiss; 1635 a0_allocateL1D; 1636 f0_L2ToL1; 1637 mru_setMRU; 1638 p_popMandatoryQueue; 1639 } 1640 1641 transition(Ms, C1_Load_L1miss, Ms_F1) {L2TagArrayRead, L2DataArrayRead, L1D1TagArrayRead} { 1642 l11m_profileMiss; 1643 a1_allocateL1D; 1644 f1_L2ToL1; 1645 mru_setMRU; 1646 p_popMandatoryQueue; 1647 } 1648 1649 transition({Ms, M0, M1, O}, Ifetch0_L1miss, MO_S0) {L1ITagArrayRead, L2DataArrayRead, L2TagArrayRead} { 1650 l2m_profileMiss; // permissions miss 1651 l1im_profileMiss; 1652 ai_allocateL1I; 1653 t_allocateTBE; 1654 ib_invBothClusters; 1655 vd_victim; 1656// i2_invL2; 1657 p_popMandatoryQueue; 1658 } 1659 1660 transition({Ms, M0, M1, O}, Ifetch1_L1miss, MO_S1) {L1ITagArrayRead, L2TagArrayRead, L2DataArrayRead } { 1661 l2m_profileMiss; // permissions miss 1662 l1im_profileMiss; 1663 ai_allocateL1I; 1664 t_allocateTBE; 1665 ib_invBothClusters; 1666 vd_victim; 1667// i2_invL2; 1668 p_popMandatoryQueue; 1669 } 1670 1671 transition(Ms, {C0_Store_L1hit, C0_Store_L1miss}, M0) {L1D0TagArrayRead, L1D0TagArrayWrite, L1D0DataArrayWrite, L2TagArrayRead, L2DataArrayWrite, L2TagArrayWrite} { 1672 a0_allocateL1D; 1673 i1_invCluster; 1674 s0_storeDone; 1675 mruD0_setD0cacheMRU; 1676 mru_setMRU; 1677 p_popMandatoryQueue; 1678 } 1679 1680 transition(Ms, {C1_Store_L1hit, C1_Store_L1miss}, M1) {L1D1TagArrayRead, L1D1TagArrayWrite, L1D1DataArrayWrite, L2TagArrayRead, L2DataArrayWrite, L2TagArrayWrite} { 1681 a1_allocateL1D; 1682 i0_invCluster; 1683 s1_storeDone; 1684 mruD1_setD1cacheMRU; 1685 mru_setMRU; 1686 p_popMandatoryQueue; 1687 } 1688 1689 transition(M0, C0_Load_L1miss, M0_F) {L1D0TagArrayRead, L2TagArrayRead, L2DataArrayRead} { 1690 l10m_profileMiss; 1691 a0_allocateL1D; 1692 f0_L2ToL1; 1693 mru_setMRU; 1694 p_popMandatoryQueue; 1695 } 1696 1697 transition(M0, C1_Load_L1miss, M0_Ms) {L2TagArrayRead, L2DataArrayRead,L1D0TagArrayRead} { 1698 l11m_profileMiss; 1699 a1_allocateL1D; 1700 f1_L2ToL1; 1701 mru_setMRU; 1702 p_popMandatoryQueue; 1703 } 1704 1705 transition(M0, {C0_Store_L1hit, C0_Store_L1miss}) {L1D0TagArrayRead,L1D0DataArrayWrite, L2DataArrayWrite, L2TagArrayRead} { 1706 a0_allocateL1D; 1707 s0_storeDone; 1708 mruD0_setD0cacheMRU; 1709 mru_setMRU; 1710 p_popMandatoryQueue; 1711 } 1712 1713 transition(M0, {C1_Store_L1hit, C1_Store_L1miss}, M1) {L1D1TagArrayRead, L1D1TagArrayWrite, L1D0DataArrayWrite, L2DataArrayWrite, L2TagArrayRead, L2TagArrayWrite} { 1714 a1_allocateL1D; 1715 i0_invCluster; 1716 s1_storeDone; 1717 mruD1_setD1cacheMRU; 1718 mru_setMRU; 1719 p_popMandatoryQueue; 1720 } 1721 1722 transition(M1, C0_Load_L1miss, M1_Ms) {L2TagArrayRead, L2DataArrayRead, L1D0TagArrayRead} { 1723 l10m_profileMiss; 1724 a0_allocateL1D; 1725 f0_L2ToL1; 1726 mru_setMRU; 1727 p_popMandatoryQueue; 1728 } 1729 1730 transition(M1, C1_Load_L1miss, M1_F) {L1D1TagArrayRead,L2TagArrayRead, L2DataArrayRead} { 1731 a1_allocateL1D; 1732 f1_L2ToL1; 1733 mru_setMRU; 1734 p_popMandatoryQueue; 1735 } 1736 1737 transition(M1, {C0_Store_L1hit, C0_Store_L1miss}, M0) {L1D0TagArrayRead, L1D0TagArrayWrite, L1D0DataArrayWrite, L2TagArrayRead, L2DataArrayWrite, L2TagArrayWrite} { 1738 a0_allocateL1D; 1739 i1_invCluster; 1740 s0_storeDone; 1741 mruD0_setD0cacheMRU; 1742 mru_setMRU; 1743 p_popMandatoryQueue; 1744 } 1745 1746 transition(M1, {C1_Store_L1hit, C1_Store_L1miss}) {L1D1TagArrayRead, L2TagArrayRead, L2DataArrayWrite} { 1747 a1_allocateL1D; 1748 s1_storeDone; 1749 mruD1_setD1cacheMRU; 1750 mru_setMRU; 1751 p_popMandatoryQueue; 1752 } 1753 1754 // end transitions from base 1755 1756 // Begin simple hit transitions 1757 transition({S, Es, E0, O, Ms, M0, O_F1, S_F1, Si_F0, Si_F1, Es_F1, E0_Es, 1758 Ms_F1, M0_Ms}, C0_Load_L1hit) {L1D0TagArrayRead, L1D0DataArrayRead} { 1759 // track hits, if implemented 1760 l0_loadDone; 1761 mruD0_setD0cacheMRU; 1762 p_popMandatoryQueue; 1763 } 1764 1765 transition({S, Es, E1, O, Ms, M1, O_F0, S_F0, Si_F0, Si_F1, Es_F0, E1_Es, 1766 Ms_F0, M1_Ms}, C1_Load_L1hit) {L1D1TagArrayRead, L1D1DataArrayRead} { 1767 // track hits, if implemented 1768 l1_loadDone; 1769 mruD1_setD1cacheMRU; 1770 p_popMandatoryQueue; 1771 } 1772 1773 transition({S, S_C, S_F0, S_F1, S_F}, Ifetch0_L1hit) {L1ITagArrayRead, L1IDataArrayRead} { 1774 // track hits, if implemented 1775 il0_loadDone; 1776 mruI_setIcacheMRU; 1777 p_popMandatoryQueue; 1778 } 1779 1780 transition({S, S_C, S_F0, S_F1, S_F}, Ifetch1_L1hit) {L1ITagArrayRead, L1IDataArrayWrite} { 1781 // track hits, if implemented 1782 il1_loadDone; 1783 mruI_setIcacheMRU; 1784 p_popMandatoryQueue; 1785 } 1786 1787 // end simple hit transitions 1788 1789 // Transitions from transient states 1790 1791 // recycles 1792 transition({I_M0, I_M0M1, I_M1M0, I_M0Ms, I_M1Ms, I_E0S, I_ES, IF_E0S, IF_ES, 1793 IF0_ES, IF1_ES, S_F0, S_F, O_F0, O_F, S_M0, O_M0, Es_F0, Es_F, E0_F, 1794 E1_Es, Ms_F0, Ms_F, M0_F, M1_Ms}, C0_Load_L1hit) {} { 1795 zz_recycleMandatoryQueue; 1796 } 1797 1798 transition({IF_E1S, F_S0, F_S1, ES_I, MO_I, MO_S0, MO_S1, Si_F0, Si_F1, S_M1, 1799 O_M1, S0, S1, I_C, S0_C, S1_C, S_C}, C0_Load_L1miss) {} { 1800 zz_recycleMandatoryQueue; 1801 } 1802 1803 transition({I_M1, I_M0M1, I_M1M0, I_M0Ms, I_M1Ms, I_E1S, I_ES, IF_E1S, IF_ES, 1804 IF0_ES, IF1_ES, S_F1, S_F, O_F1, O_F, S_M1, O_M1, Es_F1, Es_F, E1_F, 1805 E0_Es, Ms_F1, Ms_F, M0_Ms, M1_F}, C1_Load_L1hit) {} { 1806 zz_recycleMandatoryQueue; 1807 } 1808 1809 transition({IF_E0S, F_S0, F_S1, ES_I, MO_I, MO_S0, MO_S1, Si_F0, Si_F1, S_M0, 1810 O_M0, S0, S1, I_C, S0_C, S1_C, S_C}, C1_Load_L1miss) {} { 1811 zz_recycleMandatoryQueue; 1812 } 1813 1814 transition({F_S0, F_S1, MO_S0, MO_S1, Si_F0, Si_F1, S0, S1, S0_C, S1_C}, {Ifetch0_L1hit, Ifetch1_L1hit}) {} { 1815 zz_recycleMandatoryQueue; 1816 } 1817 1818 transition({I_M0, I_M1, I_M0M1, I_M1M0, I_M0Ms, I_M1Ms, I_E0S, I_E1S, I_ES, 1819 IF_E0S, IF_E1S, IF_ES, IF0_ES, IF1_ES, ES_I, MO_I, S_F0, S_F1, S_F, 1820 O_F0, O_F1, O_F, S_M0, S_M1, O_M0, O_M1, Es_F0, Es_F1, Es_F, E0_F, 1821 E1_F, E0_Es, E1_Es, Ms_F0, Ms_F1, Ms_F, M0_F, M0_Ms, M1_F, M1_Ms, I_C, 1822 S_C}, {Ifetch0_L1miss, Ifetch1_L1miss}) {} { 1823 zz_recycleMandatoryQueue; 1824 } 1825 1826 transition({I_E1S, IF_E1S, F_S0, F_S1, ES_I, MO_I, MO_S0, MO_S1, S_F1, O_F1, 1827 Si_F0, Si_F1, S_M1, O_M1, S0, S1, Es_F1, E1_F, E0_Es, Ms_F1, M0_Ms, 1828 M1_F, I_C, S0_C, S1_C, S_C}, {C0_Store_L1miss}) {} { 1829 zz_recycleMandatoryQueue; 1830 } 1831 1832 transition({I_E0S, IF_E0S, F_S0, F_S1, ES_I, MO_I, MO_S0, MO_S1 S_F0, O_F0, 1833 Si_F0, Si_F1, S_M0, O_M0, S0, S1, Es_F0, E0_F, E1_Es, Ms_F0, M0_F, 1834 M1_Ms, I_C, S0_C, S1_C, S_C}, {C1_Store_L1miss}) {} { 1835 zz_recycleMandatoryQueue; 1836 } 1837 1838 transition({I_M0, I_M0M1, I_M1M0, I_M0Ms, I_M1Ms, I_E0S, I_ES, IF_E0S, IF_ES, 1839 IF0_ES, IF1_ES, S_F0, S_F1, S_F, O_F0, O_F1, O_F, Si_F0, Si_F1, S_M0, O_M0, Es_F0, Es_F1, Es_F, E0_F, E0_Es, E1_Es, Ms_F0, Ms_F1, Ms_F, M0_F, M0_Ms, M1_Ms}, {C0_Store_L1hit}) {} { 1840 zz_recycleMandatoryQueue; 1841 } 1842 1843 transition({I_M1, I_M0M1, I_M1M0, I_M0Ms, I_M1Ms, I_E1S, I_ES, IF_E1S, IF_ES, 1844 IF0_ES, IF1_ES, S_F0, S_F1, S_F, O_F0, O_F1, O_F, Si_F0, Si_F1, S_M1, 1845 O_M1, Es_F0, Es_F1, Es_F, E1_F, E0_Es, E1_Es, Ms_F0, Ms_F1, Ms_F, 1846 M0_Ms, M1_F, M1_Ms}, {C1_Store_L1hit}) {} { 1847 zz_recycleMandatoryQueue; 1848 } 1849 1850 transition({I_M0, I_M0M1, I_M1M0, I_M0Ms, I_M1Ms, I_E0S, I_ES, IF_E0S, IF_ES, 1851 IF0_ES, IF1_ES, S_F0, S_F, O_F0, O_F, S_M0, O_M0, Es_F0, Es_F, E0_F, 1852 E1_Es, Ms_F0, Ms_F, M0_F, M1_Ms}, L1D0_Repl) {} { 1853 zz_recycleMandatoryQueue; 1854 } 1855 1856 transition({I_M1, I_M0M1, I_M1M0, I_M0Ms, I_M1Ms, I_E1S, I_ES, IF_E1S, IF_ES, 1857 IF0_ES, IF1_ES, S_F1, S_F, O_F1, O_F, S_M1, O_M1, Es_F1, Es_F, E1_F, 1858 E0_Es, Ms_F1, Ms_F, M0_Ms, M1_F}, L1D1_Repl) {} { 1859 zz_recycleMandatoryQueue; 1860 } 1861 1862 transition({F_S0, F_S1, MO_S0, MO_S1, Si_F0, Si_F1, S0, S1, S0_C, S1_C}, L1I_Repl) {} { 1863 zz_recycleMandatoryQueue; 1864 } 1865 1866 transition({S_C, S0_C, S1_C, S0, S1, Si_F0, Si_F1, I_M0, I_M1, I_M0M1, I_M1M0, I_M0Ms, I_M1Ms, I_E0S, I_E1S, I_ES, S_F0, S_F1, S_F, O_F0, O_F1, O_F, S_M0, O_M0, S_M1, O_M1, Es_F0, Es_F1, Es_F, E0_F, E1_F, E0_Es, E1_Es, Ms_F0, Ms_F1, Ms_F, M0_F, M0_Ms, M1_F, M1_Ms, MO_S0, MO_S1, IF_E0S, IF_E1S, IF_ES, IF0_ES, IF1_ES, F_S0, F_S1}, L2_Repl) {} { 1867 zz_recycleMandatoryQueue; 1868 } 1869 1870 transition({IF_E0S, IF_E1S, IF_ES, IF0_ES, IF1_ES, F_S0, F_S1}, {NB_AckS, 1871 PrbInvData, PrbInv, PrbShrData}) {} { 1872 yy_recycleProbeQueue; // these should be resolved soon, but I didn't want to add more states, though technically they could be solved now, and probes really could be solved but i don't think it's really necessary. 1873 } 1874 1875 transition({IF_E0S, IF_E1S, IF_ES, IF0_ES, IF1_ES}, NB_AckE) {} { 1876 xx_recycleResponseQueue; // these should be resolved soon, but I didn't want to add more states, though technically they could be solved now, and probes really could be solved but i don't think it's really necessary. 1877 } 1878 1879 transition({E0_Es, E1_F, Es_F1}, C0_Load_L1miss, Es_F) {L2DataArrayRead} { 1880 l10m_profileMiss; 1881 a0_allocateL1D; 1882 f0_L2ToL1; 1883 p_popMandatoryQueue; 1884 } 1885 1886 transition(S_F1, C0_Load_L1miss, S_F) {L2DataArrayRead} { 1887 l10m_profileMiss; 1888 a0_allocateL1D; 1889 f0_L2ToL1; 1890 p_popMandatoryQueue; 1891 } 1892 1893 transition(O_F1, C0_Load_L1miss, O_F) {L2DataArrayRead} { 1894 l10m_profileMiss; 1895 a0_allocateL1D; 1896 f0_L2ToL1; 1897 p_popMandatoryQueue; 1898 } 1899 1900 transition({Ms_F1, M0_Ms, M1_F}, C0_Load_L1miss, Ms_F) {L2DataArrayRead} { 1901 l10m_profileMiss; 1902 a0_allocateL1D; 1903 f0_L2ToL1; 1904 p_popMandatoryQueue; 1905 } 1906 1907 transition(I_M0, C1_Load_L1miss, I_M0Ms) {} { 1908 l2m_profileMiss; 1909 l11m_profileMiss; 1910 a1_allocateL1D; 1911 mru_setMRU; 1912 p_popMandatoryQueue; 1913 } 1914 1915 transition(I_M1, C0_Load_L1miss, I_M1Ms) {} { 1916 l2m_profileMiss; 1917 l10m_profileMiss; 1918 a0_allocateL1D; 1919 mru_setMRU; 1920 p_popMandatoryQueue; 1921 } 1922 1923 transition(I_M0, C1_Store_L1miss, I_M0M1) {} { 1924 l2m_profileMiss; 1925 l11m_profileMiss; 1926 a1_allocateL1D; 1927 mru_setMRU; 1928 p_popMandatoryQueue; 1929 } 1930 1931 transition(I_M1, C0_Store_L1miss, I_M1M0) {} { 1932 l2m_profileMiss; 1933 l10m_profileMiss; 1934 a0_allocateL1D; 1935 mru_setMRU; 1936 p_popMandatoryQueue; 1937 } 1938 1939 transition(I_E0S, C1_Load_L1miss, I_ES) {} { 1940 l2m_profileMiss; 1941 l11m_profileMiss; 1942 a1_allocateL1D; 1943 p_popMandatoryQueue; 1944 } 1945 1946 transition(I_E1S, C0_Load_L1miss, I_ES) {} { 1947 l2m_profileMiss; 1948 l10m_profileMiss; 1949 a0_allocateL1D; 1950 p_popMandatoryQueue; 1951 } 1952 1953 transition({E1_Es, E0_F, Es_F0}, C1_Load_L1miss, Es_F) {L2DataArrayRead} { 1954 l11m_profileMiss; 1955 a1_allocateL1D; 1956 f1_L2ToL1; 1957 p_popMandatoryQueue; 1958 } 1959 1960 transition(S_F0, C1_Load_L1miss, S_F) {L2DataArrayRead} { 1961 l11m_profileMiss; 1962 a1_allocateL1D; 1963 f1_L2ToL1; 1964 p_popMandatoryQueue; 1965 } 1966 1967 transition(O_F0, C1_Load_L1miss, O_F) {L2DataArrayRead} { 1968 l11m_profileMiss; 1969 a1_allocateL1D; 1970 f1_L2ToL1; 1971 p_popMandatoryQueue; 1972 } 1973 1974 transition({Ms_F0, M1_Ms, M0_F}, C1_Load_L1miss, Ms_F) { L2DataArrayRead} { 1975 l11m_profileMiss; 1976 a1_allocateL1D; 1977 f1_L2ToL1; 1978 p_popMandatoryQueue; 1979 } 1980 1981 transition({S, Es, E0, O, Ms, M0, O_F1, S_F1, Si_F0, Si_F1, Es_F1, E0_Es, Ms_F1, M0_Ms}, L1D0_Repl) {L1D0TagArrayRead} { 1982 i0_invCluster; 1983 } 1984 1985 transition({S, Es, E1, O, Ms, M1, O_F0, S_F0, Si_F0, Si_F1, Es_F0, E1_Es, Ms_F0, M1_Ms}, L1D1_Repl) {L1D1TagArrayRead} { 1986 i1_invCluster; 1987 } 1988 1989 transition({S, S_C, S_F0, S_F1}, L1I_Repl) {L1ITagArrayRead} { 1990 ii_invIcache; 1991 } 1992 1993 transition({S, E0, E1, Es}, L2_Repl, ES_I) {L2TagArrayRead, L2DataArrayRead, L1D0TagArrayRead, L1D1TagArrayRead} { 1994 forward_eviction_to_cpu0; 1995 forward_eviction_to_cpu1; 1996 t_allocateTBE; 1997 vc_victim; 1998 ib_invBothClusters; 1999 i2_invL2; 2000 ii_invIcache; 2001 } 2002 2003 transition({Ms, M0, M1, O}, L2_Repl, MO_I) {L2TagArrayRead, L2DataArrayRead, L1D0TagArrayRead, L1D1TagArrayRead} { 2004 forward_eviction_to_cpu0; 2005 forward_eviction_to_cpu1; 2006 t_allocateTBE; 2007 vd_victim; 2008 i2_invL2; 2009 ib_invBothClusters; // nothing will happen for D0 on M1, vice versa 2010 } 2011 2012 transition(S0, NB_AckS, S) {L1D0DataArrayWrite, L1D0TagArrayWrite, L2DataArrayWrite, L2TagArrayWrite} { 2013 wi_writeIcache; 2014 xi0_loadDone; 2015 uu_sendUnblock; 2016 pr_popResponseQueue; 2017 } 2018 2019 transition(S1, NB_AckS, S) {L1D1DataArrayWrite, L1D1TagArrayWrite, L2DataArrayWrite, L2TagArrayWrite} { 2020 wi_writeIcache; 2021 xi1_loadDone; 2022 uu_sendUnblock; 2023 pr_popResponseQueue; 2024 } 2025 2026 transition(S0_C, NB_AckS, S_C) {L1D0DataArrayWrite,L2DataArrayWrite} { 2027 wi_writeIcache; 2028 xi0_loadDone; 2029 uu_sendUnblock; 2030 pr_popResponseQueue; 2031 } 2032 2033 transition(S1_C, NB_AckS, S_C) {L1D1DataArrayWrite, L2DataArrayWrite} { 2034 wi_writeIcache; 2035 xi1_loadDone; 2036 uu_sendUnblock; 2037 pr_popResponseQueue; 2038 } 2039 2040 transition(I_M0, NB_AckM, M0) {L1D0DataArrayWrite, L1D0TagArrayWrite,L2DataArrayWrite, L2TagArrayWrite} { 2041 w0_writeDcache; 2042 xs0_storeDone; 2043 uu_sendUnblock; 2044 pr_popResponseQueue; 2045 } 2046 2047 transition(I_M1, NB_AckM, M1) {L1D1DataArrayWrite, L1D1TagArrayWrite, L2DataArrayWrite, L2TagArrayWrite} { 2048 w1_writeDcache; 2049 xs1_storeDone; 2050 uu_sendUnblock; 2051 pr_popResponseQueue; 2052 } 2053 2054 // THESE MO->M1 should not be instantaneous but oh well for now. 2055 transition(I_M0M1, NB_AckM, M1) {L1D1DataArrayWrite, L1D1TagArrayWrite, L2DataArrayWrite, L2TagArrayWrite} { 2056 w0_writeDcache; 2057 xs0_storeDone; 2058 uu_sendUnblock; 2059 i0_invCluster; 2060 s1_storeDone; 2061 pr_popResponseQueue; 2062 } 2063 2064 transition(I_M1M0, NB_AckM, M0) {L1D0DataArrayWrite, L1D0TagArrayWrite, L2DataArrayWrite, L2TagArrayWrite} { 2065 w1_writeDcache; 2066 xs1_storeDone; 2067 uu_sendUnblock; 2068 i1_invCluster; 2069 s0_storeDone; 2070 pr_popResponseQueue; 2071 } 2072 2073 // Above shoudl be more like this, which has some latency to xfer to L1 2074 transition(I_M0Ms, NB_AckM, M0_Ms) {L1D0DataArrayWrite,L2DataArrayWrite} { 2075 w0_writeDcache; 2076 xs0_storeDone; 2077 uu_sendUnblock; 2078 f1_L2ToL1; 2079 pr_popResponseQueue; 2080 } 2081 2082 transition(I_M1Ms, NB_AckM, M1_Ms) {L1D1DataArrayWrite, L2DataArrayWrite} { 2083 w1_writeDcache; 2084 xs1_storeDone; 2085 uu_sendUnblock; 2086 f0_L2ToL1; 2087 pr_popResponseQueue; 2088 } 2089 2090 transition(I_E0S, NB_AckE, E0) {L1D0DataArrayWrite, L1D0TagArrayWrite, L2DataArrayWrite, L2TagArrayWrite} { 2091 w0_writeDcache; 2092 xl0_loadDone; 2093 uu_sendUnblock; 2094 pr_popResponseQueue; 2095 } 2096 2097 transition(I_E1S, NB_AckE, E1) {L1D1DataArrayWrite, L1D1TagArrayWrite, L2DataArrayWrite, L2TagArrayWrite} { 2098 w1_writeDcache; 2099 xl1_loadDone; 2100 uu_sendUnblock; 2101 pr_popResponseQueue; 2102 } 2103 2104 transition(I_ES, NB_AckE, Es) {L1D1DataArrayWrite, L1D1TagArrayWrite, L1D0DataArrayWrite, L1D0TagArrayWrite, L2DataArrayWrite, L2TagArrayWrite } { 2105 w0_writeDcache; 2106 xl0_loadDone; 2107 w1_writeDcache; 2108 xl1_loadDone; 2109 uu_sendUnblock; 2110 pr_popResponseQueue; 2111 } 2112 2113 transition(I_E0S, NB_AckS, S) {L1D0DataArrayWrite, L1D0TagArrayWrite,L2DataArrayWrite, L2TagArrayWrite} { 2114 w0_writeDcache; 2115 xl0_loadDone; 2116 uu_sendUnblock; 2117 pr_popResponseQueue; 2118 } 2119 2120 transition(I_E1S, NB_AckS, S) {L1D1TagArrayWrite, L1D1DataArrayWrite, L2TagArrayWrite, L2DataArrayWrite} { 2121 w1_writeDcache; 2122 xl1_loadDone; 2123 uu_sendUnblock; 2124 pr_popResponseQueue; 2125 } 2126 2127 transition(I_ES, NB_AckS, S) {L1D0TagArrayWrite, L1D0DataArrayWrite, L2TagArrayWrite, L2DataArrayWrite} { 2128 w0_writeDcache; 2129 xl0_loadDone; 2130 w1_writeDcache; 2131 xl1_loadDone; 2132 uu_sendUnblock; 2133 pr_popResponseQueue; 2134 } 2135 2136 transition(S_F0, L2_to_L1D0, S) {L1D0TagArrayWrite, L1D0DataArrayWrite, L2TagArrayWrite, L2DataArrayRead} { 2137 c0_copyL2ToL1; 2138 mru_setMRU; 2139 l0_loadDone; 2140 pt_popTriggerQueue; 2141 } 2142 2143 transition(S_F1, L2_to_L1D1, S) {L1D1TagArrayWrite, L1D1DataArrayWrite, L2TagArrayWrite, L2DataArrayRead} { 2144 c1_copyL2ToL1; 2145 mru_setMRU; 2146 l1_loadDone; 2147 pt_popTriggerQueue; 2148 } 2149 2150 transition(Si_F0, L2_to_L1I, S) {L1ITagArrayWrite, L1IDataArrayWrite, L2TagArrayWrite, L2DataArrayRead} { 2151 ci_copyL2ToL1; 2152 mru_setMRU; 2153 il0_loadDone; 2154 pt_popTriggerQueue; 2155 } 2156 2157 transition(Si_F1, L2_to_L1I, S) {L1ITagArrayWrite, L1IDataArrayWrite, L2TagArrayWrite, L2DataArrayRead} { 2158 ci_copyL2ToL1; 2159 mru_setMRU; 2160 il1_loadDone; 2161 pt_popTriggerQueue; 2162 } 2163 2164 transition(S_F, L2_to_L1D0, S_F1) { L1D0DataArrayWrite, L2DataArrayRead} { 2165 c0_copyL2ToL1; 2166 mru_setMRU; 2167 l0_loadDone; 2168 pt_popTriggerQueue; 2169 } 2170 2171 transition(S_F, L2_to_L1D1, S_F0) { L1D1DataArrayWrite, L2DataArrayRead} { 2172 c1_copyL2ToL1; 2173 mru_setMRU; 2174 l1_loadDone; 2175 pt_popTriggerQueue; 2176 } 2177 2178 transition(O_F0, L2_to_L1D0, O) { L1D0DataArrayWrite, L1D0TagArrayWrite, L2TagArrayWrite, L2DataArrayRead} { 2179 c0_copyL2ToL1; 2180 mru_setMRU; 2181 l0_loadDone; 2182 pt_popTriggerQueue; 2183 } 2184 2185 transition(O_F1, L2_to_L1D1, O) {L1D1DataArrayWrite, L1D1TagArrayWrite, L2TagArrayWrite, L2DataArrayRead} { 2186 c1_copyL2ToL1; 2187 mru_setMRU; 2188 l1_loadDone; 2189 pt_popTriggerQueue; 2190 } 2191 2192 transition(O_F, L2_to_L1D0, O_F1) { L1D0DataArrayWrite, L2DataArrayRead} { 2193 c0_copyL2ToL1; 2194 mru_setMRU; 2195 l0_loadDone; 2196 pt_popTriggerQueue; 2197 } 2198 2199 transition(O_F, L2_to_L1D1, O_F0) { L1D1DataArrayWrite, L2DataArrayRead} { 2200 c1_copyL2ToL1; 2201 mru_setMRU; 2202 l1_loadDone; 2203 pt_popTriggerQueue; 2204 } 2205 2206 transition(M1_F, L2_to_L1D1, M1) {L1D1DataArrayWrite, L1D1TagArrayWrite, L2TagArrayWrite, L2DataArrayRead} { 2207 c1_copyL2ToL1; 2208 mru_setMRU; 2209 l1_loadDone; 2210 pt_popTriggerQueue; 2211 } 2212 2213 transition(M0_F, L2_to_L1D0, M0) {L1D0DataArrayWrite, L1D0TagArrayWrite, L2TagArrayWrite, L2DataArrayRead} { 2214 c0_copyL2ToL1; 2215 mru_setMRU; 2216 l0_loadDone; 2217 pt_popTriggerQueue; 2218 } 2219 2220 transition(Ms_F0, L2_to_L1D0, Ms) {L1D0DataArrayWrite, L1D0TagArrayWrite, L2TagArrayWrite, L2DataArrayRead} { 2221 c0_copyL2ToL1; 2222 mru_setMRU; 2223 l0_loadDone; 2224 pt_popTriggerQueue; 2225 } 2226 2227 transition(Ms_F1, L2_to_L1D1, Ms) {L1D1DataArrayWrite, L1D1TagArrayWrite, L2TagArrayWrite, L2DataArrayRead} { 2228 c1_copyL2ToL1; 2229 mru_setMRU; 2230 l1_loadDone; 2231 pt_popTriggerQueue; 2232 } 2233 2234 transition(Ms_F, L2_to_L1D0, Ms_F1) {L1D0DataArrayWrite, L2DataArrayRead} { 2235 c0_copyL2ToL1; 2236 mru_setMRU; 2237 l0_loadDone; 2238 pt_popTriggerQueue; 2239 } 2240 2241 transition(Ms_F, L2_to_L1D1, Ms_F0) {L1IDataArrayWrite, L2DataArrayRead} { 2242 c1_copyL2ToL1; 2243 mru_setMRU; 2244 l1_loadDone; 2245 pt_popTriggerQueue; 2246 } 2247 2248 transition(M1_Ms, L2_to_L1D0, Ms) {L1D0TagArrayWrite, L1D0DataArrayWrite, L2TagArrayWrite, L2DataArrayRead} { 2249 c0_copyL2ToL1; 2250 mru_setMRU; 2251 l0_loadDone; 2252 pt_popTriggerQueue; 2253 } 2254 2255 transition(M0_Ms, L2_to_L1D1, Ms) {L1D1TagArrayWrite, L1D1DataArrayWrite, L2TagArrayWrite, L2DataArrayRead} { 2256 c1_copyL2ToL1; 2257 mru_setMRU; 2258 l1_loadDone; 2259 pt_popTriggerQueue; 2260 } 2261 2262 transition(Es_F0, L2_to_L1D0, Es) {L1D0TagArrayWrite, L1D0DataArrayWrite, L2TagArrayWrite, L2DataArrayRead} { 2263 c0_copyL2ToL1; 2264 mru_setMRU; 2265 l0_loadDone; 2266 pt_popTriggerQueue; 2267 } 2268 2269 transition(Es_F1, L2_to_L1D1, Es) {L1D1TagArrayWrite, L1D1DataArrayWrite, L2TagArrayWrite, L2DataArrayRead} { 2270 c1_copyL2ToL1; 2271 mru_setMRU; 2272 l1_loadDone; 2273 pt_popTriggerQueue; 2274 } 2275 2276 transition(Es_F, L2_to_L1D0, Es_F1) {L2TagArrayRead, L2DataArrayRead} { 2277 c0_copyL2ToL1; 2278 mru_setMRU; 2279 l0_loadDone; 2280 pt_popTriggerQueue; 2281 } 2282 2283 transition(Es_F, L2_to_L1D1, Es_F0) {L2TagArrayRead, L2DataArrayRead} { 2284 c1_copyL2ToL1; 2285 mru_setMRU; 2286 l1_loadDone; 2287 pt_popTriggerQueue; 2288 } 2289 2290 transition(E0_F, L2_to_L1D0, E0) {L2TagArrayRead, L2DataArrayRead} { 2291 c0_copyL2ToL1; 2292 mru_setMRU; 2293 l0_loadDone; 2294 pt_popTriggerQueue; 2295 } 2296 2297 transition(E1_F, L2_to_L1D1, E1) {L2TagArrayRead, L2DataArrayRead} { 2298 c1_copyL2ToL1; 2299 mru_setMRU; 2300 l1_loadDone; 2301 pt_popTriggerQueue; 2302 } 2303 2304 transition(E1_Es, L2_to_L1D0, Es) {L2TagArrayRead, L2DataArrayRead} { 2305 c0_copyL2ToL1; 2306 mru_setMRU; 2307 l0_loadDone; 2308 pt_popTriggerQueue; 2309 } 2310 2311 transition(E0_Es, L2_to_L1D1, Es) {L2TagArrayRead, L2DataArrayRead} { 2312 c1_copyL2ToL1; 2313 mru_setMRU; 2314 l1_loadDone; 2315 pt_popTriggerQueue; 2316 } 2317 2318 transition(IF_E0S, L2_to_L1D0, I_E0S) {} { 2319 pt_popTriggerQueue; 2320 } 2321 2322 transition(IF_E1S, L2_to_L1D1, I_E1S) {} { 2323 pt_popTriggerQueue; 2324 } 2325 2326 transition(IF_ES, L2_to_L1D0, IF1_ES) {} { 2327 pt_popTriggerQueue; 2328 } 2329 2330 transition(IF_ES, L2_to_L1D1, IF0_ES) {} { 2331 pt_popTriggerQueue; 2332 } 2333 2334 transition(IF0_ES, L2_to_L1D0, I_ES) {} { 2335 pt_popTriggerQueue; 2336 } 2337 2338 transition(IF1_ES, L2_to_L1D1, I_ES) {} { 2339 pt_popTriggerQueue; 2340 } 2341 2342 transition(F_S0, L2_to_L1I, S0) {} { 2343 pt_popTriggerQueue; 2344 } 2345 2346 transition(F_S1, L2_to_L1I, S1) {} { 2347 pt_popTriggerQueue; 2348 } 2349 2350 transition({S_M0, O_M0}, NB_AckM, M0) {L1D0TagArrayWrite, L1D0DataArrayWrite, L2DataArrayWrite, L2TagArrayWrite} { 2351 mru_setMRU; 2352 xs0_storeDone; 2353 uu_sendUnblock; 2354 pr_popResponseQueue; 2355 } 2356 2357 transition({S_M1, O_M1}, NB_AckM, M1) {L1D1TagArrayWrite, L1D1DataArrayWrite, L2DataArrayWrite, L2TagArrayWrite} { 2358 mru_setMRU; 2359 xs1_storeDone; 2360 uu_sendUnblock; 2361 pr_popResponseQueue; 2362 } 2363 2364 transition(MO_I, NB_AckWB, I) {L2TagArrayWrite} { 2365 wb_data; 2366 d_deallocateTBE; 2367 pr_popResponseQueue; 2368 } 2369 2370 transition(ES_I, NB_AckWB, I) {L2TagArrayWrite} { 2371 wb_data; 2372 d_deallocateTBE; 2373 pr_popResponseQueue; 2374 } 2375 2376 transition(MO_S0, NB_AckWB, S0) {L2TagArrayWrite} { 2377 wb_data; 2378 i2_invL2; 2379 a2_allocateL2; 2380 d_deallocateTBE; // FOO 2381 nS_issueRdBlkS; 2382 pr_popResponseQueue; 2383 } 2384 2385 transition(MO_S1, NB_AckWB, S1) {L2TagArrayWrite} { 2386 wb_data; 2387 i2_invL2; 2388 a2_allocateL2; 2389 d_deallocateTBE; // FOO 2390 nS_issueRdBlkS; 2391 pr_popResponseQueue; 2392 } 2393 2394 // Writeback cancel "ack" 2395 transition(I_C, NB_AckWB, I) {L2TagArrayWrite} { 2396 ss_sendStaleNotification; 2397 d_deallocateTBE; 2398 pr_popResponseQueue; 2399 } 2400 2401 transition(S0_C, NB_AckWB, S0) {L2TagArrayWrite} { 2402 ss_sendStaleNotification; 2403 pr_popResponseQueue; 2404 } 2405 2406 transition(S1_C, NB_AckWB, S1) {L2TagArrayWrite} { 2407 ss_sendStaleNotification; 2408 pr_popResponseQueue; 2409 } 2410 2411 transition(S_C, NB_AckWB, S) {L2TagArrayWrite} { 2412 ss_sendStaleNotification; 2413 pr_popResponseQueue; 2414 } 2415 2416 // Begin Probe Transitions 2417 2418 transition({Ms, M0, M1, O}, PrbInvData, I) {L2TagArrayRead, L2TagArrayWrite, L2DataArrayRead} { 2419 forward_eviction_to_cpu0; 2420 forward_eviction_to_cpu1; 2421 pd_sendProbeResponseData; 2422 i2_invL2; 2423 ib_invBothClusters; 2424 pp_popProbeQueue; 2425 } 2426 2427 transition({Es, E0, E1, S, I}, PrbInvData, I) {L2TagArrayRead, L2TagArrayWrite} { 2428 forward_eviction_to_cpu0; 2429 forward_eviction_to_cpu1; 2430 pi_sendProbeResponseInv; 2431 i2_invL2; 2432 ib_invBothClusters; 2433 ii_invIcache; // only relevant for S 2434 pp_popProbeQueue; 2435 } 2436 2437 transition(S_C, PrbInvData, I_C) {L2TagArrayWrite} { 2438 t_allocateTBE; 2439 forward_eviction_to_cpu0; 2440 forward_eviction_to_cpu1; 2441 pi_sendProbeResponseInv; 2442 i2_invL2; 2443 ib_invBothClusters; 2444 ii_invIcache; 2445 pp_popProbeQueue; 2446 } 2447 2448 transition(I_C, PrbInvData, I_C) {} { 2449 pi_sendProbeResponseInv; 2450 ib_invBothClusters; 2451 pp_popProbeQueue; 2452 } 2453 2454 transition({Ms, M0, M1, O, Es, E0, E1, S, I}, PrbInv, I) {L2TagArrayRead, L2TagArrayWrite} { 2455 forward_eviction_to_cpu0; 2456 forward_eviction_to_cpu1; 2457 pi_sendProbeResponseInv; 2458 i2_invL2; // nothing will happen in I 2459 ib_invBothClusters; 2460 ii_invIcache; 2461 pp_popProbeQueue; 2462 } 2463 2464 transition(S_C, PrbInv, I_C) {L2TagArrayWrite} { 2465 t_allocateTBE; 2466 forward_eviction_to_cpu0; 2467 forward_eviction_to_cpu1; 2468 pi_sendProbeResponseInv; 2469 i2_invL2; 2470 ib_invBothClusters; 2471 ii_invIcache; 2472 pp_popProbeQueue; 2473 } 2474 2475 transition(I_C, PrbInv, I_C) {} { 2476 pi_sendProbeResponseInv; 2477 ib_invBothClusters; 2478 ii_invIcache; 2479 pp_popProbeQueue; 2480 } 2481 2482 transition({Ms, M0, M1, O}, PrbShrData, O) {L2TagArrayRead, L2TagArrayWrite, L2DataArrayRead} { 2483 pd_sendProbeResponseData; 2484 pp_popProbeQueue; 2485 } 2486 2487 transition({Es, E0, E1, S}, PrbShrData, S) {L2TagArrayRead, L2TagArrayWrite} { 2488 ph_sendProbeResponseHit; 2489 pp_popProbeQueue; 2490 } 2491 2492 transition(S_C, PrbShrData) {} { 2493 ph_sendProbeResponseHit; 2494 pp_popProbeQueue; 2495 } 2496 2497 transition({I, I_C}, PrbShrData) {L2TagArrayRead} { 2498 pb_sendProbeResponseBackprobe; 2499 pp_popProbeQueue; 2500 } 2501 2502 transition({I_M0, I_E0S}, {PrbInv, PrbInvData}) {} { 2503 pi_sendProbeResponseInv; 2504 ib_invBothClusters; // must invalidate current data (only relevant for I_M0) 2505 a0_allocateL1D; // but make sure there is room for incoming data when it arrives 2506 pp_popProbeQueue; 2507 } 2508 2509 transition({I_M1, I_E1S}, {PrbInv, PrbInvData}) {} { 2510 pi_sendProbeResponseInv; 2511 ib_invBothClusters; // must invalidate current data (only relevant for I_M1) 2512 a1_allocateL1D; // but make sure there is room for incoming data when it arrives 2513 pp_popProbeQueue; 2514 } 2515 2516 transition({I_M0M1, I_M1M0, I_M0Ms, I_M1Ms, I_ES}, {PrbInv, PrbInvData, PrbShrData}) {} { 2517 pi_sendProbeResponseInv; 2518 ib_invBothClusters; 2519 a0_allocateL1D; 2520 a1_allocateL1D; 2521 pp_popProbeQueue; 2522 } 2523 2524 transition({I_M0, I_E0S, I_M1, I_E1S}, PrbShrData) {} { 2525 pb_sendProbeResponseBackprobe; 2526 pp_popProbeQueue; 2527 } 2528 2529 transition(ES_I, PrbInvData, I_C) {} { 2530 pi_sendProbeResponseInv; 2531 ib_invBothClusters; 2532 ii_invIcache; 2533 pp_popProbeQueue; 2534 } 2535 2536 transition(MO_I, PrbInvData, I_C) {} { 2537 pdt_sendProbeResponseDataFromTBE; 2538 ib_invBothClusters; 2539 ii_invIcache; 2540 pp_popProbeQueue; 2541 } 2542 2543 transition(MO_I, PrbInv, I_C) {} { 2544 pi_sendProbeResponseInv; 2545 ib_invBothClusters; 2546 ii_invIcache; 2547 pp_popProbeQueue; 2548 } 2549 2550 transition(ES_I, PrbInv, I_C) {} { 2551 pi_sendProbeResponseInv; 2552 ib_invBothClusters; 2553 ii_invIcache; 2554 pp_popProbeQueue; 2555 } 2556 2557 transition(ES_I, PrbShrData, ES_I) {} { 2558 ph_sendProbeResponseHit; 2559 s_setSharedFlip; 2560 pp_popProbeQueue; 2561 } 2562 2563 transition(MO_I, PrbShrData, MO_I) {} { 2564 pdt_sendProbeResponseDataFromTBE; 2565 s_setSharedFlip; 2566 pp_popProbeQueue; 2567 } 2568 2569 transition(MO_S0, PrbInvData, S0_C) {L2TagArrayWrite} { 2570 forward_eviction_to_cpu0; 2571 forward_eviction_to_cpu1; 2572 pdt_sendProbeResponseDataFromTBE; 2573 i2_invL2; 2574 a2_allocateL2; 2575 d_deallocateTBE; 2576 nS_issueRdBlkS; 2577 pp_popProbeQueue; 2578 } 2579 2580 transition(MO_S1, PrbInvData, S1_C) {L2TagArrayWrite} { 2581 forward_eviction_to_cpu0; 2582 forward_eviction_to_cpu1; 2583 pdt_sendProbeResponseDataFromTBE; 2584 i2_invL2; 2585 a2_allocateL2; 2586 d_deallocateTBE; 2587 nS_issueRdBlkS; 2588 pp_popProbeQueue; 2589 } 2590 2591 transition(MO_S0, PrbInv, S0_C) {L2TagArrayWrite} { 2592 forward_eviction_to_cpu0; 2593 forward_eviction_to_cpu1; 2594 pi_sendProbeResponseInv; 2595 i2_invL2; 2596 a2_allocateL2; 2597 d_deallocateTBE; 2598 nS_issueRdBlkS; 2599 pp_popProbeQueue; 2600 } 2601 2602 transition(MO_S1, PrbInv, S1_C) {L2TagArrayWrite} { 2603 forward_eviction_to_cpu0; 2604 forward_eviction_to_cpu1; 2605 pi_sendProbeResponseInv; 2606 i2_invL2; 2607 a2_allocateL2; 2608 d_deallocateTBE; 2609 nS_issueRdBlkS; 2610 pp_popProbeQueue; 2611 } 2612 2613 transition({MO_S0, MO_S1}, PrbShrData) {} { 2614 pdt_sendProbeResponseDataFromTBE; 2615 s_setSharedFlip; 2616 pp_popProbeQueue; 2617 } 2618 2619 transition({S_F0, Es_F0, E0_F, E1_Es}, {PrbInvData, PrbInv}, IF_E0S) {}{ 2620 forward_eviction_to_cpu0; 2621 forward_eviction_to_cpu1; 2622 pi_sendProbeResponseInv; 2623 // invalidate everything you've got 2624 ib_invBothClusters; 2625 ii_invIcache; 2626 i2_invL2; 2627 // but make sure you have room for what you need from the fill 2628 a0_allocateL1D; 2629 a2_allocateL2; 2630 n_issueRdBlk; 2631 pp_popProbeQueue; 2632 } 2633 2634 transition({S_F1, Es_F1, E1_F, E0_Es}, {PrbInvData, PrbInv}, IF_E1S) {} { 2635 forward_eviction_to_cpu0; 2636 forward_eviction_to_cpu1; 2637 pi_sendProbeResponseInv; 2638 // invalidate everything you've got 2639 ib_invBothClusters; 2640 ii_invIcache; 2641 i2_invL2; 2642 // but make sure you have room for what you need from the fill 2643 a1_allocateL1D; 2644 a2_allocateL2; 2645 n_issueRdBlk; 2646 pp_popProbeQueue; 2647 } 2648 2649 transition({S_F, Es_F}, {PrbInvData, PrbInv}, IF_ES) {} { 2650 forward_eviction_to_cpu0; 2651 forward_eviction_to_cpu1; 2652 pi_sendProbeResponseInv; 2653 // invalidate everything you've got 2654 ib_invBothClusters; 2655 ii_invIcache; 2656 i2_invL2; 2657 // but make sure you have room for what you need from the fill 2658 a0_allocateL1D; 2659 a1_allocateL1D; 2660 a2_allocateL2; 2661 n_issueRdBlk; 2662 pp_popProbeQueue; 2663 } 2664 2665 transition(Si_F0, {PrbInvData, PrbInv}, F_S0) {} { 2666 forward_eviction_to_cpu0; 2667 forward_eviction_to_cpu1; 2668 pi_sendProbeResponseInv; 2669 ib_invBothClusters; 2670 ii_invIcache; 2671 i2_invL2; 2672 ai_allocateL1I; 2673 a2_allocateL2; 2674 nS_issueRdBlkS; 2675 pp_popProbeQueue; 2676 } 2677 2678 transition(Si_F1, {PrbInvData, PrbInv}, F_S1) {} { 2679 forward_eviction_to_cpu0; 2680 forward_eviction_to_cpu1; 2681 pi_sendProbeResponseInv; 2682 ib_invBothClusters; 2683 ii_invIcache; 2684 i2_invL2; 2685 ai_allocateL1I; 2686 a2_allocateL2; 2687 nS_issueRdBlkS; 2688 pp_popProbeQueue; 2689 } 2690 2691 transition({Es_F0, E0_F, E1_Es}, PrbShrData, S_F0) {} { 2692 ph_sendProbeResponseHit; 2693 pp_popProbeQueue; 2694 } 2695 2696 transition({Es_F1, E1_F, E0_Es}, PrbShrData, S_F1) {} { 2697 ph_sendProbeResponseHit; 2698 pp_popProbeQueue; 2699 } 2700 2701 transition(Es_F, PrbShrData, S_F) {} { 2702 ph_sendProbeResponseHit; 2703 pp_popProbeQueue; 2704 } 2705 2706 transition({S_F0, S_F1, S_F, Si_F0, Si_F1}, PrbShrData) {} { 2707 ph_sendProbeResponseHit; 2708 pp_popProbeQueue; 2709 } 2710 2711 transition(S_M0, PrbInvData, I_M0) {} { 2712 forward_eviction_to_cpu0; 2713 forward_eviction_to_cpu1; 2714 pim_sendProbeResponseInvMs; 2715 ib_invBothClusters; 2716 ii_invIcache; 2717 i2_invL2; 2718 a0_allocateL1D; 2719 a2_allocateL2; 2720 pp_popProbeQueue; 2721 } 2722 2723 transition(O_M0, PrbInvData, I_M0) {L2DataArrayRead} { 2724 forward_eviction_to_cpu0; 2725 forward_eviction_to_cpu1; 2726 pdm_sendProbeResponseDataMs; 2727 ib_invBothClusters; 2728 ii_invIcache; 2729 i2_invL2; 2730 a0_allocateL1D; 2731 a2_allocateL2; 2732 pp_popProbeQueue; 2733 } 2734 2735 transition({S_M0, O_M0}, {PrbInv}, I_M0) {} { 2736 forward_eviction_to_cpu0; 2737 forward_eviction_to_cpu1; 2738 pim_sendProbeResponseInvMs; 2739 ib_invBothClusters; 2740 ii_invIcache; 2741 i2_invL2; 2742 a0_allocateL1D; 2743 a2_allocateL2; 2744 pp_popProbeQueue; 2745 } 2746 2747 transition(S_M1, PrbInvData, I_M1) {} { 2748 forward_eviction_to_cpu0; 2749 forward_eviction_to_cpu1; 2750 pim_sendProbeResponseInvMs; 2751 ib_invBothClusters; 2752 ii_invIcache; 2753 i2_invL2; 2754 a1_allocateL1D; 2755 a2_allocateL2; 2756 pp_popProbeQueue; 2757 } 2758 2759 transition(O_M1, PrbInvData, I_M1) {} { 2760 forward_eviction_to_cpu0; 2761 forward_eviction_to_cpu1; 2762 pdm_sendProbeResponseDataMs; 2763 ib_invBothClusters; 2764 ii_invIcache; 2765 i2_invL2; 2766 a1_allocateL1D; 2767 a2_allocateL2; 2768 pp_popProbeQueue; 2769 } 2770 2771 transition({S_M1, O_M1}, {PrbInv}, I_M1) {} { 2772 forward_eviction_to_cpu0; 2773 forward_eviction_to_cpu1; 2774 pim_sendProbeResponseInvMs; 2775 ib_invBothClusters; 2776 ii_invIcache; 2777 i2_invL2; 2778 a1_allocateL1D; 2779 a2_allocateL2; 2780 pp_popProbeQueue; 2781 } 2782 2783 transition({S0, S0_C}, {PrbInvData, PrbInv}) {} { 2784 forward_eviction_to_cpu0; 2785 forward_eviction_to_cpu1; 2786 pi_sendProbeResponseInv; 2787 ib_invBothClusters; 2788 ii_invIcache; 2789 i2_invL2; 2790 ai_allocateL1I; 2791 a2_allocateL2; 2792 pp_popProbeQueue; 2793 } 2794 2795 transition({S1, S1_C}, {PrbInvData, PrbInv}) {} { 2796 forward_eviction_to_cpu0; 2797 forward_eviction_to_cpu1; 2798 pi_sendProbeResponseInv; 2799 ib_invBothClusters; 2800 ii_invIcache; 2801 i2_invL2; 2802 ai_allocateL1I; 2803 a2_allocateL2; 2804 pp_popProbeQueue; 2805 } 2806 2807 transition({S_M0, S_M1}, PrbShrData) {} { 2808 ph_sendProbeResponseHit; 2809 pp_popProbeQueue; 2810 } 2811 2812 transition({O_M0, O_M1}, PrbShrData) {L2DataArrayRead} { 2813 pd_sendProbeResponseData; 2814 pp_popProbeQueue; 2815 } 2816 2817 transition({S0, S1, S0_C, S1_C}, PrbShrData) {} { 2818 pb_sendProbeResponseBackprobe; 2819 pp_popProbeQueue; 2820 } 2821 2822 transition({Ms_F0, M0_F, M1_Ms, O_F0}, PrbInvData, IF_E0S) { L2DataArrayRead} { 2823 forward_eviction_to_cpu0; 2824 forward_eviction_to_cpu1; 2825 pd_sendProbeResponseData; 2826 ib_invBothClusters; 2827 i2_invL2; 2828 a0_allocateL1D; 2829 a2_allocateL2; 2830 n_issueRdBlk; 2831 pp_popProbeQueue; 2832 } 2833 2834 transition({Ms_F1, M1_F, M0_Ms, O_F1}, PrbInvData, IF_E1S) {L2DataArrayRead} { 2835 forward_eviction_to_cpu0; 2836 forward_eviction_to_cpu1; 2837 pd_sendProbeResponseData; 2838 ib_invBothClusters; 2839 i2_invL2; 2840 a1_allocateL1D; 2841 a2_allocateL2; 2842 n_issueRdBlk; 2843 pp_popProbeQueue; 2844 } 2845 2846 transition({Ms_F, O_F}, PrbInvData, IF_ES) {L2DataArrayRead} { 2847 forward_eviction_to_cpu0; 2848 forward_eviction_to_cpu1; 2849 pd_sendProbeResponseData; 2850 ib_invBothClusters; 2851 i2_invL2; 2852 a0_allocateL1D; 2853 a1_allocateL1D; 2854 a2_allocateL2; 2855 n_issueRdBlk; 2856 pp_popProbeQueue; 2857 } 2858 2859 transition({Ms_F0, M0_F, M1_Ms, O_F0}, PrbInv, IF_E0S) {} { 2860 forward_eviction_to_cpu0; 2861 forward_eviction_to_cpu1; 2862 pi_sendProbeResponseInv; 2863 ib_invBothClusters; 2864 i2_invL2; 2865 a0_allocateL1D; 2866 a2_allocateL2; 2867 n_issueRdBlk; 2868 pp_popProbeQueue; 2869 } 2870 2871 transition({Ms_F1, M1_F, M0_Ms, O_F1}, PrbInv, IF_E1S) {} { 2872 forward_eviction_to_cpu0; 2873 forward_eviction_to_cpu1; 2874 pi_sendProbeResponseInv; 2875 ib_invBothClusters; 2876 i2_invL2; 2877 a1_allocateL1D; 2878 a2_allocateL2; 2879 n_issueRdBlk; 2880 pp_popProbeQueue; 2881 } 2882 2883 transition({Ms_F, O_F}, PrbInv, IF_ES) {} { 2884 forward_eviction_to_cpu0; 2885 forward_eviction_to_cpu1; 2886 pi_sendProbeResponseInv; 2887 ib_invBothClusters; 2888 i2_invL2; 2889 a0_allocateL1D; 2890 a1_allocateL1D; 2891 a2_allocateL2; 2892 n_issueRdBlk; 2893 pp_popProbeQueue; 2894 } 2895 2896 transition({Ms_F0, M0_F, M1_Ms}, PrbShrData, O_F0) {L2DataArrayRead} { 2897 pd_sendProbeResponseData; 2898 pp_popProbeQueue; 2899 } 2900 2901 transition({Ms_F1, M1_F, M0_Ms}, PrbShrData, O_F1) {} { 2902 } 2903 2904 transition({Ms_F}, PrbShrData, O_F) {L2DataArrayRead} { 2905 pd_sendProbeResponseData; 2906 pp_popProbeQueue; 2907 } 2908 2909 transition({O_F0, O_F1, O_F}, PrbShrData) {L2DataArrayRead} { 2910 pd_sendProbeResponseData; 2911 pp_popProbeQueue; 2912 } 2913 2914 // END TRANSITIONS 2915} 2916 2917 2918