request.hh revision 10824:308771bd2647
19243SN/A/* 212706Swendy.elsasser@arm.com * Copyright (c) 2012-2013 ARM Limited 39243SN/A * All rights reserved 49243SN/A * 59243SN/A * The license below extends only to copyright in the software and shall 69243SN/A * not be construed as granting a license to any other intellectual 79243SN/A * property including but not limited to intellectual property relating 89243SN/A * to a hardware implementation of the functionality of the software 99243SN/A * licensed hereunder. You may use the software subject to the license 109243SN/A * terms below provided that you ensure that this notice is replicated 119243SN/A * unmodified and in its entirety in all distributions of the software, 129243SN/A * modified or unmodified, in source code or in binary form. 139243SN/A * 149831SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 159831SN/A * All rights reserved. 169831SN/A * 179243SN/A * Redistribution and use in source and binary forms, with or without 189243SN/A * modification, are permitted provided that the following conditions are 199243SN/A * met: redistributions of source code must retain the above copyright 209243SN/A * notice, this list of conditions and the following disclaimer; 219243SN/A * redistributions in binary form must reproduce the above copyright 229243SN/A * notice, this list of conditions and the following disclaimer in the 239243SN/A * documentation and/or other materials provided with the distribution; 249243SN/A * neither the name of the copyright holders nor the names of its 259243SN/A * contributors may be used to endorse or promote products derived from 269243SN/A * this software without specific prior written permission. 279243SN/A * 289243SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 299243SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 309243SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 319243SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 329243SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 339243SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 349243SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 359243SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 369243SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 379243SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 389243SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 399243SN/A * 409243SN/A * Authors: Ron Dreslinski 419243SN/A * Steve Reinhardt 429967SN/A * Ali Saidi 4310618SOmar.Naji@arm.com */ 4411678Swendy.elsasser@arm.com 4512266Sradhika.jagtap@arm.com/** 469243SN/A * @file 479243SN/A * Declaration of a request, the overall memory request consisting of 4811793Sbrandon.potter@amd.com the parts of the request that are persistent throughout the transaction. 4911793Sbrandon.potter@amd.com */ 5010146Sandreas.hansson@arm.com 519356SN/A#ifndef __MEM_REQUEST_HH__ 5210146Sandreas.hansson@arm.com#define __MEM_REQUEST_HH__ 5310247Sandreas.hansson@arm.com 5410208Sandreas.hansson@arm.com#include <cassert> 559352SN/A#include <climits> 5612969SMatteo.Andreozzi@arm.com 579814SN/A#include "base/flags.hh" 589243SN/A#include "base/misc.hh" 599243SN/A#include "base/types.hh" 6010432SOmar.Naji@arm.com#include "sim/core.hh" 619243SN/A 6210146Sandreas.hansson@arm.com/** 6312969SMatteo.Andreozzi@arm.com * Special TaskIds that are used for per-context-switch stats dumps 6410619Sandreas.hansson@arm.com * and Cache Occupancy. Having too many tasks seems to be a problem 659243SN/A * with vector stats. 1024 seems to be a reasonable number that 6612084Sspwilson2@wisc.edu * doesn't cause a problem with stats and is large enough to realistic 6712084Sspwilson2@wisc.edu * benchmarks (Linux/Android boot, BBench, etc.) 6810489SOmar.Naji@arm.com */ 699831SN/A 709831SN/Anamespace ContextSwitchTaskId { 719831SN/A enum TaskId { 729831SN/A MaxNormalTaskId = 1021, /* Maximum number of normal tasks */ 739831SN/A Prefetcher = 1022, /* For cache lines brought in by prefetcher */ 7410140SN/A DMA = 1023, /* Mostly Table Walker */ 7510646Sandreas.hansson@arm.com Unknown = 1024, 769243SN/A NumTaskId 7710394Swendy.elsasser@arm.com }; 7810394Swendy.elsasser@arm.com} 799566SN/A 809243SN/Aclass Request; 819243SN/A 8210140SN/Atypedef Request* RequestPtr; 8310140SN/Atypedef uint16_t MasterID; 8410147Sandreas.hansson@arm.com 8510147Sandreas.hansson@arm.comclass Request 8612706Swendy.elsasser@arm.com{ 8712706Swendy.elsasser@arm.com public: 8810394Swendy.elsasser@arm.com typedef uint32_t FlagsType; 8910394Swendy.elsasser@arm.com typedef uint8_t ArchFlagsType; 9011673SOmar.Naji@arm.com typedef ::Flags<FlagsType> Flags; 9112706Swendy.elsasser@arm.com 9212706Swendy.elsasser@arm.com /** 939243SN/A * Architecture specific flags. 949243SN/A * 9510141SN/A * These bits int the flag field are reserved for 969726SN/A * architecture-specific code. For example, SPARC uses them to 979726SN/A * represent ASIs. 9812706Swendy.elsasser@arm.com */ 9912266Sradhika.jagtap@arm.com static const FlagsType ARCH_BITS = 0x000000FF; 10012266Sradhika.jagtap@arm.com /** The request was an instruction fetch. */ 1019243SN/A static const FlagsType INST_FETCH = 0x00000100; 10210620Sandreas.hansson@arm.com /** The virtual address is also the physical address. */ 10310620Sandreas.hansson@arm.com static const FlagsType PHYSICAL = 0x00000200; 10410620Sandreas.hansson@arm.com /** 10510620Sandreas.hansson@arm.com * The request is to an uncacheable address. 10610620Sandreas.hansson@arm.com * 10710889Sandreas.hansson@arm.com * @note Uncacheable accesses may be reordered by CPU models. The 10810889Sandreas.hansson@arm.com * STRICT_ORDER flag should be set if such reordering is 10912969SMatteo.Andreozzi@arm.com * undesirable. 11012969SMatteo.Andreozzi@arm.com */ 11112969SMatteo.Andreozzi@arm.com static const FlagsType UNCACHEABLE = 0x00000400; 11210889Sandreas.hansson@arm.com /** 11310618SOmar.Naji@arm.com * The request is required to be strictly ordered by <i>CPU 11412081Sspwilson2@wisc.edu * models</i> and is non-speculative. 11510618SOmar.Naji@arm.com * 11610246Sandreas.hansson@arm.com * A strictly ordered request is guaranteed to never be re-ordered 11710246Sandreas.hansson@arm.com * or executed speculatively by a CPU model. The memory system may 11810140SN/A * still reorder requests in caches unless the UNCACHEABLE flag is 11910140SN/A * set as well. 12010140SN/A */ 12110140SN/A static const FlagsType STRICT_ORDER = 0x00000800; 12210140SN/A /** This request is to a memory mapped register. */ 1239243SN/A static const FlagsType MMAPPED_IPR = 0x00002000; 1249243SN/A /** This request is a clear exclusive. */ 1259567SN/A static const FlagsType CLEAR_LL = 0x00004000; 1269243SN/A /** This request is made in privileged mode. */ 12710489SOmar.Naji@arm.com static const FlagsType PRIVILEGED = 0x00008000; 12810489SOmar.Naji@arm.com 12910489SOmar.Naji@arm.com /** This is a write that is targeted and zeroing an entire cache block. 13010489SOmar.Naji@arm.com * There is no need for a read/modify/write 13110489SOmar.Naji@arm.com */ 13210489SOmar.Naji@arm.com static const FlagsType CACHE_BLOCK_ZERO = 0x00010000; 13310489SOmar.Naji@arm.com 13410489SOmar.Naji@arm.com /** The request should not cause a memory access. */ 13510489SOmar.Naji@arm.com static const FlagsType NO_ACCESS = 0x00080000; 13610489SOmar.Naji@arm.com /** This request will lock or unlock the accessed memory. When used with 1379243SN/A * a load, the access locks the particular chunk of memory. When used 1389243SN/A * with a store, it unlocks. The rule is that locked accesses have to be 1399831SN/A * made up of a locked load, some operation on the data, and then a locked 1409831SN/A * store. 1419831SN/A */ 1429831SN/A static const FlagsType LOCKED_RMW = 0x00100000; 1439831SN/A /** The request is a Load locked/store conditional. */ 1449243SN/A static const FlagsType LLSC = 0x00200000; 14510207Sandreas.hansson@arm.com /** This request is for a memory swap. */ 14610207Sandreas.hansson@arm.com static const FlagsType MEM_SWAP = 0x00400000; 14710207Sandreas.hansson@arm.com static const FlagsType MEM_SWAP_COND = 0x00800000; 14810207Sandreas.hansson@arm.com 14910207Sandreas.hansson@arm.com /** The request is a prefetch. */ 15010394Swendy.elsasser@arm.com static const FlagsType PREFETCH = 0x01000000; 15110394Swendy.elsasser@arm.com /** The request should be prefetched into the exclusive state. */ 15210394Swendy.elsasser@arm.com static const FlagsType PF_EXCLUSIVE = 0x02000000; 15310394Swendy.elsasser@arm.com /** The request should be marked as LRU. */ 15410394Swendy.elsasser@arm.com static const FlagsType EVICT_NEXT = 0x04000000; 15510394Swendy.elsasser@arm.com 15610394Swendy.elsasser@arm.com /** The request should be handled by the generic IPR code (only 15710394Swendy.elsasser@arm.com * valid together with MMAPPED_IPR) */ 15810394Swendy.elsasser@arm.com static const FlagsType GENERIC_IPR = 0x08000000; 15910394Swendy.elsasser@arm.com 16010394Swendy.elsasser@arm.com /** The request targets the secure memory space. */ 16110394Swendy.elsasser@arm.com static const FlagsType SECURE = 0x10000000; 16210394Swendy.elsasser@arm.com /** The request is a page table walk */ 16310394Swendy.elsasser@arm.com static const FlagsType PT_WALK = 0x20000000; 16410394Swendy.elsasser@arm.com 16510394Swendy.elsasser@arm.com /** These flags are *not* cleared when a Request object is reused 16610394Swendy.elsasser@arm.com (assigned a new address). */ 16710394Swendy.elsasser@arm.com static const FlagsType STICKY_FLAGS = INST_FETCH; 16810394Swendy.elsasser@arm.com 16910394Swendy.elsasser@arm.com /** Request Ids that are statically allocated 17010394Swendy.elsasser@arm.com * @{*/ 17112706Swendy.elsasser@arm.com /** This request id is used for writeback requests by the caches */ 17212706Swendy.elsasser@arm.com static const MasterID wbMasterId = 0; 17312706Swendy.elsasser@arm.com /** This request id is used for functional requests that don't come from a 17412706Swendy.elsasser@arm.com * particular device 17512706Swendy.elsasser@arm.com */ 17612706Swendy.elsasser@arm.com static const MasterID funcMasterId = 1; 17710394Swendy.elsasser@arm.com /** This request id is used for message signaled interrupts */ 17810561SOmar.Naji@arm.com static const MasterID intMasterId = 2; 17910561SOmar.Naji@arm.com /** Invalid request id for assertion checking only. It is invalid behavior 18010394Swendy.elsasser@arm.com * to ever send this id as part of a request. 18110394Swendy.elsasser@arm.com * @todo C++1x replace with numeric_limits when constexpr is added */ 18210394Swendy.elsasser@arm.com static const MasterID invldMasterId = std::numeric_limits<MasterID>::max(); 18310394Swendy.elsasser@arm.com /** @} */ 18410394Swendy.elsasser@arm.com 18510394Swendy.elsasser@arm.com /** Invalid or unknown Pid. Possible when operating system is not present 1869243SN/A * or has not assigned a pid yet */ 1879243SN/A static const uint32_t invldPid = std::numeric_limits<uint32_t>::max(); 1889243SN/A 18910146Sandreas.hansson@arm.com private: 19010140SN/A typedef uint8_t PrivateFlagsType; 19112969SMatteo.Andreozzi@arm.com typedef ::Flags<PrivateFlagsType> PrivateFlags; 19210466Sandreas.hansson@arm.com 19310466Sandreas.hansson@arm.com /** Whether or not the size is valid. */ 19410146Sandreas.hansson@arm.com static const PrivateFlagsType VALID_SIZE = 0x00000001; 19510140SN/A /** Whether or not paddr is valid (has been written yet). */ 19610140SN/A static const PrivateFlagsType VALID_PADDR = 0x00000002; 19710140SN/A /** Whether or not the vaddr & asid are valid. */ 19810646Sandreas.hansson@arm.com static const PrivateFlagsType VALID_VADDR = 0x00000004; 19910646Sandreas.hansson@arm.com /** Whether or not the pc is valid. */ 20010646Sandreas.hansson@arm.com static const PrivateFlagsType VALID_PC = 0x00000010; 20110646Sandreas.hansson@arm.com /** Whether or not the context ID is valid. */ 20210646Sandreas.hansson@arm.com static const PrivateFlagsType VALID_CONTEXT_ID = 0x00000020; 20310646Sandreas.hansson@arm.com static const PrivateFlagsType VALID_THREAD_ID = 0x00000040; 20410646Sandreas.hansson@arm.com /** Whether or not the sc result is valid. */ 20510646Sandreas.hansson@arm.com static const PrivateFlagsType VALID_EXTRA_DATA = 0x00000080; 20610646Sandreas.hansson@arm.com 20710646Sandreas.hansson@arm.com /** These flags are *not* cleared when a Request object is reused 20810646Sandreas.hansson@arm.com (assigned a new address). */ 20910646Sandreas.hansson@arm.com static const PrivateFlagsType STICKY_PRIVATE_FLAGS = 21010646Sandreas.hansson@arm.com VALID_CONTEXT_ID | VALID_THREAD_ID; 21110646Sandreas.hansson@arm.com 21210646Sandreas.hansson@arm.com private: 21310646Sandreas.hansson@arm.com 21410646Sandreas.hansson@arm.com /** 21510646Sandreas.hansson@arm.com * Set up a physical (e.g. device) request in a previously 21610646Sandreas.hansson@arm.com * allocated Request object. 21710646Sandreas.hansson@arm.com */ 21810646Sandreas.hansson@arm.com void 21910646Sandreas.hansson@arm.com setPhys(Addr paddr, unsigned size, Flags flags, MasterID mid, Tick time) 22010646Sandreas.hansson@arm.com { 22110646Sandreas.hansson@arm.com assert(size >= 0); 22210646Sandreas.hansson@arm.com _paddr = paddr; 22310646Sandreas.hansson@arm.com _size = size; 22410646Sandreas.hansson@arm.com _time = time; 22510646Sandreas.hansson@arm.com _masterId = mid; 22610646Sandreas.hansson@arm.com _flags.clear(~STICKY_FLAGS); 22710646Sandreas.hansson@arm.com _flags.set(flags); 22810646Sandreas.hansson@arm.com privateFlags.clear(~STICKY_PRIVATE_FLAGS); 22910646Sandreas.hansson@arm.com privateFlags.set(VALID_PADDR|VALID_SIZE); 23010646Sandreas.hansson@arm.com depth = 0; 23110646Sandreas.hansson@arm.com accessDelta = 0; 23210646Sandreas.hansson@arm.com //translateDelta = 0; 23310646Sandreas.hansson@arm.com } 23410646Sandreas.hansson@arm.com 23510646Sandreas.hansson@arm.com /** 23610646Sandreas.hansson@arm.com * The physical address of the request. Valid only if validPaddr 23710646Sandreas.hansson@arm.com * is set. 23810140SN/A */ 23910140SN/A Addr _paddr; 24010140SN/A 24110146Sandreas.hansson@arm.com /** 2429243SN/A * The size of the request. This field must be set when vaddr or 24310619Sandreas.hansson@arm.com * paddr is written via setVirt() or setPhys(), so it is always 24410619Sandreas.hansson@arm.com * valid as long as one of the address fields is valid. 24510618SOmar.Naji@arm.com */ 24610619Sandreas.hansson@arm.com unsigned _size; 24710619Sandreas.hansson@arm.com 24810619Sandreas.hansson@arm.com /** The requestor ID which is unique in the system for all ports 24910619Sandreas.hansson@arm.com * that are capable of issuing a transaction 25010619Sandreas.hansson@arm.com */ 25110619Sandreas.hansson@arm.com MasterID _masterId; 25210619Sandreas.hansson@arm.com 25310619Sandreas.hansson@arm.com /** Flag structure for the request. */ 25410619Sandreas.hansson@arm.com Flags _flags; 25510619Sandreas.hansson@arm.com 25610619Sandreas.hansson@arm.com /** Private flags for field validity checking. */ 25710619Sandreas.hansson@arm.com PrivateFlags privateFlags; 25810619Sandreas.hansson@arm.com 25910619Sandreas.hansson@arm.com /** 26012706Swendy.elsasser@arm.com * The time this request was started. Used to calculate 26110618SOmar.Naji@arm.com * latencies. This field is set to curTick() any time paddr or vaddr 2629243SN/A * is written. 2639243SN/A */ 2649243SN/A Tick _time; 26510146Sandreas.hansson@arm.com 2669243SN/A /** 2679243SN/A * The task id associated with this request 2689243SN/A */ 26911334Sandreas.hansson@arm.com uint32_t _taskId; 27011334Sandreas.hansson@arm.com 27111334Sandreas.hansson@arm.com /** The address space ID. */ 2729243SN/A int _asid; 2739243SN/A 2749243SN/A /** The virtual address of the request. */ 2759243SN/A Addr _vaddr; 27611334Sandreas.hansson@arm.com 2779243SN/A /** 2789243SN/A * Extra data for the request, such as the return value of 2799243SN/A * store conditional or the compare value for a CAS. */ 2809243SN/A uint64_t _extraData; 2819243SN/A 2829243SN/A /** The context ID (for statistics, typically). */ 2839243SN/A int _contextId; 2849243SN/A /** The thread ID (id within this CPU) */ 28510146Sandreas.hansson@arm.com ThreadID _threadId; 2869243SN/A 2879831SN/A /** program counter of initiating access; for tracing/debugging */ 28812969SMatteo.Andreozzi@arm.com Addr _pc; 2899831SN/A 2909243SN/A public: 29112969SMatteo.Andreozzi@arm.com 29212969SMatteo.Andreozzi@arm.com /** 2939243SN/A * Minimal constructor. No fields are initialized. (Note that 2949243SN/A * _flags and privateFlags are cleared by Flags default 2959243SN/A * constructor.) 29610146Sandreas.hansson@arm.com */ 2979243SN/A Request() 2989831SN/A : _paddr(0), _size(0), _masterId(invldMasterId), _time(0), 29912969SMatteo.Andreozzi@arm.com _taskId(ContextSwitchTaskId::Unknown), _asid(0), _vaddr(0), 30012969SMatteo.Andreozzi@arm.com _extraData(0), _contextId(0), _threadId(0), _pc(0), 30112969SMatteo.Andreozzi@arm.com translateDelta(0), accessDelta(0), depth(0) 30212969SMatteo.Andreozzi@arm.com {} 3039243SN/A 3049243SN/A /** 30510146Sandreas.hansson@arm.com * Constructor for physical (e.g. device) requests. Initializes 30613857Sodanrc@yahoo.com.br * just physical address, size, flags, and timestamp (to curTick()). 30713857Sodanrc@yahoo.com.br * These fields are adequate to perform a request. 3089243SN/A */ 3099669SN/A Request(Addr paddr, unsigned size, Flags flags, MasterID mid) 31010136SN/A : _paddr(0), _size(0), _masterId(invldMasterId), _time(0), 31110136SN/A _taskId(ContextSwitchTaskId::Unknown), _asid(0), _vaddr(0), 3129243SN/A _extraData(0), _contextId(0), _threadId(0), _pc(0), 3139967SN/A translateDelta(0), accessDelta(0), depth(0) 31410245Sandreas.hansson@arm.com { 31510245Sandreas.hansson@arm.com setPhys(paddr, size, flags, mid, curTick()); 31610245Sandreas.hansson@arm.com } 3179243SN/A 31810286Sandreas.hansson@arm.com Request(Addr paddr, unsigned size, Flags flags, MasterID mid, Tick time) 31910286Sandreas.hansson@arm.com : _paddr(0), _size(0), _masterId(invldMasterId), _time(0), 3209831SN/A _taskId(ContextSwitchTaskId::Unknown), _asid(0), _vaddr(0), 3219243SN/A _extraData(0), _contextId(0), _threadId(0), _pc(0), 3229491SN/A translateDelta(0), accessDelta(0), depth(0) 3239831SN/A { 32410136SN/A setPhys(paddr, size, flags, mid, time); 3259491SN/A } 3269491SN/A 3279831SN/A Request(Addr paddr, unsigned size, Flags flags, MasterID mid, Tick time, 3289243SN/A Addr pc) 3299669SN/A : _paddr(0), _size(0), _masterId(invldMasterId), _time(0), 3309566SN/A _taskId(ContextSwitchTaskId::Unknown), _asid(0), _vaddr(0), 3319566SN/A _extraData(0), _contextId(0), _threadId(0), _pc(0), 3329669SN/A translateDelta(0), accessDelta(0), depth(0) 3339669SN/A { 3349669SN/A setPhys(paddr, size, flags, mid, time); 3359669SN/A privateFlags.set(VALID_PC); 3369669SN/A _pc = pc; 3379669SN/A } 3389669SN/A 3399669SN/A Request(int asid, Addr vaddr, unsigned size, Flags flags, MasterID mid, 3409669SN/A Addr pc, int cid, ThreadID tid) 3419669SN/A : _paddr(0), _size(0), _masterId(invldMasterId), _time(0), 34211189Sandreas.hansson@arm.com _taskId(ContextSwitchTaskId::Unknown), _asid(0), _vaddr(0), 3439669SN/A _extraData(0), _contextId(0), _threadId(0), _pc(0), 34410136SN/A translateDelta(0), accessDelta(0), depth(0) 34510286Sandreas.hansson@arm.com { 34610286Sandreas.hansson@arm.com setVirt(asid, vaddr, size, flags, mid, pc); 34710286Sandreas.hansson@arm.com setThreadContext(cid, tid); 3489669SN/A } 3499669SN/A 3509669SN/A ~Request() {} 35110286Sandreas.hansson@arm.com 35210286Sandreas.hansson@arm.com /** 3539669SN/A * Set up CPU and thread numbers. 3549669SN/A */ 3559491SN/A void 3569243SN/A setThreadContext(int context_id, ThreadID tid) 3579243SN/A { 3589243SN/A _contextId = context_id; 3599491SN/A _threadId = tid; 3609491SN/A privateFlags.set(VALID_CONTEXT_ID|VALID_THREAD_ID); 3619243SN/A } 3629243SN/A 3639243SN/A /** 36411189Sandreas.hansson@arm.com * Set up a virtual (e.g., CPU) request in a previously 3659243SN/A * allocated Request object. 36610136SN/A */ 3679491SN/A void 3689491SN/A setVirt(int asid, Addr vaddr, unsigned size, Flags flags, MasterID mid, 3699491SN/A Addr pc) 37010286Sandreas.hansson@arm.com { 37110286Sandreas.hansson@arm.com _asid = asid; 37210286Sandreas.hansson@arm.com _vaddr = vaddr; 3739566SN/A _size = size; 3749566SN/A _masterId = mid; 3759566SN/A _pc = pc; 3769566SN/A _time = curTick(); 3779566SN/A 3789491SN/A _flags.clear(~STICKY_FLAGS); 3799491SN/A _flags.set(flags); 3809243SN/A privateFlags.clear(~STICKY_PRIVATE_FLAGS); 3819243SN/A privateFlags.set(VALID_VADDR|VALID_SIZE|VALID_PC); 3829243SN/A depth = 0; 3839491SN/A accessDelta = 0; 3849243SN/A translateDelta = 0; 3859243SN/A } 3869243SN/A 38710286Sandreas.hansson@arm.com /** 38810286Sandreas.hansson@arm.com * Set just the physical address. This usually used to record the 3899243SN/A * result of a translation. However, when using virtualized CPUs 39011189Sandreas.hansson@arm.com * setPhys() is sometimes called to finalize a physical address 3919243SN/A * without a virtual address, so we can't check if the virtual 3929243SN/A * address is valid. 3939243SN/A */ 3949243SN/A void 3959243SN/A setPaddr(Addr paddr) 3969243SN/A { 3979243SN/A _paddr = paddr; 39810245Sandreas.hansson@arm.com privateFlags.set(VALID_PADDR); 3999243SN/A } 4009243SN/A 4019831SN/A /** 4029243SN/A * Generate two requests as if this request had been split into two 4039243SN/A * pieces. The original request can't have been translated already. 4049567SN/A */ 4059567SN/A void splitOnVaddr(Addr split_addr, RequestPtr &req1, RequestPtr &req2) 4069967SN/A { 4079967SN/A assert(privateFlags.isSet(VALID_VADDR)); 40810618SOmar.Naji@arm.com assert(privateFlags.noneSet(VALID_PADDR)); 4099243SN/A assert(split_addr > _vaddr && split_addr < _vaddr + _size); 4109243SN/A req1 = new Request(*this); 4119243SN/A req2 = new Request(*this); 41210146Sandreas.hansson@arm.com req1->_size = split_addr - _vaddr; 4139243SN/A req2->_vaddr = split_addr; 4149243SN/A req2->_size = _size - req1->_size; 4159243SN/A } 4169243SN/A 4179243SN/A /** 4189831SN/A * Accessor for paddr. 4199831SN/A */ 4209831SN/A bool 4219831SN/A hasPaddr() const 4229831SN/A { 4239831SN/A return privateFlags.isSet(VALID_PADDR); 4249831SN/A } 4259831SN/A 4269243SN/A Addr 4279831SN/A getPaddr() const 4289831SN/A { 4299831SN/A assert(privateFlags.isSet(VALID_PADDR)); 4309831SN/A return _paddr; 4319831SN/A } 4329831SN/A 4339831SN/A /** 43412969SMatteo.Andreozzi@arm.com * Time for the TLB/table walker to successfully translate this request. 4359243SN/A */ 4369831SN/A Tick translateDelta; 4379831SN/A 4389831SN/A /** 43910889Sandreas.hansson@arm.com * Access latency to complete this memory transaction not including 44010889Sandreas.hansson@arm.com * translation time. 44110889Sandreas.hansson@arm.com */ 44210889Sandreas.hansson@arm.com Tick accessDelta; 44312969SMatteo.Andreozzi@arm.com 44412969SMatteo.Andreozzi@arm.com /** 44512969SMatteo.Andreozzi@arm.com * Level of the cache hierachy where this request was responded to 44612969SMatteo.Andreozzi@arm.com * (e.g. 0 = L1; 1 = L2). 44712969SMatteo.Andreozzi@arm.com */ 44812969SMatteo.Andreozzi@arm.com mutable int depth; 44912969SMatteo.Andreozzi@arm.com 45012969SMatteo.Andreozzi@arm.com /** 45112969SMatteo.Andreozzi@arm.com * Accessor for size. 45212969SMatteo.Andreozzi@arm.com */ 45312969SMatteo.Andreozzi@arm.com bool 45412969SMatteo.Andreozzi@arm.com hasSize() const 45512969SMatteo.Andreozzi@arm.com { 45612969SMatteo.Andreozzi@arm.com return privateFlags.isSet(VALID_SIZE); 45712969SMatteo.Andreozzi@arm.com } 45812969SMatteo.Andreozzi@arm.com 45912969SMatteo.Andreozzi@arm.com unsigned 46010889Sandreas.hansson@arm.com getSize() const 4619831SN/A { 4629243SN/A assert(privateFlags.isSet(VALID_SIZE)); 4639831SN/A return _size; 4649831SN/A } 4659831SN/A 4669831SN/A /** Accessor for time. */ 4679831SN/A Tick 4689831SN/A time() const 4699831SN/A { 4709831SN/A assert(privateFlags.isSet(VALID_PADDR|VALID_VADDR)); 4719831SN/A return _time; 4729831SN/A } 4739831SN/A 4749831SN/A /** Accessor for flags. */ 4759966SN/A Flags 4769831SN/A getFlags() 4779831SN/A { 4789831SN/A assert(privateFlags.isSet(VALID_PADDR|VALID_VADDR)); 47912969SMatteo.Andreozzi@arm.com return _flags; 4809831SN/A } 4819831SN/A 4829831SN/A /** Note that unlike other accessors, this function sets *specific 48312969SMatteo.Andreozzi@arm.com flags* (ORs them in); it does not assign its argument to the 48412969SMatteo.Andreozzi@arm.com _flags field. Thus this method should rightly be called 48511678Swendy.elsasser@arm.com setFlags() and not just flags(). */ 48611678Swendy.elsasser@arm.com void 48712969SMatteo.Andreozzi@arm.com setFlags(Flags flags) 48812969SMatteo.Andreozzi@arm.com { 48912969SMatteo.Andreozzi@arm.com assert(privateFlags.isSet(VALID_PADDR|VALID_VADDR)); 49012969SMatteo.Andreozzi@arm.com _flags.set(flags); 4919831SN/A } 49212969SMatteo.Andreozzi@arm.com 4939831SN/A /** Accessor function for vaddr.*/ 4949831SN/A bool 4959831SN/A hasVaddr() const 4969831SN/A { 4979243SN/A return privateFlags.isSet(VALID_VADDR); 4989243SN/A } 4999831SN/A 5009831SN/A Addr 5019831SN/A getVaddr() const 5029831SN/A { 5039831SN/A assert(privateFlags.isSet(VALID_VADDR)); 5049243SN/A return _vaddr; 5059831SN/A } 5069831SN/A 5079831SN/A /** Accesssor for the requestor id. */ 5089243SN/A MasterID 50910206Sandreas.hansson@arm.com masterId() const 51010206Sandreas.hansson@arm.com { 51110206Sandreas.hansson@arm.com return _masterId; 5129567SN/A } 5139567SN/A 5149243SN/A uint32_t 5159243SN/A taskId() const 5169243SN/A { 5179243SN/A return _taskId; 51810146Sandreas.hansson@arm.com } 5199243SN/A 5209243SN/A void 5219243SN/A taskId(uint32_t id) { 5229243SN/A _taskId = id; 5239243SN/A } 5249831SN/A 5259831SN/A /** Accessor function for asid.*/ 5269831SN/A int 5279831SN/A getAsid() const 5289831SN/A { 5299831SN/A assert(privateFlags.isSet(VALID_VADDR)); 5309831SN/A return _asid; 5319831SN/A } 53212969SMatteo.Andreozzi@arm.com 5339243SN/A /** Accessor function for asid.*/ 5349832SN/A void 53510889Sandreas.hansson@arm.com setAsid(int asid) 53610889Sandreas.hansson@arm.com { 53710889Sandreas.hansson@arm.com _asid = asid; 5389243SN/A } 5399832SN/A 5409832SN/A /** Accessor function for architecture-specific flags.*/ 5419832SN/A ArchFlagsType 5429966SN/A getArchFlags() const 5439243SN/A { 54412969SMatteo.Andreozzi@arm.com assert(privateFlags.isSet(VALID_PADDR|VALID_VADDR)); 54512969SMatteo.Andreozzi@arm.com return _flags & ARCH_BITS; 5469243SN/A } 5479832SN/A 5489831SN/A /** Accessor function to check if sc result is valid. */ 54912969SMatteo.Andreozzi@arm.com bool 55010889Sandreas.hansson@arm.com extraDataValid() const 55112969SMatteo.Andreozzi@arm.com { 55212969SMatteo.Andreozzi@arm.com return privateFlags.isSet(VALID_EXTRA_DATA); 55312969SMatteo.Andreozzi@arm.com } 55412969SMatteo.Andreozzi@arm.com 55512969SMatteo.Andreozzi@arm.com /** Accessor function for store conditional return value.*/ 55612969SMatteo.Andreozzi@arm.com uint64_t 5579831SN/A getExtraData() const 5589832SN/A { 55912969SMatteo.Andreozzi@arm.com assert(privateFlags.isSet(VALID_EXTRA_DATA)); 56011678Swendy.elsasser@arm.com return _extraData; 56111678Swendy.elsasser@arm.com } 56211678Swendy.elsasser@arm.com 5639977SN/A /** Accessor function for store conditional return value.*/ 56410889Sandreas.hansson@arm.com void 56510889Sandreas.hansson@arm.com setExtraData(uint64_t extraData) 5669977SN/A { 5679977SN/A _extraData = extraData; 5689977SN/A privateFlags.set(VALID_EXTRA_DATA); 5699832SN/A } 5709832SN/A 5719831SN/A bool 5729831SN/A hasContextId() const 5739831SN/A { 5749243SN/A return privateFlags.isSet(VALID_CONTEXT_ID); 5759243SN/A } 5769243SN/A 5779243SN/A /** Accessor function for context ID.*/ 5789831SN/A int 5799831SN/A contextId() const 5809726SN/A { 5819243SN/A assert(privateFlags.isSet(VALID_CONTEXT_ID)); 58210206Sandreas.hansson@arm.com return _contextId; 58310206Sandreas.hansson@arm.com } 58410206Sandreas.hansson@arm.com 58510206Sandreas.hansson@arm.com /** Accessor function for thread ID. */ 58610206Sandreas.hansson@arm.com ThreadID 5879243SN/A threadId() const 5889243SN/A { 5899243SN/A assert(privateFlags.isSet(VALID_THREAD_ID)); 5909243SN/A return _threadId; 59112969SMatteo.Andreozzi@arm.com } 59212969SMatteo.Andreozzi@arm.com 59312969SMatteo.Andreozzi@arm.com void 5949243SN/A setPC(Addr pc) 59512969SMatteo.Andreozzi@arm.com { 59612969SMatteo.Andreozzi@arm.com privateFlags.set(VALID_PC); 59712969SMatteo.Andreozzi@arm.com _pc = pc; 59812969SMatteo.Andreozzi@arm.com } 5999243SN/A 60012969SMatteo.Andreozzi@arm.com bool 6019243SN/A hasPC() const 60212969SMatteo.Andreozzi@arm.com { 60312969SMatteo.Andreozzi@arm.com return privateFlags.isSet(VALID_PC); 6049243SN/A } 60512969SMatteo.Andreozzi@arm.com 6069243SN/A /** Accessor function for pc.*/ 60712969SMatteo.Andreozzi@arm.com Addr 60812969SMatteo.Andreozzi@arm.com getPC() const 60912969SMatteo.Andreozzi@arm.com { 61012969SMatteo.Andreozzi@arm.com assert(privateFlags.isSet(VALID_PC)); 6119243SN/A return _pc; 61212969SMatteo.Andreozzi@arm.com } 6139243SN/A 6149243SN/A /** 6159243SN/A * Increment/Get the depth at which this request is responded to. 61610146Sandreas.hansson@arm.com * This currently happens when the request misses in any cache level. 6179243SN/A */ 6189243SN/A void incAccessDepth() const { depth++; } 6199567SN/A int getAccessDepth() const { return depth; } 6209831SN/A 6219243SN/A /** 62211334Sandreas.hansson@arm.com * Set/Get the time taken for this request to be successfully translated. 62311334Sandreas.hansson@arm.com */ 62411334Sandreas.hansson@arm.com void setTranslateLatency() { translateDelta = curTick() - _time; } 62511334Sandreas.hansson@arm.com Tick getTranslateLatency() const { return translateDelta; } 62611334Sandreas.hansson@arm.com 6279243SN/A /** 6289243SN/A * Set/Get the time taken to complete this request's access, not including 6299243SN/A * the time to successfully translate the request. 6309243SN/A */ 6319243SN/A void setAccessLatency() { accessDelta = curTick() - _time - translateDelta; } 6329243SN/A Tick getAccessLatency() const { return accessDelta; } 6339243SN/A 6349831SN/A /** Accessor functions for flags. Note that these are for testing 6359831SN/A only; setting flags should be done via setFlags(). */ 6369831SN/A bool isUncacheable() const { return _flags.isSet(UNCACHEABLE); } 6379831SN/A bool isStrictlyOrdered() const { return _flags.isSet(STRICT_ORDER); } 6389831SN/A bool isInstFetch() const { return _flags.isSet(INST_FETCH); } 6399243SN/A bool isPrefetch() const { return _flags.isSet(PREFETCH); } 6409831SN/A bool isLLSC() const { return _flags.isSet(LLSC); } 6419831SN/A bool isPriv() const { return _flags.isSet(PRIVILEGED); } 6429243SN/A bool isLockedRMW() const { return _flags.isSet(LOCKED_RMW); } 64312969SMatteo.Andreozzi@arm.com bool isSwap() const { return _flags.isSet(MEM_SWAP|MEM_SWAP_COND); } 64412969SMatteo.Andreozzi@arm.com bool isCondSwap() const { return _flags.isSet(MEM_SWAP_COND); } 64512969SMatteo.Andreozzi@arm.com bool isMmappedIpr() const { return _flags.isSet(MMAPPED_IPR); } 6469243SN/A bool isClearLL() const { return _flags.isSet(CLEAR_LL); } 64713834Sjason@lowepower.com bool isSecure() const { return _flags.isSet(SECURE); } 64813834Sjason@lowepower.com bool isPTWalk() const { return _flags.isSet(PT_WALK); } 64913834Sjason@lowepower.com}; 65013834Sjason@lowepower.com 65113834Sjason@lowepower.com#endif // __MEM_REQUEST_HH__ 65213834Sjason@lowepower.com