physical.hh revision 6107
112641Sgiacomo.travaglini@arm.com/* 212641Sgiacomo.travaglini@arm.com * Copyright (c) 2001-2005 The Regents of The University of Michigan 312641Sgiacomo.travaglini@arm.com * All rights reserved. 412641Sgiacomo.travaglini@arm.com * 512641Sgiacomo.travaglini@arm.com * Redistribution and use in source and binary forms, with or without 612641Sgiacomo.travaglini@arm.com * modification, are permitted provided that the following conditions are 712641Sgiacomo.travaglini@arm.com * met: redistributions of source code must retain the above copyright 812641Sgiacomo.travaglini@arm.com * notice, this list of conditions and the following disclaimer; 912641Sgiacomo.travaglini@arm.com * redistributions in binary form must reproduce the above copyright 1012641Sgiacomo.travaglini@arm.com * notice, this list of conditions and the following disclaimer in the 1112641Sgiacomo.travaglini@arm.com * documentation and/or other materials provided with the distribution; 1212641Sgiacomo.travaglini@arm.com * neither the name of the copyright holders nor the names of its 1312641Sgiacomo.travaglini@arm.com * contributors may be used to endorse or promote products derived from 1412641Sgiacomo.travaglini@arm.com * this software without specific prior written permission. 1512641Sgiacomo.travaglini@arm.com * 1612641Sgiacomo.travaglini@arm.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1712641Sgiacomo.travaglini@arm.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1812641Sgiacomo.travaglini@arm.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 1912641Sgiacomo.travaglini@arm.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2012641Sgiacomo.travaglini@arm.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2112641Sgiacomo.travaglini@arm.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2212641Sgiacomo.travaglini@arm.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2312641Sgiacomo.travaglini@arm.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2412641Sgiacomo.travaglini@arm.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2512641Sgiacomo.travaglini@arm.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2612641Sgiacomo.travaglini@arm.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2712641Sgiacomo.travaglini@arm.com * 2812641Sgiacomo.travaglini@arm.com * Authors: Ron Dreslinski 2912641Sgiacomo.travaglini@arm.com */ 3012641Sgiacomo.travaglini@arm.com 3112641Sgiacomo.travaglini@arm.com/* @file 3212641Sgiacomo.travaglini@arm.com */ 3312641Sgiacomo.travaglini@arm.com 3412641Sgiacomo.travaglini@arm.com#ifndef __PHYSICAL_MEMORY_HH__ 3512641Sgiacomo.travaglini@arm.com#define __PHYSICAL_MEMORY_HH__ 3612641Sgiacomo.travaglini@arm.com 3712641Sgiacomo.travaglini@arm.com#include <map> 3812641Sgiacomo.travaglini@arm.com#include <string> 3912641Sgiacomo.travaglini@arm.com 4012641Sgiacomo.travaglini@arm.com#include "base/range.hh" 4112641Sgiacomo.travaglini@arm.com#include "mem/mem_object.hh" 4212641Sgiacomo.travaglini@arm.com#include "mem/packet.hh" 4312641Sgiacomo.travaglini@arm.com#include "mem/tport.hh" 4412641Sgiacomo.travaglini@arm.com#include "params/PhysicalMemory.hh" 4512641Sgiacomo.travaglini@arm.com#include "sim/eventq.hh" 4612641Sgiacomo.travaglini@arm.com 4712641Sgiacomo.travaglini@arm.com// 4812641Sgiacomo.travaglini@arm.com// Functional model for a contiguous block of physical memory. (i.e. RAM) 4912641Sgiacomo.travaglini@arm.com// 5012641Sgiacomo.travaglini@arm.comclass PhysicalMemory : public MemObject 5112641Sgiacomo.travaglini@arm.com{ 5212641Sgiacomo.travaglini@arm.com protected: 5312641Sgiacomo.travaglini@arm.com 5412641Sgiacomo.travaglini@arm.com class MemoryPort : public SimpleTimingPort 5512641Sgiacomo.travaglini@arm.com { 5612641Sgiacomo.travaglini@arm.com PhysicalMemory *memory; 5712641Sgiacomo.travaglini@arm.com 5812641Sgiacomo.travaglini@arm.com public: 5912641Sgiacomo.travaglini@arm.com 6012641Sgiacomo.travaglini@arm.com MemoryPort(const std::string &_name, PhysicalMemory *_memory); 6112641Sgiacomo.travaglini@arm.com 6212641Sgiacomo.travaglini@arm.com protected: 6312641Sgiacomo.travaglini@arm.com 6412641Sgiacomo.travaglini@arm.com virtual Tick recvAtomic(PacketPtr pkt); 6512641Sgiacomo.travaglini@arm.com 6612641Sgiacomo.travaglini@arm.com virtual void recvFunctional(PacketPtr pkt); 6712641Sgiacomo.travaglini@arm.com 6812641Sgiacomo.travaglini@arm.com virtual void recvStatusChange(Status status); 6912641Sgiacomo.travaglini@arm.com 7012641Sgiacomo.travaglini@arm.com virtual void getDeviceAddressRanges(AddrRangeList &resp, 7112641Sgiacomo.travaglini@arm.com bool &snoop); 7212641Sgiacomo.travaglini@arm.com 7312641Sgiacomo.travaglini@arm.com virtual int deviceBlockSize(); 7412641Sgiacomo.travaglini@arm.com }; 7512641Sgiacomo.travaglini@arm.com 7612641Sgiacomo.travaglini@arm.com int numPorts; 7712641Sgiacomo.travaglini@arm.com 7812641Sgiacomo.travaglini@arm.com 7912641Sgiacomo.travaglini@arm.com private: 8012641Sgiacomo.travaglini@arm.com // prevent copying of a MainMemory object 8112641Sgiacomo.travaglini@arm.com PhysicalMemory(const PhysicalMemory &specmem); 8212641Sgiacomo.travaglini@arm.com const PhysicalMemory &operator=(const PhysicalMemory &specmem); 8312641Sgiacomo.travaglini@arm.com 8412641Sgiacomo.travaglini@arm.com protected: 8512641Sgiacomo.travaglini@arm.com 8612641Sgiacomo.travaglini@arm.com class LockedAddr { 8712641Sgiacomo.travaglini@arm.com public: 8813915Sgabeblack@google.com // on alpha, minimum LL/SC granularity is 16 bytes, so lower 8912641Sgiacomo.travaglini@arm.com // bits need to masked off. 9012641Sgiacomo.travaglini@arm.com static const Addr Addr_Mask = 0xf; 9112641Sgiacomo.travaglini@arm.com 9212641Sgiacomo.travaglini@arm.com static Addr mask(Addr paddr) { return (paddr & ~Addr_Mask); } 9312641Sgiacomo.travaglini@arm.com 9412641Sgiacomo.travaglini@arm.com Addr addr; // locked address 9512641Sgiacomo.travaglini@arm.com int contextId; // locking hw context 9612641Sgiacomo.travaglini@arm.com 9712641Sgiacomo.travaglini@arm.com // check for matching execution context 9812641Sgiacomo.travaglini@arm.com bool matchesContext(Request *req) 9912641Sgiacomo.travaglini@arm.com { 10012641Sgiacomo.travaglini@arm.com return (contextId == req->contextId()); 10112641Sgiacomo.travaglini@arm.com } 10212641Sgiacomo.travaglini@arm.com 10312641Sgiacomo.travaglini@arm.com LockedAddr(Request *req) 10413915Sgabeblack@google.com : addr(mask(req->getPaddr())), 10512641Sgiacomo.travaglini@arm.com contextId(req->contextId()) 10612641Sgiacomo.travaglini@arm.com { 10712641Sgiacomo.travaglini@arm.com } 10812641Sgiacomo.travaglini@arm.com }; 10912641Sgiacomo.travaglini@arm.com 11012641Sgiacomo.travaglini@arm.com std::list<LockedAddr> lockedAddrList; 11112641Sgiacomo.travaglini@arm.com 11212641Sgiacomo.travaglini@arm.com // helper function for checkLockedAddrs(): we really want to 11312641Sgiacomo.travaglini@arm.com // inline a quick check for an empty locked addr list (hopefully 11412641Sgiacomo.travaglini@arm.com // the common case), and do the full list search (if necessary) in 11512641Sgiacomo.travaglini@arm.com // this out-of-line function 11612641Sgiacomo.travaglini@arm.com bool checkLockedAddrList(PacketPtr pkt); 11712641Sgiacomo.travaglini@arm.com 11812641Sgiacomo.travaglini@arm.com // Record the address of a load-locked operation so that we can 11912641Sgiacomo.travaglini@arm.com // clear the execution context's lock flag if a matching store is 12012641Sgiacomo.travaglini@arm.com // performed 12112641Sgiacomo.travaglini@arm.com void trackLoadLocked(PacketPtr pkt); 12212641Sgiacomo.travaglini@arm.com 12312641Sgiacomo.travaglini@arm.com // Compare a store address with any locked addresses so we can 12412641Sgiacomo.travaglini@arm.com // clear the lock flag appropriately. Return value set to 'false' 12512641Sgiacomo.travaglini@arm.com // if store operation should be suppressed (because it was a 12613915Sgabeblack@google.com // conditional store and the address was no longer locked by the 12712641Sgiacomo.travaglini@arm.com // requesting execution context), 'true' otherwise. Note that 12812641Sgiacomo.travaglini@arm.com // this method must be called on *all* stores since even 12912641Sgiacomo.travaglini@arm.com // non-conditional stores must clear any matching lock addresses. 13012641Sgiacomo.travaglini@arm.com bool writeOK(PacketPtr pkt) { 13112641Sgiacomo.travaglini@arm.com Request *req = pkt->req; 13212641Sgiacomo.travaglini@arm.com if (lockedAddrList.empty()) { 13312641Sgiacomo.travaglini@arm.com // no locked addrs: nothing to check, store_conditional fails 13412641Sgiacomo.travaglini@arm.com bool isLLSC = pkt->isLLSC(); 13512641Sgiacomo.travaglini@arm.com if (isLLSC) { 13612641Sgiacomo.travaglini@arm.com req->setExtraData(0); 13712641Sgiacomo.travaglini@arm.com } 13813915Sgabeblack@google.com return !isLLSC; // only do write if not an sc 13912641Sgiacomo.travaglini@arm.com } else { 14012641Sgiacomo.travaglini@arm.com // iterate over list... 14112641Sgiacomo.travaglini@arm.com return checkLockedAddrList(pkt); 14212641Sgiacomo.travaglini@arm.com } 14312641Sgiacomo.travaglini@arm.com } 14412641Sgiacomo.travaglini@arm.com 145 uint8_t *pmemAddr; 146 int pagePtr; 147 Tick lat; 148 Tick lat_var; 149 std::vector<MemoryPort*> ports; 150 typedef std::vector<MemoryPort*>::iterator PortIterator; 151 152 uint64_t cachedSize; 153 uint64_t cachedStart; 154 public: 155 Addr new_page(); 156 uint64_t size() { return cachedSize; } 157 uint64_t start() { return cachedStart; } 158 159 public: 160 typedef PhysicalMemoryParams Params; 161 PhysicalMemory(const Params *p); 162 virtual ~PhysicalMemory(); 163 164 const Params * 165 params() const 166 { 167 return dynamic_cast<const Params *>(_params); 168 } 169 170 public: 171 int deviceBlockSize(); 172 void getAddressRanges(AddrRangeList &resp, bool &snoop); 173 virtual Port *getPort(const std::string &if_name, int idx = -1); 174 void virtual init(); 175 unsigned int drain(Event *de); 176 177 protected: 178 Tick doAtomicAccess(PacketPtr pkt); 179 void doFunctionalAccess(PacketPtr pkt); 180 virtual Tick calculateLatency(PacketPtr pkt); 181 void recvStatusChange(Port::Status status); 182 183 public: 184 virtual void serialize(std::ostream &os); 185 virtual void unserialize(Checkpoint *cp, const std::string §ion); 186 187}; 188 189#endif //__PHYSICAL_MEMORY_HH__ 190