physical.hh revision 10905
12632Sstever@eecs.umich.edu/* 22632Sstever@eecs.umich.edu * Copyright (c) 2012 ARM Limited 32632Sstever@eecs.umich.edu * All rights reserved 42632Sstever@eecs.umich.edu * 52632Sstever@eecs.umich.edu * The license below extends only to copyright in the software and shall 62632Sstever@eecs.umich.edu * not be construed as granting a license to any other intellectual 72632Sstever@eecs.umich.edu * property including but not limited to intellectual property relating 82632Sstever@eecs.umich.edu * to a hardware implementation of the functionality of the software 92632Sstever@eecs.umich.edu * licensed hereunder. You may use the software subject to the license 102632Sstever@eecs.umich.edu * terms below provided that you ensure that this notice is replicated 112632Sstever@eecs.umich.edu * unmodified and in its entirety in all distributions of the software, 122632Sstever@eecs.umich.edu * modified or unmodified, in source code or in binary form. 132632Sstever@eecs.umich.edu * 142632Sstever@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 152632Sstever@eecs.umich.edu * modification, are permitted provided that the following conditions are 162632Sstever@eecs.umich.edu * met: redistributions of source code must retain the above copyright 172632Sstever@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 182632Sstever@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 192632Sstever@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 202632Sstever@eecs.umich.edu * documentation and/or other materials provided with the distribution; 212632Sstever@eecs.umich.edu * neither the name of the copyright holders nor the names of its 222632Sstever@eecs.umich.edu * contributors may be used to endorse or promote products derived from 232632Sstever@eecs.umich.edu * this software without specific prior written permission. 242632Sstever@eecs.umich.edu * 252632Sstever@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 262632Sstever@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 272632Sstever@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 282632Sstever@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 292632Sstever@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 302632Sstever@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 312022SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 322022SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 332022SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 342022SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 352022SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 362469SN/A * 372469SN/A * Authors: Andreas Hansson 382469SN/A */ 392469SN/A 402516SN/A#ifndef __MEM_PHYSICAL_HH__ 412516SN/A#define __MEM_PHYSICAL_HH__ 422944Sgblack@eecs.umich.edu 432482SN/A#include "base/addr_range_map.hh" 443056Sgblack@eecs.umich.edu#include "mem/packet.hh" 452469SN/A 463056Sgblack@eecs.umich.edu/** 473056Sgblack@eecs.umich.edu * Forward declaration to avoid header dependencies. 483056Sgblack@eecs.umich.edu */ 493056Sgblack@eecs.umich.educlass AbstractMemory; 502516SN/A 513056Sgblack@eecs.umich.edu/** 523056Sgblack@eecs.umich.edu * The physical memory encapsulates all memories in the system and 533056Sgblack@eecs.umich.edu * provides basic functionality for accessing those memories without 543056Sgblack@eecs.umich.edu * going through the memory system and interconnect. 553056Sgblack@eecs.umich.edu * 563056Sgblack@eecs.umich.edu * The physical memory is also responsible for providing the host 573056Sgblack@eecs.umich.edu * system backingstore used by the memories in the simulated guest 583056Sgblack@eecs.umich.edu * system. When the system is created, the physical memory allocates 593056Sgblack@eecs.umich.edu * the backing store based on the address ranges that are populated in 603056Sgblack@eecs.umich.edu * the system, and does so independent of how those map to actual 613056Sgblack@eecs.umich.edu * memory controllers. Thus, the physical memory completely abstracts 623056Sgblack@eecs.umich.edu * the mapping of the backing store of the host system and the address 633056Sgblack@eecs.umich.edu * mapping in the guest system. This enables us to arbitrarily change 643056Sgblack@eecs.umich.edu * the number of memory controllers, and their address mapping, as 653056Sgblack@eecs.umich.edu * long as the ranges stay the same. 663056Sgblack@eecs.umich.edu */ 673056Sgblack@eecs.umich.educlass PhysicalMemory : public Serializable 683056Sgblack@eecs.umich.edu{ 693056Sgblack@eecs.umich.edu 703056Sgblack@eecs.umich.edu private: 713056Sgblack@eecs.umich.edu 723056Sgblack@eecs.umich.edu // Name for debugging 733056Sgblack@eecs.umich.edu std::string _name; 743056Sgblack@eecs.umich.edu 753056Sgblack@eecs.umich.edu // Global address map 763056Sgblack@eecs.umich.edu AddrRangeMap<AbstractMemory*> addrMap; 773056Sgblack@eecs.umich.edu 783056Sgblack@eecs.umich.edu // a mutable cache for the last address map iterator that matched 793056Sgblack@eecs.umich.edu // an address 803056Sgblack@eecs.umich.edu mutable AddrRangeMap<AbstractMemory*>::const_iterator rangeCache; 813056Sgblack@eecs.umich.edu 823056Sgblack@eecs.umich.edu // All address-mapped memories 832482SN/A std::vector<AbstractMemory*> memories; 842944Sgblack@eecs.umich.edu 852944Sgblack@eecs.umich.edu // The total memory size 862944Sgblack@eecs.umich.edu uint64_t size; 872944Sgblack@eecs.umich.edu 882944Sgblack@eecs.umich.edu // Let the user choose if we reserve swap space when calling mmap 892944Sgblack@eecs.umich.edu const bool mmapUsingNoReserve; 902516SN/A 912516SN/A // The physical memory used to provide the memory in the simulated 922516SN/A // system 932516SN/A std::vector<std::pair<AddrRange, uint8_t*>> backingStore; 942482SN/A 952482SN/A // Prevent copying 962591SN/A PhysicalMemory(const PhysicalMemory&); 972516SN/A 982580SN/A // Prevent assignment 992580SN/A PhysicalMemory& operator=(const PhysicalMemory&); 1002482SN/A 1012482SN/A /** 1022591SN/A * Create the memory region providing the backing store for a 1032516SN/A * given address range that corresponds to a set of memories in 1042580SN/A * the simulated system. 1052580SN/A * 1062482SN/A * @param range The address range covered 1072482SN/A * @param memories The memories this range maps to 1082591SN/A */ 1092516SN/A void createBackingStore(AddrRange range, 1102580SN/A const std::vector<AbstractMemory*>& _memories); 1112580SN/A 1122482SN/A public: 1132482SN/A 1142591SN/A /** 1152516SN/A * Create a physical memory object, wrapping a number of memories. 1162580SN/A */ 1172580SN/A PhysicalMemory(const std::string& _name, 1182482SN/A const std::vector<AbstractMemory*>& _memories, 1192482SN/A bool mmap_using_noreserve); 1202591SN/A 1212516SN/A /** 1222580SN/A * Unmap all the backing store we have used. 1232580SN/A */ 1242482SN/A ~PhysicalMemory(); 1252482SN/A 1262591SN/A /** 1272516SN/A * Return the name for debugging and for creation of sections for 1282580SN/A * checkpointing. 1292580SN/A */ 1302482SN/A const std::string name() const { return _name; } 1312469SN/A 1322482SN/A /** 1332516SN/A * Check if a physical address is within a range of a memory that 1343042Sgblack@eecs.umich.edu * is part of the global address map. 1352516SN/A * 1362516SN/A * @param addr A physical address 1372469SN/A * @return Whether the address corresponds to a memory 1382944Sgblack@eecs.umich.edu */ 1392516SN/A bool isMemAddr(Addr addr) const; 1402516SN/A 1412469SN/A /** 1422469SN/A * Get the memory ranges for all memories that are to be reported 1432482SN/A * to the configuration table. The ranges are merged before they 1442482SN/A * are returned such that any interleaved ranges appear as a 1452974Sgblack@eecs.umich.edu * single range. 1462974Sgblack@eecs.umich.edu * 1472974Sgblack@eecs.umich.edu * @return All configuration table memory ranges 1482526SN/A */ 1492974Sgblack@eecs.umich.edu AddrRangeList getConfAddrRanges() const; 1502974Sgblack@eecs.umich.edu 1512974Sgblack@eecs.umich.edu /** 1522646Ssaidi@eecs.umich.edu * Get the total physical memory size. 1532974Sgblack@eecs.umich.edu * 1542469SN/A * @return The sum of all memory sizes 1552516SN/A */ 1562646Ssaidi@eecs.umich.edu uint64_t totalSize() const { return size; } 1572482SN/A 1582469SN/A /** 1592516SN/A * Get the pointers to the backing store for external host 1602646Ssaidi@eecs.umich.edu * access. Note that memory in the guest should be accessed using 1612482SN/A * access() or functionalAccess(). This interface is primarily 1622954Sgblack@eecs.umich.edu * intended for CPU models using hardware virtualization. Note 1632469SN/A * that memories that are null are not present, and that the 1642516SN/A * backing store may also contain memories that are not part of 1652516SN/A * the OS-visible global address map and thus are allowed to 1662482SN/A * overlap. 1672469SN/A * 1682516SN/A * @return Pointers to the memory backing store 1692482SN/A */ 1702482SN/A std::vector<std::pair<AddrRange, uint8_t*>> getBackingStore() const 1712646Ssaidi@eecs.umich.edu { return backingStore; } 1722482SN/A 1732482SN/A /** 1742482SN/A * Perform an untimed memory access and update all the state 1752482SN/A * (e.g. locked addresses) and statistics accordingly. The packet 1762482SN/A * is turned into a response if required. 1772615SN/A * 1782469SN/A * @param pkt Packet performing the access 1792469SN/A */ 1802482SN/A void access(PacketPtr pkt); 1812646Ssaidi@eecs.umich.edu 1822482SN/A /** 1832482SN/A * Perform an untimed memory read or write without changing 1842482SN/A * anything but the memory itself. No stats are affected by this 1852588SN/A * access. In addition to normal accesses this also facilitates 1862482SN/A * print requests. 1872526SN/A * 1882469SN/A * @param pkt Packet performing the access 1892482SN/A */ 1902469SN/A void functionalAccess(PacketPtr pkt); 1912516SN/A 1922469SN/A /** 1932580SN/A * Serialize all the memories in the system. This is independent 1942469SN/A * of the logical memory layout, and the serialization only sees 1952580SN/A * the contigous backing store, independent of how this maps to 1962469SN/A * logical memories in the guest system. 1972526SN/A * 1982482SN/A * @param os stream to serialize to 1992482SN/A */ 2002482SN/A void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE; 2012469SN/A 2022580SN/A /** 2032580SN/A * Serialize a specific store. 2042580SN/A * 2052580SN/A * @param store_id Unique identifier of this backing store 2062580SN/A * @param range The address range of this backing store 2072580SN/A * @param pmem The host pointer to this backing store 2082580SN/A */ 2092526SN/A void serializeStore(CheckpointOut &cp, unsigned int store_id, 2102482SN/A AddrRange range, uint8_t* pmem) const; 2112482SN/A 2122482SN/A /** 2132469SN/A * Unserialize the memories in the system. As with the 2142516SN/A * serialization, this action is independent of how the address 2152646Ssaidi@eecs.umich.edu * ranges are mapped to logical memories in the guest system. 2162469SN/A */ 2172580SN/A void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE; 2182469SN/A 2192580SN/A /** 2202580SN/A * Unserialize a specific backing store, identified by a section. 2212469SN/A */ 2222526SN/A void unserializeStore(CheckpointIn &cp); 2232469SN/A 2242615SN/A}; 2252615SN/A 2262646Ssaidi@eecs.umich.edu#endif //__MEM_PHYSICAL_HH__ 2272526SN/A