physical.hh revision 5275
12391SN/A/*
22391SN/A * Copyright (c) 2001-2005 The Regents of The University of Michigan
32391SN/A * All rights reserved.
42391SN/A *
52391SN/A * Redistribution and use in source and binary forms, with or without
62391SN/A * modification, are permitted provided that the following conditions are
72391SN/A * met: redistributions of source code must retain the above copyright
82391SN/A * notice, this list of conditions and the following disclaimer;
92391SN/A * redistributions in binary form must reproduce the above copyright
102391SN/A * notice, this list of conditions and the following disclaimer in the
112391SN/A * documentation and/or other materials provided with the distribution;
122391SN/A * neither the name of the copyright holders nor the names of its
132391SN/A * contributors may be used to endorse or promote products derived from
142391SN/A * this software without specific prior written permission.
152391SN/A *
162391SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
172391SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
182391SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
192391SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
202391SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
212391SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
222391SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
232391SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
242391SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
252391SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
262391SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
272665Ssaidi@eecs.umich.edu *
282665Ssaidi@eecs.umich.edu * Authors: Ron Dreslinski
292391SN/A */
302391SN/A
312391SN/A/* @file
322391SN/A */
332391SN/A
342391SN/A#ifndef __PHYSICAL_MEMORY_HH__
352391SN/A#define __PHYSICAL_MEMORY_HH__
362391SN/A
374762Snate@binkert.org#include <map>
384762Snate@binkert.org#include <string>
394762Snate@binkert.org
402391SN/A#include "base/range.hh"
412462SN/A#include "mem/mem_object.hh"
422414SN/A#include "mem/packet.hh"
432914Ssaidi@eecs.umich.edu#include "mem/tport.hh"
444762Snate@binkert.org#include "params/PhysicalMemory.hh"
452415SN/A#include "sim/eventq.hh"
462462SN/A
472391SN/A//
482391SN/A// Functional model for a contiguous block of physical memory. (i.e. RAM)
492391SN/A//
502462SN/Aclass PhysicalMemory : public MemObject
512391SN/A{
522914Ssaidi@eecs.umich.edu    class MemoryPort : public SimpleTimingPort
532413SN/A    {
542413SN/A        PhysicalMemory *memory;
552413SN/A
562413SN/A      public:
572413SN/A
582640Sstever@eecs.umich.edu        MemoryPort(const std::string &_name, PhysicalMemory *_memory);
592413SN/A
602413SN/A      protected:
612413SN/A
623349Sbinkertn@umich.edu        virtual Tick recvAtomic(PacketPtr pkt);
632413SN/A
643349Sbinkertn@umich.edu        virtual void recvFunctional(PacketPtr pkt);
652413SN/A
662413SN/A        virtual void recvStatusChange(Status status);
672413SN/A
682521SN/A        virtual void getDeviceAddressRanges(AddrRangeList &resp,
694475Sstever@eecs.umich.edu                                            bool &snoop);
702413SN/A
712413SN/A        virtual int deviceBlockSize();
722413SN/A    };
732413SN/A
742416SN/A    int numPorts;
752416SN/A
762413SN/A
772391SN/A  private:
782391SN/A    // prevent copying of a MainMemory object
792391SN/A    PhysicalMemory(const PhysicalMemory &specmem);
802391SN/A    const PhysicalMemory &operator=(const PhysicalMemory &specmem);
812391SN/A
822391SN/A  protected:
833170Sstever@eecs.umich.edu
843170Sstever@eecs.umich.edu    class LockedAddr {
853170Sstever@eecs.umich.edu      public:
863170Sstever@eecs.umich.edu        // on alpha, minimum LL/SC granularity is 16 bytes, so lower
873170Sstever@eecs.umich.edu        // bits need to masked off.
883170Sstever@eecs.umich.edu        static const Addr Addr_Mask = 0xf;
893170Sstever@eecs.umich.edu
903170Sstever@eecs.umich.edu        static Addr mask(Addr paddr) { return (paddr & ~Addr_Mask); }
913170Sstever@eecs.umich.edu
923170Sstever@eecs.umich.edu        Addr addr; 	// locked address
933170Sstever@eecs.umich.edu        int cpuNum;	// locking CPU
943170Sstever@eecs.umich.edu        int threadNum;	// locking thread ID within CPU
953170Sstever@eecs.umich.edu
963170Sstever@eecs.umich.edu        // check for matching execution context
973170Sstever@eecs.umich.edu        bool matchesContext(Request *req)
983170Sstever@eecs.umich.edu        {
993170Sstever@eecs.umich.edu            return (cpuNum == req->getCpuNum() &&
1003170Sstever@eecs.umich.edu                    threadNum == req->getThreadNum());
1013170Sstever@eecs.umich.edu        }
1023170Sstever@eecs.umich.edu
1033170Sstever@eecs.umich.edu        LockedAddr(Request *req)
1043170Sstever@eecs.umich.edu            : addr(mask(req->getPaddr())),
1053170Sstever@eecs.umich.edu              cpuNum(req->getCpuNum()),
1063170Sstever@eecs.umich.edu              threadNum(req->getThreadNum())
1073170Sstever@eecs.umich.edu        {
1083170Sstever@eecs.umich.edu        }
1093170Sstever@eecs.umich.edu    };
1103170Sstever@eecs.umich.edu
1113170Sstever@eecs.umich.edu    std::list<LockedAddr> lockedAddrList;
1123170Sstever@eecs.umich.edu
1133170Sstever@eecs.umich.edu    // helper function for checkLockedAddrs(): we really want to
1143170Sstever@eecs.umich.edu    // inline a quick check for an empty locked addr list (hopefully
1153170Sstever@eecs.umich.edu    // the common case), and do the full list search (if necessary) in
1163170Sstever@eecs.umich.edu    // this out-of-line function
1174626Sstever@eecs.umich.edu    bool checkLockedAddrList(PacketPtr pkt);
1183170Sstever@eecs.umich.edu
1193170Sstever@eecs.umich.edu    // Record the address of a load-locked operation so that we can
1203170Sstever@eecs.umich.edu    // clear the execution context's lock flag if a matching store is
1213170Sstever@eecs.umich.edu    // performed
1224626Sstever@eecs.umich.edu    void trackLoadLocked(PacketPtr pkt);
1233170Sstever@eecs.umich.edu
1243170Sstever@eecs.umich.edu    // Compare a store address with any locked addresses so we can
1253170Sstever@eecs.umich.edu    // clear the lock flag appropriately.  Return value set to 'false'
1263170Sstever@eecs.umich.edu    // if store operation should be suppressed (because it was a
1273170Sstever@eecs.umich.edu    // conditional store and the address was no longer locked by the
1283170Sstever@eecs.umich.edu    // requesting execution context), 'true' otherwise.  Note that
1293170Sstever@eecs.umich.edu    // this method must be called on *all* stores since even
1303170Sstever@eecs.umich.edu    // non-conditional stores must clear any matching lock addresses.
1314626Sstever@eecs.umich.edu    bool writeOK(PacketPtr pkt) {
1324626Sstever@eecs.umich.edu        Request *req = pkt->req;
1333170Sstever@eecs.umich.edu        if (lockedAddrList.empty()) {
1343170Sstever@eecs.umich.edu            // no locked addrs: nothing to check, store_conditional fails
1354626Sstever@eecs.umich.edu            bool isLocked = pkt->isLocked();
1363170Sstever@eecs.umich.edu            if (isLocked) {
1374040Ssaidi@eecs.umich.edu                req->setExtraData(0);
1383170Sstever@eecs.umich.edu            }
1393170Sstever@eecs.umich.edu            return !isLocked; // only do write if not an sc
1403170Sstever@eecs.umich.edu        } else {
1413170Sstever@eecs.umich.edu            // iterate over list...
1424626Sstever@eecs.umich.edu            return checkLockedAddrList(pkt);
1433170Sstever@eecs.umich.edu        }
1443170Sstever@eecs.umich.edu    }
1453170Sstever@eecs.umich.edu
1463012Ssaidi@eecs.umich.edu    uint8_t *pmemAddr;
1473012Ssaidi@eecs.umich.edu    int pagePtr;
1482565SN/A    Tick lat;
1494467Sstever@eecs.umich.edu    std::vector<MemoryPort*> ports;
1504467Sstever@eecs.umich.edu    typedef std::vector<MemoryPort*>::iterator PortIterator;
1512391SN/A
1525275Ssaidi@eecs.umich.edu    uint64_t cachedSize;
1535275Ssaidi@eecs.umich.edu    uint64_t cachedStart;
1542391SN/A  public:
1552391SN/A    Addr new_page();
1565275Ssaidi@eecs.umich.edu    uint64_t size() { return cachedSize; }
1575275Ssaidi@eecs.umich.edu    uint64_t start() { return cachedStart; }
1582391SN/A
1592391SN/A  public:
1604762Snate@binkert.org    typedef PhysicalMemoryParams Params;
1614762Snate@binkert.org    PhysicalMemory(const Params *p);
1622391SN/A    virtual ~PhysicalMemory();
1632391SN/A
1644762Snate@binkert.org    const Params *
1654762Snate@binkert.org    params() const
1664762Snate@binkert.org    {
1674762Snate@binkert.org        return dynamic_cast<const Params *>(_params);
1684762Snate@binkert.org    }
1694762Snate@binkert.org
1702391SN/A  public:
1712415SN/A    int deviceBlockSize();
1724475Sstever@eecs.umich.edu    void getAddressRanges(AddrRangeList &resp, bool &snoop);
1732738Sstever@eecs.umich.edu    virtual Port *getPort(const std::string &if_name, int idx = -1);
1742541SN/A    void virtual init();
1752914Ssaidi@eecs.umich.edu    unsigned int drain(Event *de);
1762391SN/A
1773012Ssaidi@eecs.umich.edu  protected:
1784626Sstever@eecs.umich.edu    Tick doAtomicAccess(PacketPtr pkt);
1793349Sbinkertn@umich.edu    void doFunctionalAccess(PacketPtr pkt);
1803349Sbinkertn@umich.edu    virtual Tick calculateLatency(PacketPtr pkt);
1812413SN/A    void recvStatusChange(Port::Status status);
1822391SN/A
1832391SN/A  public:
1842391SN/A    virtual void serialize(std::ostream &os);
1852391SN/A    virtual void unserialize(Checkpoint *cp, const std::string &section);
1862497SN/A
1872391SN/A};
1882391SN/A
1892391SN/A#endif //__PHYSICAL_MEMORY_HH__
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