dram_ctrl.hh revision 11676
19243SN/A/* 211675Swendy.elsasser@arm.com * Copyright (c) 2012-2016 ARM Limited 39243SN/A * All rights reserved 49243SN/A * 59243SN/A * The license below extends only to copyright in the software and shall 69243SN/A * not be construed as granting a license to any other intellectual 79243SN/A * property including but not limited to intellectual property relating 89243SN/A * to a hardware implementation of the functionality of the software 99243SN/A * licensed hereunder. You may use the software subject to the license 109243SN/A * terms below provided that you ensure that this notice is replicated 119243SN/A * unmodified and in its entirety in all distributions of the software, 129243SN/A * modified or unmodified, in source code or in binary form. 139243SN/A * 149831SN/A * Copyright (c) 2013 Amin Farmahini-Farahani 159831SN/A * All rights reserved. 169831SN/A * 179243SN/A * Redistribution and use in source and binary forms, with or without 189243SN/A * modification, are permitted provided that the following conditions are 199243SN/A * met: redistributions of source code must retain the above copyright 209243SN/A * notice, this list of conditions and the following disclaimer; 219243SN/A * redistributions in binary form must reproduce the above copyright 229243SN/A * notice, this list of conditions and the following disclaimer in the 239243SN/A * documentation and/or other materials provided with the distribution; 249243SN/A * neither the name of the copyright holders nor the names of its 259243SN/A * contributors may be used to endorse or promote products derived from 269243SN/A * this software without specific prior written permission. 279243SN/A * 289243SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 299243SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 309243SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 319243SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 329243SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 339243SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 349243SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 359243SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 369243SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 379243SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 389243SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 399243SN/A * 409243SN/A * Authors: Andreas Hansson 419243SN/A * Ani Udipi 429967SN/A * Neha Agarwal 4310618SOmar.Naji@arm.com * Omar Naji 4411555Sjungma@eit.uni-kl.de * Matthias Jung 459243SN/A */ 469243SN/A 479243SN/A/** 489243SN/A * @file 4910146Sandreas.hansson@arm.com * DRAMCtrl declaration 509243SN/A */ 519243SN/A 5210146Sandreas.hansson@arm.com#ifndef __MEM_DRAM_CTRL_HH__ 5310146Sandreas.hansson@arm.com#define __MEM_DRAM_CTRL_HH__ 549243SN/A 559488SN/A#include <deque> 5610618SOmar.Naji@arm.com#include <string> 5710889Sandreas.hansson@arm.com#include <unordered_set> 589488SN/A 599243SN/A#include "base/statistics.hh" 609243SN/A#include "enums/AddrMap.hh" 619243SN/A#include "enums/MemSched.hh" 629243SN/A#include "enums/PageManage.hh" 639243SN/A#include "mem/abstract_mem.hh" 649243SN/A#include "mem/qport.hh" 6510146Sandreas.hansson@arm.com#include "params/DRAMCtrl.hh" 669243SN/A#include "sim/eventq.hh" 6710432SOmar.Naji@arm.com#include "mem/drampower.hh" 689243SN/A 699243SN/A/** 7010287Sandreas.hansson@arm.com * The DRAM controller is a single-channel memory controller capturing 7110287Sandreas.hansson@arm.com * the most important timing constraints associated with a 7210287Sandreas.hansson@arm.com * contemporary DRAM. For multi-channel memory systems, the controller 7310287Sandreas.hansson@arm.com * is combined with a crossbar model, with the channel address 7410287Sandreas.hansson@arm.com * interleaving taking part in the crossbar. 759243SN/A * 7610287Sandreas.hansson@arm.com * As a basic design principle, this controller 7710287Sandreas.hansson@arm.com * model is not cycle callable, but instead uses events to: 1) decide 7810287Sandreas.hansson@arm.com * when new decisions can be made, 2) when resources become available, 7910287Sandreas.hansson@arm.com * 3) when things are to be considered done, and 4) when to send 8010287Sandreas.hansson@arm.com * things back. Through these simple principles, the model delivers 8110287Sandreas.hansson@arm.com * high performance, and lots of flexibility, allowing users to 8210287Sandreas.hansson@arm.com * evaluate the system impact of a wide range of memory technologies, 8310287Sandreas.hansson@arm.com * such as DDR3/4, LPDDR2/3/4, WideIO1/2, HBM and HMC. 8410287Sandreas.hansson@arm.com * 8510287Sandreas.hansson@arm.com * For more details, please see Hansson et al, "Simulating DRAM 8610287Sandreas.hansson@arm.com * controllers for future system architecture exploration", 8710287Sandreas.hansson@arm.com * Proc. ISPASS, 2014. If you use this model as part of your research 8810287Sandreas.hansson@arm.com * please cite the paper. 899243SN/A */ 9010146Sandreas.hansson@arm.comclass DRAMCtrl : public AbstractMemory 919243SN/A{ 929243SN/A 939243SN/A private: 949243SN/A 959243SN/A // For now, make use of a queued slave port to avoid dealing with 969243SN/A // flow control for the responses being sent back 979243SN/A class MemoryPort : public QueuedSlavePort 989243SN/A { 999243SN/A 10010713Sandreas.hansson@arm.com RespPacketQueue queue; 10110146Sandreas.hansson@arm.com DRAMCtrl& memory; 1029243SN/A 1039243SN/A public: 1049243SN/A 10510146Sandreas.hansson@arm.com MemoryPort(const std::string& name, DRAMCtrl& _memory); 1069243SN/A 1079243SN/A protected: 1089243SN/A 1099243SN/A Tick recvAtomic(PacketPtr pkt); 1109243SN/A 1119243SN/A void recvFunctional(PacketPtr pkt); 1129243SN/A 1139243SN/A bool recvTimingReq(PacketPtr); 1149243SN/A 1159243SN/A virtual AddrRangeList getAddrRanges() const; 1169243SN/A 1179243SN/A }; 1189243SN/A 1199243SN/A /** 1209243SN/A * Our incoming port, for a multi-ported controller add a crossbar 1219243SN/A * in front of it 1229243SN/A */ 1239243SN/A MemoryPort port; 1249243SN/A 1259243SN/A /** 12610619Sandreas.hansson@arm.com * Remeber if the memory system is in timing mode 12710619Sandreas.hansson@arm.com */ 12810619Sandreas.hansson@arm.com bool isTimingMode; 12910619Sandreas.hansson@arm.com 13010619Sandreas.hansson@arm.com /** 1319243SN/A * Remember if we have to retry a request when available. 1329243SN/A */ 1339243SN/A bool retryRdReq; 1349243SN/A bool retryWrReq; 1359243SN/A 1369243SN/A /** 13710206Sandreas.hansson@arm.com * Bus state used to control the read/write switching and drive 13810206Sandreas.hansson@arm.com * the scheduling of the next request. 1399243SN/A */ 14010206Sandreas.hansson@arm.com enum BusState { 14110206Sandreas.hansson@arm.com READ = 0, 14210206Sandreas.hansson@arm.com READ_TO_WRITE, 14310206Sandreas.hansson@arm.com WRITE, 14410206Sandreas.hansson@arm.com WRITE_TO_READ 14510206Sandreas.hansson@arm.com }; 14610206Sandreas.hansson@arm.com 14710206Sandreas.hansson@arm.com BusState busState; 1489243SN/A 1499243SN/A /** 15011675Swendy.elsasser@arm.com * Simple structure to hold the values needed to keep track of 15111675Swendy.elsasser@arm.com * commands for DRAMPower 15211675Swendy.elsasser@arm.com */ 15311675Swendy.elsasser@arm.com struct Command { 15411675Swendy.elsasser@arm.com Data::MemCommand::cmds type; 15511675Swendy.elsasser@arm.com uint8_t bank; 15611675Swendy.elsasser@arm.com Tick timeStamp; 15711675Swendy.elsasser@arm.com 15811675Swendy.elsasser@arm.com constexpr Command(Data::MemCommand::cmds _type, uint8_t _bank, 15911675Swendy.elsasser@arm.com Tick time_stamp) 16011675Swendy.elsasser@arm.com : type(_type), bank(_bank), timeStamp(time_stamp) 16111675Swendy.elsasser@arm.com { } 16211675Swendy.elsasser@arm.com }; 16311675Swendy.elsasser@arm.com 16411675Swendy.elsasser@arm.com /** 16510210Sandreas.hansson@arm.com * A basic class to track the bank state, i.e. what row is 16610210Sandreas.hansson@arm.com * currently open (if any), when is the bank free to accept a new 16710211Sandreas.hansson@arm.com * column (read/write) command, when can it be precharged, and 16810211Sandreas.hansson@arm.com * when can it be activated. 16910210Sandreas.hansson@arm.com * 17010210Sandreas.hansson@arm.com * The bank also keeps track of how many bytes have been accessed 17110210Sandreas.hansson@arm.com * in the open row since it was opened. 1729243SN/A */ 1739243SN/A class Bank 1749243SN/A { 1759243SN/A 1769243SN/A public: 1779243SN/A 17810207Sandreas.hansson@arm.com static const uint32_t NO_ROW = -1; 1799243SN/A 1809243SN/A uint32_t openRow; 18110246Sandreas.hansson@arm.com uint8_t bank; 18210394Swendy.elsasser@arm.com uint8_t bankgr; 1839243SN/A 18410211Sandreas.hansson@arm.com Tick colAllowedAt; 18510210Sandreas.hansson@arm.com Tick preAllowedAt; 1869969SN/A Tick actAllowedAt; 1879243SN/A 18810141SN/A uint32_t rowAccesses; 1899727SN/A uint32_t bytesAccessed; 1909727SN/A 1919727SN/A Bank() : 19210618SOmar.Naji@arm.com openRow(NO_ROW), bank(0), bankgr(0), 19310246Sandreas.hansson@arm.com colAllowedAt(0), preAllowedAt(0), actAllowedAt(0), 19410141SN/A rowAccesses(0), bytesAccessed(0) 1959243SN/A { } 1969243SN/A }; 1979243SN/A 19810618SOmar.Naji@arm.com 19910618SOmar.Naji@arm.com /** 20010618SOmar.Naji@arm.com * Rank class includes a vector of banks. Refresh and Power state 20110618SOmar.Naji@arm.com * machines are defined per rank. Events required to change the 20210618SOmar.Naji@arm.com * state of the refresh and power state machine are scheduled per 20310618SOmar.Naji@arm.com * rank. This class allows the implementation of rank-wise refresh 20410618SOmar.Naji@arm.com * and rank-wise power-down. 20510618SOmar.Naji@arm.com */ 20610618SOmar.Naji@arm.com class Rank : public EventManager 20710618SOmar.Naji@arm.com { 20810618SOmar.Naji@arm.com 20910618SOmar.Naji@arm.com private: 21010618SOmar.Naji@arm.com 21110618SOmar.Naji@arm.com /** 21210618SOmar.Naji@arm.com * The power state captures the different operational states of 21310618SOmar.Naji@arm.com * the DRAM and interacts with the bus read/write state machine, 21410618SOmar.Naji@arm.com * and the refresh state machine. In the idle state all banks are 21510618SOmar.Naji@arm.com * precharged. From there we either go to an auto refresh (as 21610618SOmar.Naji@arm.com * determined by the refresh state machine), or to a precharge 21710618SOmar.Naji@arm.com * power down mode. From idle the memory can also go to the active 21810618SOmar.Naji@arm.com * state (with one or more banks active), and in turn from there 21910618SOmar.Naji@arm.com * to active power down. At the moment we do not capture the deep 22010618SOmar.Naji@arm.com * power down and self-refresh state. 22110618SOmar.Naji@arm.com */ 22210618SOmar.Naji@arm.com enum PowerState { 22310618SOmar.Naji@arm.com PWR_IDLE = 0, 22410618SOmar.Naji@arm.com PWR_REF, 22510618SOmar.Naji@arm.com PWR_PRE_PDN, 22610618SOmar.Naji@arm.com PWR_ACT, 22710618SOmar.Naji@arm.com PWR_ACT_PDN 22810618SOmar.Naji@arm.com }; 22910618SOmar.Naji@arm.com 23010618SOmar.Naji@arm.com /** 23110618SOmar.Naji@arm.com * The refresh state is used to control the progress of the 23210618SOmar.Naji@arm.com * refresh scheduling. When normal operation is in progress the 23310618SOmar.Naji@arm.com * refresh state is idle. From there, it progresses to the refresh 23410618SOmar.Naji@arm.com * drain state once tREFI has passed. The refresh drain state 23510618SOmar.Naji@arm.com * captures the DRAM row active state, as it will stay there until 23610618SOmar.Naji@arm.com * all ongoing accesses complete. Thereafter all banks are 23710618SOmar.Naji@arm.com * precharged, and lastly, the DRAM is refreshed. 23810618SOmar.Naji@arm.com */ 23910618SOmar.Naji@arm.com enum RefreshState { 24010618SOmar.Naji@arm.com REF_IDLE = 0, 24110618SOmar.Naji@arm.com REF_DRAIN, 24210618SOmar.Naji@arm.com REF_PRE, 24310618SOmar.Naji@arm.com REF_RUN 24410618SOmar.Naji@arm.com }; 24510618SOmar.Naji@arm.com 24610618SOmar.Naji@arm.com /** 24710618SOmar.Naji@arm.com * A reference to the parent DRAMCtrl instance 24810618SOmar.Naji@arm.com */ 24910618SOmar.Naji@arm.com DRAMCtrl& memory; 25010618SOmar.Naji@arm.com 25110618SOmar.Naji@arm.com /** 25210618SOmar.Naji@arm.com * Since we are taking decisions out of order, we need to keep 25310618SOmar.Naji@arm.com * track of what power transition is happening at what time, such 25410618SOmar.Naji@arm.com * that we can go back in time and change history. For example, if 25510618SOmar.Naji@arm.com * we precharge all banks and schedule going to the idle state, we 25610618SOmar.Naji@arm.com * might at a later point decide to activate a bank before the 25710618SOmar.Naji@arm.com * transition to idle would have taken place. 25810618SOmar.Naji@arm.com */ 25910618SOmar.Naji@arm.com PowerState pwrStateTrans; 26010618SOmar.Naji@arm.com 26110618SOmar.Naji@arm.com /** 26210618SOmar.Naji@arm.com * Current power state. 26310618SOmar.Naji@arm.com */ 26410618SOmar.Naji@arm.com PowerState pwrState; 26510618SOmar.Naji@arm.com 26610618SOmar.Naji@arm.com /** 26710618SOmar.Naji@arm.com * Track when we transitioned to the current power state 26810618SOmar.Naji@arm.com */ 26910618SOmar.Naji@arm.com Tick pwrStateTick; 27010618SOmar.Naji@arm.com 27110618SOmar.Naji@arm.com /** 27210618SOmar.Naji@arm.com * current refresh state 27310618SOmar.Naji@arm.com */ 27410618SOmar.Naji@arm.com RefreshState refreshState; 27510618SOmar.Naji@arm.com 27610618SOmar.Naji@arm.com /** 27710618SOmar.Naji@arm.com * Keep track of when a refresh is due. 27810618SOmar.Naji@arm.com */ 27910618SOmar.Naji@arm.com Tick refreshDueAt; 28010618SOmar.Naji@arm.com 28110618SOmar.Naji@arm.com /* 28210618SOmar.Naji@arm.com * Command energies 28310618SOmar.Naji@arm.com */ 28410618SOmar.Naji@arm.com Stats::Scalar actEnergy; 28510618SOmar.Naji@arm.com Stats::Scalar preEnergy; 28610618SOmar.Naji@arm.com Stats::Scalar readEnergy; 28710618SOmar.Naji@arm.com Stats::Scalar writeEnergy; 28810618SOmar.Naji@arm.com Stats::Scalar refreshEnergy; 28910618SOmar.Naji@arm.com 29010618SOmar.Naji@arm.com /* 29110618SOmar.Naji@arm.com * Active Background Energy 29210618SOmar.Naji@arm.com */ 29310618SOmar.Naji@arm.com Stats::Scalar actBackEnergy; 29410618SOmar.Naji@arm.com 29510618SOmar.Naji@arm.com /* 29610618SOmar.Naji@arm.com * Precharge Background Energy 29710618SOmar.Naji@arm.com */ 29810618SOmar.Naji@arm.com Stats::Scalar preBackEnergy; 29910618SOmar.Naji@arm.com 30010618SOmar.Naji@arm.com Stats::Scalar totalEnergy; 30110618SOmar.Naji@arm.com Stats::Scalar averagePower; 30210618SOmar.Naji@arm.com 30310618SOmar.Naji@arm.com /** 30410618SOmar.Naji@arm.com * Track time spent in each power state. 30510618SOmar.Naji@arm.com */ 30610618SOmar.Naji@arm.com Stats::Vector pwrStateTime; 30710618SOmar.Naji@arm.com 30810618SOmar.Naji@arm.com /** 30910618SOmar.Naji@arm.com * Function to update Power Stats 31010618SOmar.Naji@arm.com */ 31110618SOmar.Naji@arm.com void updatePowerStats(); 31210618SOmar.Naji@arm.com 31310618SOmar.Naji@arm.com /** 31410618SOmar.Naji@arm.com * Schedule a power state transition in the future, and 31510618SOmar.Naji@arm.com * potentially override an already scheduled transition. 31610618SOmar.Naji@arm.com * 31710618SOmar.Naji@arm.com * @param pwr_state Power state to transition to 31810618SOmar.Naji@arm.com * @param tick Tick when transition should take place 31910618SOmar.Naji@arm.com */ 32010618SOmar.Naji@arm.com void schedulePowerEvent(PowerState pwr_state, Tick tick); 32110618SOmar.Naji@arm.com 32210618SOmar.Naji@arm.com public: 32310618SOmar.Naji@arm.com 32410618SOmar.Naji@arm.com /** 32510618SOmar.Naji@arm.com * Current Rank index 32610618SOmar.Naji@arm.com */ 32710618SOmar.Naji@arm.com uint8_t rank; 32810618SOmar.Naji@arm.com 32910618SOmar.Naji@arm.com /** 33010618SOmar.Naji@arm.com * One DRAMPower instance per rank 33110618SOmar.Naji@arm.com */ 33210618SOmar.Naji@arm.com DRAMPower power; 33310618SOmar.Naji@arm.com 33410618SOmar.Naji@arm.com /** 33511675Swendy.elsasser@arm.com * List of comamnds issued, to be sent to DRAMPpower at refresh 33611675Swendy.elsasser@arm.com * and stats dump. Keep commands here since commands to different 33711675Swendy.elsasser@arm.com * banks are added out of order. Will only pass commands up to 33811675Swendy.elsasser@arm.com * curTick() to DRAMPower after sorting. 33911675Swendy.elsasser@arm.com */ 34011675Swendy.elsasser@arm.com std::vector<Command> cmdList; 34111675Swendy.elsasser@arm.com 34211675Swendy.elsasser@arm.com /** 34310618SOmar.Naji@arm.com * Vector of Banks. Each rank is made of several devices which in 34410618SOmar.Naji@arm.com * term are made from several banks. 34510618SOmar.Naji@arm.com */ 34610618SOmar.Naji@arm.com std::vector<Bank> banks; 34710618SOmar.Naji@arm.com 34810618SOmar.Naji@arm.com /** 34910618SOmar.Naji@arm.com * To track number of banks which are currently active for 35010618SOmar.Naji@arm.com * this rank. 35110618SOmar.Naji@arm.com */ 35210618SOmar.Naji@arm.com unsigned int numBanksActive; 35310618SOmar.Naji@arm.com 35410618SOmar.Naji@arm.com /** List to keep track of activate ticks */ 35510618SOmar.Naji@arm.com std::deque<Tick> actTicks; 35610618SOmar.Naji@arm.com 35710618SOmar.Naji@arm.com Rank(DRAMCtrl& _memory, const DRAMCtrlParams* _p); 35810618SOmar.Naji@arm.com 35910618SOmar.Naji@arm.com const std::string name() const 36010618SOmar.Naji@arm.com { 36110618SOmar.Naji@arm.com return csprintf("%s_%d", memory.name(), rank); 36210618SOmar.Naji@arm.com } 36310618SOmar.Naji@arm.com 36410618SOmar.Naji@arm.com /** 36510618SOmar.Naji@arm.com * Kick off accounting for power and refresh states and 36610618SOmar.Naji@arm.com * schedule initial refresh. 36710618SOmar.Naji@arm.com * 36810618SOmar.Naji@arm.com * @param ref_tick Tick for first refresh 36910618SOmar.Naji@arm.com */ 37010618SOmar.Naji@arm.com void startup(Tick ref_tick); 37110618SOmar.Naji@arm.com 37210618SOmar.Naji@arm.com /** 37310619Sandreas.hansson@arm.com * Stop the refresh events. 37410619Sandreas.hansson@arm.com */ 37510619Sandreas.hansson@arm.com void suspend(); 37610619Sandreas.hansson@arm.com 37710619Sandreas.hansson@arm.com /** 37810618SOmar.Naji@arm.com * Check if the current rank is available for scheduling. 37910618SOmar.Naji@arm.com * 38010618SOmar.Naji@arm.com * @param Return true if the rank is idle from a refresh point of view 38110618SOmar.Naji@arm.com */ 38210618SOmar.Naji@arm.com bool isAvailable() const { return refreshState == REF_IDLE; } 38310618SOmar.Naji@arm.com 38410618SOmar.Naji@arm.com /** 38511676Swendy.elsasser@arm.com * Check if the current rank has all banks closed and is not 38611676Swendy.elsasser@arm.com * in a low power state 38711676Swendy.elsasser@arm.com * 38811676Swendy.elsasser@arm.com * @param Return true if the rank is idle from a bank 38911676Swendy.elsasser@arm.com * and power point of view 39011676Swendy.elsasser@arm.com */ 39111676Swendy.elsasser@arm.com bool inPwrIdleState() const { return pwrState == PWR_IDLE; } 39211676Swendy.elsasser@arm.com 39311676Swendy.elsasser@arm.com /** 39410618SOmar.Naji@arm.com * Let the rank check if it was waiting for requests to drain 39510618SOmar.Naji@arm.com * to allow it to transition states. 39610618SOmar.Naji@arm.com */ 39710618SOmar.Naji@arm.com void checkDrainDone(); 39810618SOmar.Naji@arm.com 39911675Swendy.elsasser@arm.com /** 40011675Swendy.elsasser@arm.com * Push command out of cmdList queue that are scheduled at 40111675Swendy.elsasser@arm.com * or before curTick() to DRAMPower library 40211675Swendy.elsasser@arm.com * All commands before curTick are guaranteed to be complete 40311675Swendy.elsasser@arm.com * and can safely be flushed. 40411675Swendy.elsasser@arm.com */ 40511675Swendy.elsasser@arm.com void flushCmdList(); 40611675Swendy.elsasser@arm.com 40710618SOmar.Naji@arm.com /* 40810618SOmar.Naji@arm.com * Function to register Stats 40910618SOmar.Naji@arm.com */ 41010618SOmar.Naji@arm.com void regStats(); 41110618SOmar.Naji@arm.com 41210618SOmar.Naji@arm.com void processActivateEvent(); 41310618SOmar.Naji@arm.com EventWrapper<Rank, &Rank::processActivateEvent> 41410618SOmar.Naji@arm.com activateEvent; 41510618SOmar.Naji@arm.com 41610618SOmar.Naji@arm.com void processPrechargeEvent(); 41710618SOmar.Naji@arm.com EventWrapper<Rank, &Rank::processPrechargeEvent> 41810618SOmar.Naji@arm.com prechargeEvent; 41910618SOmar.Naji@arm.com 42010618SOmar.Naji@arm.com void processRefreshEvent(); 42110618SOmar.Naji@arm.com EventWrapper<Rank, &Rank::processRefreshEvent> 42210618SOmar.Naji@arm.com refreshEvent; 42310618SOmar.Naji@arm.com 42410618SOmar.Naji@arm.com void processPowerEvent(); 42510618SOmar.Naji@arm.com EventWrapper<Rank, &Rank::processPowerEvent> 42610618SOmar.Naji@arm.com powerEvent; 42710618SOmar.Naji@arm.com 42810618SOmar.Naji@arm.com }; 42910618SOmar.Naji@arm.com 4309243SN/A /** 4319831SN/A * A burst helper helps organize and manage a packet that is larger than 4329831SN/A * the DRAM burst size. A system packet that is larger than the burst size 4339831SN/A * is split into multiple DRAM packets and all those DRAM packets point to 4349831SN/A * a single burst helper such that we know when the whole packet is served. 4359831SN/A */ 4369831SN/A class BurstHelper { 4379831SN/A 4389831SN/A public: 4399831SN/A 4409831SN/A /** Number of DRAM bursts requred for a system packet **/ 4419831SN/A const unsigned int burstCount; 4429831SN/A 4439831SN/A /** Number of DRAM bursts serviced so far for a system packet **/ 4449831SN/A unsigned int burstsServiced; 4459831SN/A 4469831SN/A BurstHelper(unsigned int _burstCount) 4479831SN/A : burstCount(_burstCount), burstsServiced(0) 44810618SOmar.Naji@arm.com { } 4499831SN/A }; 4509831SN/A 4519831SN/A /** 4529243SN/A * A DRAM packet stores packets along with the timestamp of when 4539243SN/A * the packet entered the queue, and also the decoded address. 4549243SN/A */ 4559243SN/A class DRAMPacket { 4569243SN/A 4579243SN/A public: 4589243SN/A 4599243SN/A /** When did request enter the controller */ 4609243SN/A const Tick entryTime; 4619243SN/A 4629243SN/A /** When will request leave the controller */ 4639243SN/A Tick readyTime; 4649243SN/A 4659243SN/A /** This comes from the outside world */ 4669243SN/A const PacketPtr pkt; 4679243SN/A 4689966SN/A const bool isRead; 4699966SN/A 4709243SN/A /** Will be populated by address decoder */ 4719243SN/A const uint8_t rank; 4729967SN/A const uint8_t bank; 47310245Sandreas.hansson@arm.com const uint32_t row; 4749831SN/A 4759831SN/A /** 4769967SN/A * Bank id is calculated considering banks in all the ranks 4779967SN/A * eg: 2 ranks each with 8 banks, then bankId = 0 --> rank0, bank0 and 4789967SN/A * bankId = 8 --> rank1, bank0 4799967SN/A */ 4809967SN/A const uint16_t bankId; 4819967SN/A 4829967SN/A /** 4839831SN/A * The starting address of the DRAM packet. 4849831SN/A * This address could be unaligned to burst size boundaries. The 4859831SN/A * reason is to keep the address offset so we can accurately check 4869831SN/A * incoming read packets with packets in the write queue. 4879831SN/A */ 4889832SN/A Addr addr; 4899831SN/A 4909831SN/A /** 4919831SN/A * The size of this dram packet in bytes 4929831SN/A * It is always equal or smaller than DRAM burst size 4939831SN/A */ 4949832SN/A unsigned int size; 4959831SN/A 4969831SN/A /** 4979831SN/A * A pointer to the BurstHelper if this DRAMPacket is a split packet 4989831SN/A * If not a split packet (common case), this is set to NULL 4999831SN/A */ 5009831SN/A BurstHelper* burstHelper; 5019967SN/A Bank& bankRef; 50210618SOmar.Naji@arm.com Rank& rankRef; 5039243SN/A 5049967SN/A DRAMPacket(PacketPtr _pkt, bool is_read, uint8_t _rank, uint8_t _bank, 50510245Sandreas.hansson@arm.com uint32_t _row, uint16_t bank_id, Addr _addr, 50610618SOmar.Naji@arm.com unsigned int _size, Bank& bank_ref, Rank& rank_ref) 5079243SN/A : entryTime(curTick()), readyTime(curTick()), 5089967SN/A pkt(_pkt), isRead(is_read), rank(_rank), bank(_bank), row(_row), 5099967SN/A bankId(bank_id), addr(_addr), size(_size), burstHelper(NULL), 51010618SOmar.Naji@arm.com bankRef(bank_ref), rankRef(rank_ref) 5119243SN/A { } 5129243SN/A 5139243SN/A }; 5149243SN/A 5159243SN/A /** 5169243SN/A * Bunch of things requires to setup "events" in gem5 51710206Sandreas.hansson@arm.com * When event "respondEvent" occurs for example, the method 51810206Sandreas.hansson@arm.com * processRespondEvent is called; no parameters are allowed 5199243SN/A * in these methods 5209243SN/A */ 52110208Sandreas.hansson@arm.com void processNextReqEvent(); 52210208Sandreas.hansson@arm.com EventWrapper<DRAMCtrl,&DRAMCtrl::processNextReqEvent> nextReqEvent; 52310208Sandreas.hansson@arm.com 5249243SN/A void processRespondEvent(); 52510146Sandreas.hansson@arm.com EventWrapper<DRAMCtrl, &DRAMCtrl::processRespondEvent> respondEvent; 5269243SN/A 5279243SN/A /** 5289243SN/A * Check if the read queue has room for more entries 5299243SN/A * 5309831SN/A * @param pktCount The number of entries needed in the read queue 5319243SN/A * @return true if read queue is full, false otherwise 5329243SN/A */ 5339831SN/A bool readQueueFull(unsigned int pktCount) const; 5349243SN/A 5359243SN/A /** 5369243SN/A * Check if the write queue has room for more entries 5379243SN/A * 5389831SN/A * @param pktCount The number of entries needed in the write queue 5399243SN/A * @return true if write queue is full, false otherwise 5409243SN/A */ 5419831SN/A bool writeQueueFull(unsigned int pktCount) const; 5429243SN/A 5439243SN/A /** 5449243SN/A * When a new read comes in, first check if the write q has a 5459243SN/A * pending request to the same address.\ If not, decode the 5469831SN/A * address to populate rank/bank/row, create one or mutliple 5479831SN/A * "dram_pkt", and push them to the back of the read queue.\ 5489831SN/A * If this is the only 5499243SN/A * read request in the system, schedule an event to start 5509243SN/A * servicing it. 5519243SN/A * 5529243SN/A * @param pkt The request packet from the outside world 5539831SN/A * @param pktCount The number of DRAM bursts the pkt 5549831SN/A * translate to. If pkt size is larger then one full burst, 5559831SN/A * then pktCount is greater than one. 5569243SN/A */ 5579831SN/A void addToReadQueue(PacketPtr pkt, unsigned int pktCount); 5589243SN/A 5599243SN/A /** 5609243SN/A * Decode the incoming pkt, create a dram_pkt and push to the 5619243SN/A * back of the write queue. \If the write q length is more than 5629243SN/A * the threshold specified by the user, ie the queue is beginning 5639243SN/A * to get full, stop reads, and start draining writes. 5649243SN/A * 5659243SN/A * @param pkt The request packet from the outside world 5669831SN/A * @param pktCount The number of DRAM bursts the pkt 5679831SN/A * translate to. If pkt size is larger then one full burst, 5689831SN/A * then pktCount is greater than one. 5699243SN/A */ 5709831SN/A void addToWriteQueue(PacketPtr pkt, unsigned int pktCount); 5719243SN/A 5729243SN/A /** 5739243SN/A * Actually do the DRAM access - figure out the latency it 5749243SN/A * will take to service the req based on bank state, channel state etc 5759243SN/A * and then update those states to account for this request.\ Based 5769243SN/A * on this, update the packet's "readyTime" and move it to the 5779243SN/A * response q from where it will eventually go back to the outside 5789243SN/A * world. 5799243SN/A * 5809243SN/A * @param pkt The DRAM packet created from the outside world pkt 5819243SN/A */ 5829243SN/A void doDRAMAccess(DRAMPacket* dram_pkt); 5839243SN/A 5849243SN/A /** 5859243SN/A * When a packet reaches its "readyTime" in the response Q, 5869243SN/A * use the "access()" method in AbstractMemory to actually 5879243SN/A * create the response packet, and send it back to the outside 5889243SN/A * world requestor. 5899243SN/A * 5909243SN/A * @param pkt The packet from the outside world 5919726SN/A * @param static_latency Static latency to add before sending the packet 5929243SN/A */ 5939726SN/A void accessAndRespond(PacketPtr pkt, Tick static_latency); 5949243SN/A 5959243SN/A /** 5969243SN/A * Address decoder to figure out physical mapping onto ranks, 5979831SN/A * banks, and rows. This function is called multiple times on the same 5989831SN/A * system packet if the pakcet is larger than burst of the memory. The 5999831SN/A * dramPktAddr is used for the offset within the packet. 6009243SN/A * 6019243SN/A * @param pkt The packet from the outside world 6029831SN/A * @param dramPktAddr The starting address of the DRAM packet 6039831SN/A * @param size The size of the DRAM packet in bytes 6049966SN/A * @param isRead Is the request for a read or a write to DRAM 6059243SN/A * @return A DRAMPacket pointer with the decoded information 6069243SN/A */ 60710143SN/A DRAMPacket* decodeAddr(PacketPtr pkt, Addr dramPktAddr, unsigned int size, 60810143SN/A bool isRead); 6099243SN/A 6109243SN/A /** 61110206Sandreas.hansson@arm.com * The memory schduler/arbiter - picks which request needs to 6129567SN/A * go next, based on the specified policy such as FCFS or FR-FCFS 61310206Sandreas.hansson@arm.com * and moves it to the head of the queue. 61410393Swendy.elsasser@arm.com * Prioritizes accesses to the same rank as previous burst unless 61510393Swendy.elsasser@arm.com * controller is switching command type. 61610393Swendy.elsasser@arm.com * 61710393Swendy.elsasser@arm.com * @param queue Queued requests to consider 61810890Swendy.elsasser@arm.com * @param extra_col_delay Any extra delay due to a read/write switch 61910618SOmar.Naji@arm.com * @return true if a packet is scheduled to a rank which is available else 62010618SOmar.Naji@arm.com * false 6219243SN/A */ 62210890Swendy.elsasser@arm.com bool chooseNext(std::deque<DRAMPacket*>& queue, Tick extra_col_delay); 6239243SN/A 6249243SN/A /** 6259974SN/A * For FR-FCFS policy reorder the read/write queue depending on row buffer 62610890Swendy.elsasser@arm.com * hits and earliest bursts available in DRAM 62710393Swendy.elsasser@arm.com * 62810393Swendy.elsasser@arm.com * @param queue Queued requests to consider 62910890Swendy.elsasser@arm.com * @param extra_col_delay Any extra delay due to a read/write switch 63010618SOmar.Naji@arm.com * @return true if a packet is scheduled to a rank which is available else 63110618SOmar.Naji@arm.com * false 6329974SN/A */ 63310890Swendy.elsasser@arm.com bool reorderQueue(std::deque<DRAMPacket*>& queue, Tick extra_col_delay); 6349974SN/A 6359974SN/A /** 63610211Sandreas.hansson@arm.com * Find which are the earliest banks ready to issue an activate 63710211Sandreas.hansson@arm.com * for the enqueued requests. Assumes maximum of 64 banks per DIMM 63810393Swendy.elsasser@arm.com * Also checks if the bank is already prepped. 6399967SN/A * 64010393Swendy.elsasser@arm.com * @param queue Queued requests to consider 64110890Swendy.elsasser@arm.com * @param time of seamless burst command 6429967SN/A * @return One-hot encoded mask of bank indices 64310890Swendy.elsasser@arm.com * @return boolean indicating burst can issue seamlessly, with no gaps 6449967SN/A */ 64510890Swendy.elsasser@arm.com std::pair<uint64_t, bool> minBankPrep(const std::deque<DRAMPacket*>& queue, 64610890Swendy.elsasser@arm.com Tick min_col_at) const; 6479488SN/A 6489488SN/A /** 6499488SN/A * Keep track of when row activations happen, in order to enforce 6509488SN/A * the maximum number of activations in the activation window. The 6519488SN/A * method updates the time that the banks become available based 6529488SN/A * on the current limits. 65310210Sandreas.hansson@arm.com * 65410618SOmar.Naji@arm.com * @param rank_ref Reference to the rank 65510618SOmar.Naji@arm.com * @param bank_ref Reference to the bank 65610210Sandreas.hansson@arm.com * @param act_tick Time when the activation takes place 65710210Sandreas.hansson@arm.com * @param row Index of the row 6589488SN/A */ 65910618SOmar.Naji@arm.com void activateBank(Rank& rank_ref, Bank& bank_ref, Tick act_tick, 66010618SOmar.Naji@arm.com uint32_t row); 66110207Sandreas.hansson@arm.com 66210207Sandreas.hansson@arm.com /** 66310207Sandreas.hansson@arm.com * Precharge a given bank and also update when the precharge is 66410207Sandreas.hansson@arm.com * done. This will also deal with any stats related to the 66510207Sandreas.hansson@arm.com * accesses to the open page. 66610207Sandreas.hansson@arm.com * 66710618SOmar.Naji@arm.com * @param rank_ref The rank to precharge 66810247Sandreas.hansson@arm.com * @param bank_ref The bank to precharge 66910211Sandreas.hansson@arm.com * @param pre_at Time when the precharge takes place 67010247Sandreas.hansson@arm.com * @param trace Is this an auto precharge then do not add to trace 67110207Sandreas.hansson@arm.com */ 67210618SOmar.Naji@arm.com void prechargeBank(Rank& rank_ref, Bank& bank_ref, 67310618SOmar.Naji@arm.com Tick pre_at, bool trace = true); 6749488SN/A 67510143SN/A /** 67610143SN/A * Used for debugging to observe the contents of the queues. 67710143SN/A */ 6789243SN/A void printQs() const; 6799243SN/A 6809243SN/A /** 68110889Sandreas.hansson@arm.com * Burst-align an address. 68210889Sandreas.hansson@arm.com * 68310889Sandreas.hansson@arm.com * @param addr The potentially unaligned address 68410889Sandreas.hansson@arm.com * 68510889Sandreas.hansson@arm.com * @return An address aligned to a DRAM burst 68610889Sandreas.hansson@arm.com */ 68710889Sandreas.hansson@arm.com Addr burstAlign(Addr addr) const { return (addr & ~(Addr(burstSize - 1))); } 68810889Sandreas.hansson@arm.com 68910889Sandreas.hansson@arm.com /** 6909243SN/A * The controller's main read and write queues 6919243SN/A */ 6929833SN/A std::deque<DRAMPacket*> readQueue; 6939833SN/A std::deque<DRAMPacket*> writeQueue; 6949243SN/A 6959243SN/A /** 69610889Sandreas.hansson@arm.com * To avoid iterating over the write queue to check for 69710889Sandreas.hansson@arm.com * overlapping transactions, maintain a set of burst addresses 69810889Sandreas.hansson@arm.com * that are currently queued. Since we merge writes to the same 69910889Sandreas.hansson@arm.com * location we never have more than one address to the same burst 70010889Sandreas.hansson@arm.com * address. 70110889Sandreas.hansson@arm.com */ 70210889Sandreas.hansson@arm.com std::unordered_set<Addr> isInWriteQueue; 70310889Sandreas.hansson@arm.com 70410889Sandreas.hansson@arm.com /** 7059243SN/A * Response queue where read packets wait after we're done working 7069567SN/A * with them, but it's not time to send the response yet. The 7079567SN/A * responses are stored seperately mostly to keep the code clean 7089567SN/A * and help with events scheduling. For all logical purposes such 7099567SN/A * as sizing the read queue, this and the main read queue need to 7109567SN/A * be added together. 7119243SN/A */ 7129833SN/A std::deque<DRAMPacket*> respQueue; 7139243SN/A 7149567SN/A /** 71510618SOmar.Naji@arm.com * Vector of ranks 7169243SN/A */ 71710618SOmar.Naji@arm.com std::vector<Rank*> ranks; 7189243SN/A 7199243SN/A /** 7209243SN/A * The following are basic design parameters of the memory 7219831SN/A * controller, and are initialized based on parameter values. 7229831SN/A * The rowsPerBank is determined based on the capacity, number of 7239831SN/A * ranks and banks, the burst size, and the row buffer size. 7249243SN/A */ 72510489SOmar.Naji@arm.com const uint32_t deviceSize; 7269831SN/A const uint32_t deviceBusWidth; 7279831SN/A const uint32_t burstLength; 7289831SN/A const uint32_t deviceRowBufferSize; 7299831SN/A const uint32_t devicesPerRank; 7309831SN/A const uint32_t burstSize; 7319831SN/A const uint32_t rowBufferSize; 73210140SN/A const uint32_t columnsPerRowBuffer; 73310286Sandreas.hansson@arm.com const uint32_t columnsPerStripe; 7349243SN/A const uint32_t ranksPerChannel; 73510394Swendy.elsasser@arm.com const uint32_t bankGroupsPerRank; 73610394Swendy.elsasser@arm.com const bool bankGroupArch; 7379243SN/A const uint32_t banksPerRank; 7389566SN/A const uint32_t channels; 7399243SN/A uint32_t rowsPerBank; 7409243SN/A const uint32_t readBufferSize; 7419243SN/A const uint32_t writeBufferSize; 74210140SN/A const uint32_t writeHighThreshold; 74310140SN/A const uint32_t writeLowThreshold; 74410140SN/A const uint32_t minWritesPerSwitch; 74510140SN/A uint32_t writesThisTime; 74610147Sandreas.hansson@arm.com uint32_t readsThisTime; 7479243SN/A 7489243SN/A /** 7499243SN/A * Basic memory timing parameters initialized based on parameter 7509243SN/A * values. 7519243SN/A */ 75210286Sandreas.hansson@arm.com const Tick M5_CLASS_VAR_USED tCK; 7539243SN/A const Tick tWTR; 75410206Sandreas.hansson@arm.com const Tick tRTW; 75510393Swendy.elsasser@arm.com const Tick tCS; 7569243SN/A const Tick tBURST; 75710394Swendy.elsasser@arm.com const Tick tCCD_L; 7589243SN/A const Tick tRCD; 7599243SN/A const Tick tCL; 7609243SN/A const Tick tRP; 7619963SN/A const Tick tRAS; 76210210Sandreas.hansson@arm.com const Tick tWR; 76310212Sandreas.hansson@arm.com const Tick tRTP; 7649243SN/A const Tick tRFC; 7659243SN/A const Tick tREFI; 7669971SN/A const Tick tRRD; 76710394Swendy.elsasser@arm.com const Tick tRRD_L; 7689488SN/A const Tick tXAW; 76911673SOmar.Naji@arm.com const Tick tXP; 77011673SOmar.Naji@arm.com const Tick tXS; 7719488SN/A const uint32_t activationLimit; 7729243SN/A 7739243SN/A /** 7749243SN/A * Memory controller configuration initialized based on parameter 7759243SN/A * values. 7769243SN/A */ 7779243SN/A Enums::MemSched memSchedPolicy; 7789243SN/A Enums::AddrMap addrMapping; 7799243SN/A Enums::PageManage pageMgmt; 7809243SN/A 7819243SN/A /** 78210141SN/A * Max column accesses (read and write) per row, before forefully 78310141SN/A * closing it. 78410141SN/A */ 78510141SN/A const uint32_t maxAccessesPerRow; 78610141SN/A 78710141SN/A /** 7889726SN/A * Pipeline latency of the controller frontend. The frontend 7899726SN/A * contribution is added to writes (that complete when they are in 7909726SN/A * the write buffer) and reads that are serviced the write buffer. 7919726SN/A */ 7929726SN/A const Tick frontendLatency; 7939726SN/A 7949726SN/A /** 7959726SN/A * Pipeline latency of the backend and PHY. Along with the 7969726SN/A * frontend contribution, this latency is added to reads serviced 7979726SN/A * by the DRAM. 7989726SN/A */ 7999726SN/A const Tick backendLatency; 8009726SN/A 8019726SN/A /** 8029243SN/A * Till when has the main data bus been spoken for already? 8039243SN/A */ 8049243SN/A Tick busBusyUntil; 8059243SN/A 8069243SN/A Tick prevArrival; 8079243SN/A 80810206Sandreas.hansson@arm.com /** 80910206Sandreas.hansson@arm.com * The soonest you have to start thinking about the next request 81010206Sandreas.hansson@arm.com * is the longest access time that can occur before 81110206Sandreas.hansson@arm.com * busBusyUntil. Assuming you need to precharge, open a new row, 81210206Sandreas.hansson@arm.com * and access, it is tRP + tRCD + tCL. 81310206Sandreas.hansson@arm.com */ 81410206Sandreas.hansson@arm.com Tick nextReqTime; 8159972SN/A 8169243SN/A // All statistics that the model needs to capture 8179243SN/A Stats::Scalar readReqs; 8189243SN/A Stats::Scalar writeReqs; 8199831SN/A Stats::Scalar readBursts; 8209831SN/A Stats::Scalar writeBursts; 8219975SN/A Stats::Scalar bytesReadDRAM; 8229975SN/A Stats::Scalar bytesReadWrQ; 8239243SN/A Stats::Scalar bytesWritten; 8249977SN/A Stats::Scalar bytesReadSys; 8259977SN/A Stats::Scalar bytesWrittenSys; 8269243SN/A Stats::Scalar servicedByWrQ; 8279977SN/A Stats::Scalar mergedWrBursts; 8289243SN/A Stats::Scalar neitherReadNorWrite; 8299977SN/A Stats::Vector perBankRdBursts; 8309977SN/A Stats::Vector perBankWrBursts; 8319243SN/A Stats::Scalar numRdRetry; 8329243SN/A Stats::Scalar numWrRetry; 8339243SN/A Stats::Scalar totGap; 8349243SN/A Stats::Vector readPktSize; 8359243SN/A Stats::Vector writePktSize; 8369243SN/A Stats::Vector rdQLenPdf; 8379243SN/A Stats::Vector wrQLenPdf; 8389727SN/A Stats::Histogram bytesPerActivate; 83910147Sandreas.hansson@arm.com Stats::Histogram rdPerTurnAround; 84010147Sandreas.hansson@arm.com Stats::Histogram wrPerTurnAround; 8419243SN/A 8429243SN/A // Latencies summed over all requests 8439243SN/A Stats::Scalar totQLat; 8449243SN/A Stats::Scalar totMemAccLat; 8459243SN/A Stats::Scalar totBusLat; 8469243SN/A 8479243SN/A // Average latencies per request 8489243SN/A Stats::Formula avgQLat; 8499243SN/A Stats::Formula avgBusLat; 8509243SN/A Stats::Formula avgMemAccLat; 8519243SN/A 8529243SN/A // Average bandwidth 8539243SN/A Stats::Formula avgRdBW; 8549243SN/A Stats::Formula avgWrBW; 8559977SN/A Stats::Formula avgRdBWSys; 8569977SN/A Stats::Formula avgWrBWSys; 8579243SN/A Stats::Formula peakBW; 8589243SN/A Stats::Formula busUtil; 8599975SN/A Stats::Formula busUtilRead; 8609975SN/A Stats::Formula busUtilWrite; 8619243SN/A 8629243SN/A // Average queue lengths 8639243SN/A Stats::Average avgRdQLen; 8649243SN/A Stats::Average avgWrQLen; 8659243SN/A 8669243SN/A // Row hit count and rate 8679243SN/A Stats::Scalar readRowHits; 8689243SN/A Stats::Scalar writeRowHits; 8699243SN/A Stats::Formula readRowHitRate; 8709243SN/A Stats::Formula writeRowHitRate; 8719243SN/A Stats::Formula avgGap; 8729243SN/A 8739975SN/A // DRAM Power Calculation 8749975SN/A Stats::Formula pageHitRate; 8759975SN/A 87610393Swendy.elsasser@arm.com // Holds the value of the rank of burst issued 87710393Swendy.elsasser@arm.com uint8_t activeRank; 87810393Swendy.elsasser@arm.com 87910432SOmar.Naji@arm.com // timestamp offset 88010432SOmar.Naji@arm.com uint64_t timeStampOffset; 88110432SOmar.Naji@arm.com 88211190Sandreas.hansson@arm.com /** 88311190Sandreas.hansson@arm.com * Upstream caches need this packet until true is returned, so 88411190Sandreas.hansson@arm.com * hold it for deletion until a subsequent call 8859349SN/A */ 88611190Sandreas.hansson@arm.com std::unique_ptr<Packet> pendingDelete; 8879349SN/A 88810432SOmar.Naji@arm.com /** 88910618SOmar.Naji@arm.com * This function increments the energy when called. If stats are 89010618SOmar.Naji@arm.com * dumped periodically, note accumulated energy values will 89110618SOmar.Naji@arm.com * appear in the stats (even if the stats are reset). This is a 89210618SOmar.Naji@arm.com * result of the energy values coming from DRAMPower, and there 89310618SOmar.Naji@arm.com * is currently no support for resetting the state. 89410618SOmar.Naji@arm.com * 89510618SOmar.Naji@arm.com * @param rank Currrent rank 89610618SOmar.Naji@arm.com */ 89710618SOmar.Naji@arm.com void updatePowerStats(Rank& rank_ref); 89810432SOmar.Naji@arm.com 89910432SOmar.Naji@arm.com /** 90011675Swendy.elsasser@arm.com * Function for sorting Command structures based on timeStamp 90110432SOmar.Naji@arm.com * 90211675Swendy.elsasser@arm.com * @param a Memory Command 90311675Swendy.elsasser@arm.com * @param next Memory Command 90411675Swendy.elsasser@arm.com * @return true if timeStamp of Command 1 < timeStamp of Command 2 90510432SOmar.Naji@arm.com */ 90611675Swendy.elsasser@arm.com static bool sortTime(const Command& cmd, const Command& cmd_next) { 90711675Swendy.elsasser@arm.com return cmd.timeStamp < cmd_next.timeStamp; 90810432SOmar.Naji@arm.com }; 90910432SOmar.Naji@arm.com 9109243SN/A public: 9119243SN/A 91211169Sandreas.hansson@arm.com void regStats() override; 9139243SN/A 91410146Sandreas.hansson@arm.com DRAMCtrl(const DRAMCtrlParams* p); 9159243SN/A 91611168Sandreas.hansson@arm.com DrainState drain() override; 9179243SN/A 9189294SN/A virtual BaseSlavePort& getSlavePort(const std::string& if_name, 91911169Sandreas.hansson@arm.com PortID idx = InvalidPortID) override; 9209243SN/A 92111168Sandreas.hansson@arm.com virtual void init() override; 92211168Sandreas.hansson@arm.com virtual void startup() override; 92311168Sandreas.hansson@arm.com virtual void drainResume() override; 9249243SN/A 92511676Swendy.elsasser@arm.com /** 92611676Swendy.elsasser@arm.com * Return true once refresh is complete for all ranks and there are no 92711676Swendy.elsasser@arm.com * additional commands enqueued. (only evaluated when draining) 92811676Swendy.elsasser@arm.com * This will ensure that all banks are closed, power state is IDLE, and 92911676Swendy.elsasser@arm.com * power stats have been updated 93011676Swendy.elsasser@arm.com * 93111676Swendy.elsasser@arm.com * @return true if all ranks have refreshed, with no commands enqueued 93211676Swendy.elsasser@arm.com * 93311676Swendy.elsasser@arm.com */ 93411676Swendy.elsasser@arm.com bool allRanksDrained() const; 93511676Swendy.elsasser@arm.com 9369243SN/A protected: 9379243SN/A 9389243SN/A Tick recvAtomic(PacketPtr pkt); 9399243SN/A void recvFunctional(PacketPtr pkt); 9409243SN/A bool recvTimingReq(PacketPtr pkt); 9419243SN/A 9429243SN/A}; 9439243SN/A 94410146Sandreas.hansson@arm.com#endif //__MEM_DRAM_CTRL_HH__ 945