dram_ctrl.hh revision 11675
19243SN/A/* 211675Swendy.elsasser@arm.com * Copyright (c) 2012-2016 ARM Limited 39243SN/A * All rights reserved 49243SN/A * 59243SN/A * The license below extends only to copyright in the software and shall 69243SN/A * not be construed as granting a license to any other intellectual 79243SN/A * property including but not limited to intellectual property relating 89243SN/A * to a hardware implementation of the functionality of the software 99243SN/A * licensed hereunder. You may use the software subject to the license 109243SN/A * terms below provided that you ensure that this notice is replicated 119243SN/A * unmodified and in its entirety in all distributions of the software, 129243SN/A * modified or unmodified, in source code or in binary form. 139243SN/A * 149831SN/A * Copyright (c) 2013 Amin Farmahini-Farahani 159831SN/A * All rights reserved. 169831SN/A * 179243SN/A * Redistribution and use in source and binary forms, with or without 189243SN/A * modification, are permitted provided that the following conditions are 199243SN/A * met: redistributions of source code must retain the above copyright 209243SN/A * notice, this list of conditions and the following disclaimer; 219243SN/A * redistributions in binary form must reproduce the above copyright 229243SN/A * notice, this list of conditions and the following disclaimer in the 239243SN/A * documentation and/or other materials provided with the distribution; 249243SN/A * neither the name of the copyright holders nor the names of its 259243SN/A * contributors may be used to endorse or promote products derived from 269243SN/A * this software without specific prior written permission. 279243SN/A * 289243SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 299243SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 309243SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 319243SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 329243SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 339243SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 349243SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 359243SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 369243SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 379243SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 389243SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 399243SN/A * 409243SN/A * Authors: Andreas Hansson 419243SN/A * Ani Udipi 429967SN/A * Neha Agarwal 4310618SOmar.Naji@arm.com * Omar Naji 4411555Sjungma@eit.uni-kl.de * Matthias Jung 459243SN/A */ 469243SN/A 479243SN/A/** 489243SN/A * @file 4910146Sandreas.hansson@arm.com * DRAMCtrl declaration 509243SN/A */ 519243SN/A 5210146Sandreas.hansson@arm.com#ifndef __MEM_DRAM_CTRL_HH__ 5310146Sandreas.hansson@arm.com#define __MEM_DRAM_CTRL_HH__ 549243SN/A 559488SN/A#include <deque> 5610618SOmar.Naji@arm.com#include <string> 5710889Sandreas.hansson@arm.com#include <unordered_set> 589488SN/A 599243SN/A#include "base/statistics.hh" 609243SN/A#include "enums/AddrMap.hh" 619243SN/A#include "enums/MemSched.hh" 629243SN/A#include "enums/PageManage.hh" 639243SN/A#include "mem/abstract_mem.hh" 649243SN/A#include "mem/qport.hh" 6510146Sandreas.hansson@arm.com#include "params/DRAMCtrl.hh" 669243SN/A#include "sim/eventq.hh" 6710432SOmar.Naji@arm.com#include "mem/drampower.hh" 689243SN/A 699243SN/A/** 7010287Sandreas.hansson@arm.com * The DRAM controller is a single-channel memory controller capturing 7110287Sandreas.hansson@arm.com * the most important timing constraints associated with a 7210287Sandreas.hansson@arm.com * contemporary DRAM. For multi-channel memory systems, the controller 7310287Sandreas.hansson@arm.com * is combined with a crossbar model, with the channel address 7410287Sandreas.hansson@arm.com * interleaving taking part in the crossbar. 759243SN/A * 7610287Sandreas.hansson@arm.com * As a basic design principle, this controller 7710287Sandreas.hansson@arm.com * model is not cycle callable, but instead uses events to: 1) decide 7810287Sandreas.hansson@arm.com * when new decisions can be made, 2) when resources become available, 7910287Sandreas.hansson@arm.com * 3) when things are to be considered done, and 4) when to send 8010287Sandreas.hansson@arm.com * things back. Through these simple principles, the model delivers 8110287Sandreas.hansson@arm.com * high performance, and lots of flexibility, allowing users to 8210287Sandreas.hansson@arm.com * evaluate the system impact of a wide range of memory technologies, 8310287Sandreas.hansson@arm.com * such as DDR3/4, LPDDR2/3/4, WideIO1/2, HBM and HMC. 8410287Sandreas.hansson@arm.com * 8510287Sandreas.hansson@arm.com * For more details, please see Hansson et al, "Simulating DRAM 8610287Sandreas.hansson@arm.com * controllers for future system architecture exploration", 8710287Sandreas.hansson@arm.com * Proc. ISPASS, 2014. If you use this model as part of your research 8810287Sandreas.hansson@arm.com * please cite the paper. 899243SN/A */ 9010146Sandreas.hansson@arm.comclass DRAMCtrl : public AbstractMemory 919243SN/A{ 929243SN/A 939243SN/A private: 949243SN/A 959243SN/A // For now, make use of a queued slave port to avoid dealing with 969243SN/A // flow control for the responses being sent back 979243SN/A class MemoryPort : public QueuedSlavePort 989243SN/A { 999243SN/A 10010713Sandreas.hansson@arm.com RespPacketQueue queue; 10110146Sandreas.hansson@arm.com DRAMCtrl& memory; 1029243SN/A 1039243SN/A public: 1049243SN/A 10510146Sandreas.hansson@arm.com MemoryPort(const std::string& name, DRAMCtrl& _memory); 1069243SN/A 1079243SN/A protected: 1089243SN/A 1099243SN/A Tick recvAtomic(PacketPtr pkt); 1109243SN/A 1119243SN/A void recvFunctional(PacketPtr pkt); 1129243SN/A 1139243SN/A bool recvTimingReq(PacketPtr); 1149243SN/A 1159243SN/A virtual AddrRangeList getAddrRanges() const; 1169243SN/A 1179243SN/A }; 1189243SN/A 1199243SN/A /** 1209243SN/A * Our incoming port, for a multi-ported controller add a crossbar 1219243SN/A * in front of it 1229243SN/A */ 1239243SN/A MemoryPort port; 1249243SN/A 1259243SN/A /** 12610619Sandreas.hansson@arm.com * Remeber if the memory system is in timing mode 12710619Sandreas.hansson@arm.com */ 12810619Sandreas.hansson@arm.com bool isTimingMode; 12910619Sandreas.hansson@arm.com 13010619Sandreas.hansson@arm.com /** 1319243SN/A * Remember if we have to retry a request when available. 1329243SN/A */ 1339243SN/A bool retryRdReq; 1349243SN/A bool retryWrReq; 1359243SN/A 1369243SN/A /** 13710206Sandreas.hansson@arm.com * Bus state used to control the read/write switching and drive 13810206Sandreas.hansson@arm.com * the scheduling of the next request. 1399243SN/A */ 14010206Sandreas.hansson@arm.com enum BusState { 14110206Sandreas.hansson@arm.com READ = 0, 14210206Sandreas.hansson@arm.com READ_TO_WRITE, 14310206Sandreas.hansson@arm.com WRITE, 14410206Sandreas.hansson@arm.com WRITE_TO_READ 14510206Sandreas.hansson@arm.com }; 14610206Sandreas.hansson@arm.com 14710206Sandreas.hansson@arm.com BusState busState; 1489243SN/A 1499243SN/A /** 15011675Swendy.elsasser@arm.com * Simple structure to hold the values needed to keep track of 15111675Swendy.elsasser@arm.com * commands for DRAMPower 15211675Swendy.elsasser@arm.com */ 15311675Swendy.elsasser@arm.com struct Command { 15411675Swendy.elsasser@arm.com Data::MemCommand::cmds type; 15511675Swendy.elsasser@arm.com uint8_t bank; 15611675Swendy.elsasser@arm.com Tick timeStamp; 15711675Swendy.elsasser@arm.com 15811675Swendy.elsasser@arm.com constexpr Command(Data::MemCommand::cmds _type, uint8_t _bank, 15911675Swendy.elsasser@arm.com Tick time_stamp) 16011675Swendy.elsasser@arm.com : type(_type), bank(_bank), timeStamp(time_stamp) 16111675Swendy.elsasser@arm.com { } 16211675Swendy.elsasser@arm.com }; 16311675Swendy.elsasser@arm.com 16411675Swendy.elsasser@arm.com /** 16510210Sandreas.hansson@arm.com * A basic class to track the bank state, i.e. what row is 16610210Sandreas.hansson@arm.com * currently open (if any), when is the bank free to accept a new 16710211Sandreas.hansson@arm.com * column (read/write) command, when can it be precharged, and 16810211Sandreas.hansson@arm.com * when can it be activated. 16910210Sandreas.hansson@arm.com * 17010210Sandreas.hansson@arm.com * The bank also keeps track of how many bytes have been accessed 17110210Sandreas.hansson@arm.com * in the open row since it was opened. 1729243SN/A */ 1739243SN/A class Bank 1749243SN/A { 1759243SN/A 1769243SN/A public: 1779243SN/A 17810207Sandreas.hansson@arm.com static const uint32_t NO_ROW = -1; 1799243SN/A 1809243SN/A uint32_t openRow; 18110246Sandreas.hansson@arm.com uint8_t bank; 18210394Swendy.elsasser@arm.com uint8_t bankgr; 1839243SN/A 18410211Sandreas.hansson@arm.com Tick colAllowedAt; 18510210Sandreas.hansson@arm.com Tick preAllowedAt; 1869969SN/A Tick actAllowedAt; 1879243SN/A 18810141SN/A uint32_t rowAccesses; 1899727SN/A uint32_t bytesAccessed; 1909727SN/A 1919727SN/A Bank() : 19210618SOmar.Naji@arm.com openRow(NO_ROW), bank(0), bankgr(0), 19310246Sandreas.hansson@arm.com colAllowedAt(0), preAllowedAt(0), actAllowedAt(0), 19410141SN/A rowAccesses(0), bytesAccessed(0) 1959243SN/A { } 1969243SN/A }; 1979243SN/A 19810618SOmar.Naji@arm.com 19910618SOmar.Naji@arm.com /** 20010618SOmar.Naji@arm.com * Rank class includes a vector of banks. Refresh and Power state 20110618SOmar.Naji@arm.com * machines are defined per rank. Events required to change the 20210618SOmar.Naji@arm.com * state of the refresh and power state machine are scheduled per 20310618SOmar.Naji@arm.com * rank. This class allows the implementation of rank-wise refresh 20410618SOmar.Naji@arm.com * and rank-wise power-down. 20510618SOmar.Naji@arm.com */ 20610618SOmar.Naji@arm.com class Rank : public EventManager 20710618SOmar.Naji@arm.com { 20810618SOmar.Naji@arm.com 20910618SOmar.Naji@arm.com private: 21010618SOmar.Naji@arm.com 21110618SOmar.Naji@arm.com /** 21210618SOmar.Naji@arm.com * The power state captures the different operational states of 21310618SOmar.Naji@arm.com * the DRAM and interacts with the bus read/write state machine, 21410618SOmar.Naji@arm.com * and the refresh state machine. In the idle state all banks are 21510618SOmar.Naji@arm.com * precharged. From there we either go to an auto refresh (as 21610618SOmar.Naji@arm.com * determined by the refresh state machine), or to a precharge 21710618SOmar.Naji@arm.com * power down mode. From idle the memory can also go to the active 21810618SOmar.Naji@arm.com * state (with one or more banks active), and in turn from there 21910618SOmar.Naji@arm.com * to active power down. At the moment we do not capture the deep 22010618SOmar.Naji@arm.com * power down and self-refresh state. 22110618SOmar.Naji@arm.com */ 22210618SOmar.Naji@arm.com enum PowerState { 22310618SOmar.Naji@arm.com PWR_IDLE = 0, 22410618SOmar.Naji@arm.com PWR_REF, 22510618SOmar.Naji@arm.com PWR_PRE_PDN, 22610618SOmar.Naji@arm.com PWR_ACT, 22710618SOmar.Naji@arm.com PWR_ACT_PDN 22810618SOmar.Naji@arm.com }; 22910618SOmar.Naji@arm.com 23010618SOmar.Naji@arm.com /** 23110618SOmar.Naji@arm.com * The refresh state is used to control the progress of the 23210618SOmar.Naji@arm.com * refresh scheduling. When normal operation is in progress the 23310618SOmar.Naji@arm.com * refresh state is idle. From there, it progresses to the refresh 23410618SOmar.Naji@arm.com * drain state once tREFI has passed. The refresh drain state 23510618SOmar.Naji@arm.com * captures the DRAM row active state, as it will stay there until 23610618SOmar.Naji@arm.com * all ongoing accesses complete. Thereafter all banks are 23710618SOmar.Naji@arm.com * precharged, and lastly, the DRAM is refreshed. 23810618SOmar.Naji@arm.com */ 23910618SOmar.Naji@arm.com enum RefreshState { 24010618SOmar.Naji@arm.com REF_IDLE = 0, 24110618SOmar.Naji@arm.com REF_DRAIN, 24210618SOmar.Naji@arm.com REF_PRE, 24310618SOmar.Naji@arm.com REF_RUN 24410618SOmar.Naji@arm.com }; 24510618SOmar.Naji@arm.com 24610618SOmar.Naji@arm.com /** 24710618SOmar.Naji@arm.com * A reference to the parent DRAMCtrl instance 24810618SOmar.Naji@arm.com */ 24910618SOmar.Naji@arm.com DRAMCtrl& memory; 25010618SOmar.Naji@arm.com 25110618SOmar.Naji@arm.com /** 25210618SOmar.Naji@arm.com * Since we are taking decisions out of order, we need to keep 25310618SOmar.Naji@arm.com * track of what power transition is happening at what time, such 25410618SOmar.Naji@arm.com * that we can go back in time and change history. For example, if 25510618SOmar.Naji@arm.com * we precharge all banks and schedule going to the idle state, we 25610618SOmar.Naji@arm.com * might at a later point decide to activate a bank before the 25710618SOmar.Naji@arm.com * transition to idle would have taken place. 25810618SOmar.Naji@arm.com */ 25910618SOmar.Naji@arm.com PowerState pwrStateTrans; 26010618SOmar.Naji@arm.com 26110618SOmar.Naji@arm.com /** 26210618SOmar.Naji@arm.com * Current power state. 26310618SOmar.Naji@arm.com */ 26410618SOmar.Naji@arm.com PowerState pwrState; 26510618SOmar.Naji@arm.com 26610618SOmar.Naji@arm.com /** 26710618SOmar.Naji@arm.com * Track when we transitioned to the current power state 26810618SOmar.Naji@arm.com */ 26910618SOmar.Naji@arm.com Tick pwrStateTick; 27010618SOmar.Naji@arm.com 27110618SOmar.Naji@arm.com /** 27210618SOmar.Naji@arm.com * current refresh state 27310618SOmar.Naji@arm.com */ 27410618SOmar.Naji@arm.com RefreshState refreshState; 27510618SOmar.Naji@arm.com 27610618SOmar.Naji@arm.com /** 27710618SOmar.Naji@arm.com * Keep track of when a refresh is due. 27810618SOmar.Naji@arm.com */ 27910618SOmar.Naji@arm.com Tick refreshDueAt; 28010618SOmar.Naji@arm.com 28110618SOmar.Naji@arm.com /* 28210618SOmar.Naji@arm.com * Command energies 28310618SOmar.Naji@arm.com */ 28410618SOmar.Naji@arm.com Stats::Scalar actEnergy; 28510618SOmar.Naji@arm.com Stats::Scalar preEnergy; 28610618SOmar.Naji@arm.com Stats::Scalar readEnergy; 28710618SOmar.Naji@arm.com Stats::Scalar writeEnergy; 28810618SOmar.Naji@arm.com Stats::Scalar refreshEnergy; 28910618SOmar.Naji@arm.com 29010618SOmar.Naji@arm.com /* 29110618SOmar.Naji@arm.com * Active Background Energy 29210618SOmar.Naji@arm.com */ 29310618SOmar.Naji@arm.com Stats::Scalar actBackEnergy; 29410618SOmar.Naji@arm.com 29510618SOmar.Naji@arm.com /* 29610618SOmar.Naji@arm.com * Precharge Background Energy 29710618SOmar.Naji@arm.com */ 29810618SOmar.Naji@arm.com Stats::Scalar preBackEnergy; 29910618SOmar.Naji@arm.com 30010618SOmar.Naji@arm.com Stats::Scalar totalEnergy; 30110618SOmar.Naji@arm.com Stats::Scalar averagePower; 30210618SOmar.Naji@arm.com 30310618SOmar.Naji@arm.com /** 30410618SOmar.Naji@arm.com * Track time spent in each power state. 30510618SOmar.Naji@arm.com */ 30610618SOmar.Naji@arm.com Stats::Vector pwrStateTime; 30710618SOmar.Naji@arm.com 30810618SOmar.Naji@arm.com /** 30910618SOmar.Naji@arm.com * Function to update Power Stats 31010618SOmar.Naji@arm.com */ 31110618SOmar.Naji@arm.com void updatePowerStats(); 31210618SOmar.Naji@arm.com 31310618SOmar.Naji@arm.com /** 31410618SOmar.Naji@arm.com * Schedule a power state transition in the future, and 31510618SOmar.Naji@arm.com * potentially override an already scheduled transition. 31610618SOmar.Naji@arm.com * 31710618SOmar.Naji@arm.com * @param pwr_state Power state to transition to 31810618SOmar.Naji@arm.com * @param tick Tick when transition should take place 31910618SOmar.Naji@arm.com */ 32010618SOmar.Naji@arm.com void schedulePowerEvent(PowerState pwr_state, Tick tick); 32110618SOmar.Naji@arm.com 32210618SOmar.Naji@arm.com public: 32310618SOmar.Naji@arm.com 32410618SOmar.Naji@arm.com /** 32510618SOmar.Naji@arm.com * Current Rank index 32610618SOmar.Naji@arm.com */ 32710618SOmar.Naji@arm.com uint8_t rank; 32810618SOmar.Naji@arm.com 32910618SOmar.Naji@arm.com /** 33010618SOmar.Naji@arm.com * One DRAMPower instance per rank 33110618SOmar.Naji@arm.com */ 33210618SOmar.Naji@arm.com DRAMPower power; 33310618SOmar.Naji@arm.com 33410618SOmar.Naji@arm.com /** 33511675Swendy.elsasser@arm.com * List of comamnds issued, to be sent to DRAMPpower at refresh 33611675Swendy.elsasser@arm.com * and stats dump. Keep commands here since commands to different 33711675Swendy.elsasser@arm.com * banks are added out of order. Will only pass commands up to 33811675Swendy.elsasser@arm.com * curTick() to DRAMPower after sorting. 33911675Swendy.elsasser@arm.com */ 34011675Swendy.elsasser@arm.com std::vector<Command> cmdList; 34111675Swendy.elsasser@arm.com 34211675Swendy.elsasser@arm.com /** 34310618SOmar.Naji@arm.com * Vector of Banks. Each rank is made of several devices which in 34410618SOmar.Naji@arm.com * term are made from several banks. 34510618SOmar.Naji@arm.com */ 34610618SOmar.Naji@arm.com std::vector<Bank> banks; 34710618SOmar.Naji@arm.com 34810618SOmar.Naji@arm.com /** 34910618SOmar.Naji@arm.com * To track number of banks which are currently active for 35010618SOmar.Naji@arm.com * this rank. 35110618SOmar.Naji@arm.com */ 35210618SOmar.Naji@arm.com unsigned int numBanksActive; 35310618SOmar.Naji@arm.com 35410618SOmar.Naji@arm.com /** List to keep track of activate ticks */ 35510618SOmar.Naji@arm.com std::deque<Tick> actTicks; 35610618SOmar.Naji@arm.com 35710618SOmar.Naji@arm.com Rank(DRAMCtrl& _memory, const DRAMCtrlParams* _p); 35810618SOmar.Naji@arm.com 35910618SOmar.Naji@arm.com const std::string name() const 36010618SOmar.Naji@arm.com { 36110618SOmar.Naji@arm.com return csprintf("%s_%d", memory.name(), rank); 36210618SOmar.Naji@arm.com } 36310618SOmar.Naji@arm.com 36410618SOmar.Naji@arm.com /** 36510618SOmar.Naji@arm.com * Kick off accounting for power and refresh states and 36610618SOmar.Naji@arm.com * schedule initial refresh. 36710618SOmar.Naji@arm.com * 36810618SOmar.Naji@arm.com * @param ref_tick Tick for first refresh 36910618SOmar.Naji@arm.com */ 37010618SOmar.Naji@arm.com void startup(Tick ref_tick); 37110618SOmar.Naji@arm.com 37210618SOmar.Naji@arm.com /** 37310619Sandreas.hansson@arm.com * Stop the refresh events. 37410619Sandreas.hansson@arm.com */ 37510619Sandreas.hansson@arm.com void suspend(); 37610619Sandreas.hansson@arm.com 37710619Sandreas.hansson@arm.com /** 37810618SOmar.Naji@arm.com * Check if the current rank is available for scheduling. 37910618SOmar.Naji@arm.com * 38010618SOmar.Naji@arm.com * @param Return true if the rank is idle from a refresh point of view 38110618SOmar.Naji@arm.com */ 38210618SOmar.Naji@arm.com bool isAvailable() const { return refreshState == REF_IDLE; } 38310618SOmar.Naji@arm.com 38410618SOmar.Naji@arm.com /** 38510618SOmar.Naji@arm.com * Let the rank check if it was waiting for requests to drain 38610618SOmar.Naji@arm.com * to allow it to transition states. 38710618SOmar.Naji@arm.com */ 38810618SOmar.Naji@arm.com void checkDrainDone(); 38910618SOmar.Naji@arm.com 39011675Swendy.elsasser@arm.com /** 39111675Swendy.elsasser@arm.com * Push command out of cmdList queue that are scheduled at 39211675Swendy.elsasser@arm.com * or before curTick() to DRAMPower library 39311675Swendy.elsasser@arm.com * All commands before curTick are guaranteed to be complete 39411675Swendy.elsasser@arm.com * and can safely be flushed. 39511675Swendy.elsasser@arm.com */ 39611675Swendy.elsasser@arm.com void flushCmdList(); 39711675Swendy.elsasser@arm.com 39810618SOmar.Naji@arm.com /* 39910618SOmar.Naji@arm.com * Function to register Stats 40010618SOmar.Naji@arm.com */ 40110618SOmar.Naji@arm.com void regStats(); 40210618SOmar.Naji@arm.com 40310618SOmar.Naji@arm.com void processActivateEvent(); 40410618SOmar.Naji@arm.com EventWrapper<Rank, &Rank::processActivateEvent> 40510618SOmar.Naji@arm.com activateEvent; 40610618SOmar.Naji@arm.com 40710618SOmar.Naji@arm.com void processPrechargeEvent(); 40810618SOmar.Naji@arm.com EventWrapper<Rank, &Rank::processPrechargeEvent> 40910618SOmar.Naji@arm.com prechargeEvent; 41010618SOmar.Naji@arm.com 41110618SOmar.Naji@arm.com void processRefreshEvent(); 41210618SOmar.Naji@arm.com EventWrapper<Rank, &Rank::processRefreshEvent> 41310618SOmar.Naji@arm.com refreshEvent; 41410618SOmar.Naji@arm.com 41510618SOmar.Naji@arm.com void processPowerEvent(); 41610618SOmar.Naji@arm.com EventWrapper<Rank, &Rank::processPowerEvent> 41710618SOmar.Naji@arm.com powerEvent; 41810618SOmar.Naji@arm.com 41910618SOmar.Naji@arm.com }; 42010618SOmar.Naji@arm.com 4219243SN/A /** 4229831SN/A * A burst helper helps organize and manage a packet that is larger than 4239831SN/A * the DRAM burst size. A system packet that is larger than the burst size 4249831SN/A * is split into multiple DRAM packets and all those DRAM packets point to 4259831SN/A * a single burst helper such that we know when the whole packet is served. 4269831SN/A */ 4279831SN/A class BurstHelper { 4289831SN/A 4299831SN/A public: 4309831SN/A 4319831SN/A /** Number of DRAM bursts requred for a system packet **/ 4329831SN/A const unsigned int burstCount; 4339831SN/A 4349831SN/A /** Number of DRAM bursts serviced so far for a system packet **/ 4359831SN/A unsigned int burstsServiced; 4369831SN/A 4379831SN/A BurstHelper(unsigned int _burstCount) 4389831SN/A : burstCount(_burstCount), burstsServiced(0) 43910618SOmar.Naji@arm.com { } 4409831SN/A }; 4419831SN/A 4429831SN/A /** 4439243SN/A * A DRAM packet stores packets along with the timestamp of when 4449243SN/A * the packet entered the queue, and also the decoded address. 4459243SN/A */ 4469243SN/A class DRAMPacket { 4479243SN/A 4489243SN/A public: 4499243SN/A 4509243SN/A /** When did request enter the controller */ 4519243SN/A const Tick entryTime; 4529243SN/A 4539243SN/A /** When will request leave the controller */ 4549243SN/A Tick readyTime; 4559243SN/A 4569243SN/A /** This comes from the outside world */ 4579243SN/A const PacketPtr pkt; 4589243SN/A 4599966SN/A const bool isRead; 4609966SN/A 4619243SN/A /** Will be populated by address decoder */ 4629243SN/A const uint8_t rank; 4639967SN/A const uint8_t bank; 46410245Sandreas.hansson@arm.com const uint32_t row; 4659831SN/A 4669831SN/A /** 4679967SN/A * Bank id is calculated considering banks in all the ranks 4689967SN/A * eg: 2 ranks each with 8 banks, then bankId = 0 --> rank0, bank0 and 4699967SN/A * bankId = 8 --> rank1, bank0 4709967SN/A */ 4719967SN/A const uint16_t bankId; 4729967SN/A 4739967SN/A /** 4749831SN/A * The starting address of the DRAM packet. 4759831SN/A * This address could be unaligned to burst size boundaries. The 4769831SN/A * reason is to keep the address offset so we can accurately check 4779831SN/A * incoming read packets with packets in the write queue. 4789831SN/A */ 4799832SN/A Addr addr; 4809831SN/A 4819831SN/A /** 4829831SN/A * The size of this dram packet in bytes 4839831SN/A * It is always equal or smaller than DRAM burst size 4849831SN/A */ 4859832SN/A unsigned int size; 4869831SN/A 4879831SN/A /** 4889831SN/A * A pointer to the BurstHelper if this DRAMPacket is a split packet 4899831SN/A * If not a split packet (common case), this is set to NULL 4909831SN/A */ 4919831SN/A BurstHelper* burstHelper; 4929967SN/A Bank& bankRef; 49310618SOmar.Naji@arm.com Rank& rankRef; 4949243SN/A 4959967SN/A DRAMPacket(PacketPtr _pkt, bool is_read, uint8_t _rank, uint8_t _bank, 49610245Sandreas.hansson@arm.com uint32_t _row, uint16_t bank_id, Addr _addr, 49710618SOmar.Naji@arm.com unsigned int _size, Bank& bank_ref, Rank& rank_ref) 4989243SN/A : entryTime(curTick()), readyTime(curTick()), 4999967SN/A pkt(_pkt), isRead(is_read), rank(_rank), bank(_bank), row(_row), 5009967SN/A bankId(bank_id), addr(_addr), size(_size), burstHelper(NULL), 50110618SOmar.Naji@arm.com bankRef(bank_ref), rankRef(rank_ref) 5029243SN/A { } 5039243SN/A 5049243SN/A }; 5059243SN/A 5069243SN/A /** 5079243SN/A * Bunch of things requires to setup "events" in gem5 50810206Sandreas.hansson@arm.com * When event "respondEvent" occurs for example, the method 50910206Sandreas.hansson@arm.com * processRespondEvent is called; no parameters are allowed 5109243SN/A * in these methods 5119243SN/A */ 51210208Sandreas.hansson@arm.com void processNextReqEvent(); 51310208Sandreas.hansson@arm.com EventWrapper<DRAMCtrl,&DRAMCtrl::processNextReqEvent> nextReqEvent; 51410208Sandreas.hansson@arm.com 5159243SN/A void processRespondEvent(); 51610146Sandreas.hansson@arm.com EventWrapper<DRAMCtrl, &DRAMCtrl::processRespondEvent> respondEvent; 5179243SN/A 5189243SN/A /** 5199243SN/A * Check if the read queue has room for more entries 5209243SN/A * 5219831SN/A * @param pktCount The number of entries needed in the read queue 5229243SN/A * @return true if read queue is full, false otherwise 5239243SN/A */ 5249831SN/A bool readQueueFull(unsigned int pktCount) const; 5259243SN/A 5269243SN/A /** 5279243SN/A * Check if the write queue has room for more entries 5289243SN/A * 5299831SN/A * @param pktCount The number of entries needed in the write queue 5309243SN/A * @return true if write queue is full, false otherwise 5319243SN/A */ 5329831SN/A bool writeQueueFull(unsigned int pktCount) const; 5339243SN/A 5349243SN/A /** 5359243SN/A * When a new read comes in, first check if the write q has a 5369243SN/A * pending request to the same address.\ If not, decode the 5379831SN/A * address to populate rank/bank/row, create one or mutliple 5389831SN/A * "dram_pkt", and push them to the back of the read queue.\ 5399831SN/A * If this is the only 5409243SN/A * read request in the system, schedule an event to start 5419243SN/A * servicing it. 5429243SN/A * 5439243SN/A * @param pkt The request packet from the outside world 5449831SN/A * @param pktCount The number of DRAM bursts the pkt 5459831SN/A * translate to. If pkt size is larger then one full burst, 5469831SN/A * then pktCount is greater than one. 5479243SN/A */ 5489831SN/A void addToReadQueue(PacketPtr pkt, unsigned int pktCount); 5499243SN/A 5509243SN/A /** 5519243SN/A * Decode the incoming pkt, create a dram_pkt and push to the 5529243SN/A * back of the write queue. \If the write q length is more than 5539243SN/A * the threshold specified by the user, ie the queue is beginning 5549243SN/A * to get full, stop reads, and start draining writes. 5559243SN/A * 5569243SN/A * @param pkt The request packet from the outside world 5579831SN/A * @param pktCount The number of DRAM bursts the pkt 5589831SN/A * translate to. If pkt size is larger then one full burst, 5599831SN/A * then pktCount is greater than one. 5609243SN/A */ 5619831SN/A void addToWriteQueue(PacketPtr pkt, unsigned int pktCount); 5629243SN/A 5639243SN/A /** 5649243SN/A * Actually do the DRAM access - figure out the latency it 5659243SN/A * will take to service the req based on bank state, channel state etc 5669243SN/A * and then update those states to account for this request.\ Based 5679243SN/A * on this, update the packet's "readyTime" and move it to the 5689243SN/A * response q from where it will eventually go back to the outside 5699243SN/A * world. 5709243SN/A * 5719243SN/A * @param pkt The DRAM packet created from the outside world pkt 5729243SN/A */ 5739243SN/A void doDRAMAccess(DRAMPacket* dram_pkt); 5749243SN/A 5759243SN/A /** 5769243SN/A * When a packet reaches its "readyTime" in the response Q, 5779243SN/A * use the "access()" method in AbstractMemory to actually 5789243SN/A * create the response packet, and send it back to the outside 5799243SN/A * world requestor. 5809243SN/A * 5819243SN/A * @param pkt The packet from the outside world 5829726SN/A * @param static_latency Static latency to add before sending the packet 5839243SN/A */ 5849726SN/A void accessAndRespond(PacketPtr pkt, Tick static_latency); 5859243SN/A 5869243SN/A /** 5879243SN/A * Address decoder to figure out physical mapping onto ranks, 5889831SN/A * banks, and rows. This function is called multiple times on the same 5899831SN/A * system packet if the pakcet is larger than burst of the memory. The 5909831SN/A * dramPktAddr is used for the offset within the packet. 5919243SN/A * 5929243SN/A * @param pkt The packet from the outside world 5939831SN/A * @param dramPktAddr The starting address of the DRAM packet 5949831SN/A * @param size The size of the DRAM packet in bytes 5959966SN/A * @param isRead Is the request for a read or a write to DRAM 5969243SN/A * @return A DRAMPacket pointer with the decoded information 5979243SN/A */ 59810143SN/A DRAMPacket* decodeAddr(PacketPtr pkt, Addr dramPktAddr, unsigned int size, 59910143SN/A bool isRead); 6009243SN/A 6019243SN/A /** 60210206Sandreas.hansson@arm.com * The memory schduler/arbiter - picks which request needs to 6039567SN/A * go next, based on the specified policy such as FCFS or FR-FCFS 60410206Sandreas.hansson@arm.com * and moves it to the head of the queue. 60510393Swendy.elsasser@arm.com * Prioritizes accesses to the same rank as previous burst unless 60610393Swendy.elsasser@arm.com * controller is switching command type. 60710393Swendy.elsasser@arm.com * 60810393Swendy.elsasser@arm.com * @param queue Queued requests to consider 60910890Swendy.elsasser@arm.com * @param extra_col_delay Any extra delay due to a read/write switch 61010618SOmar.Naji@arm.com * @return true if a packet is scheduled to a rank which is available else 61110618SOmar.Naji@arm.com * false 6129243SN/A */ 61310890Swendy.elsasser@arm.com bool chooseNext(std::deque<DRAMPacket*>& queue, Tick extra_col_delay); 6149243SN/A 6159243SN/A /** 6169974SN/A * For FR-FCFS policy reorder the read/write queue depending on row buffer 61710890Swendy.elsasser@arm.com * hits and earliest bursts available in DRAM 61810393Swendy.elsasser@arm.com * 61910393Swendy.elsasser@arm.com * @param queue Queued requests to consider 62010890Swendy.elsasser@arm.com * @param extra_col_delay Any extra delay due to a read/write switch 62110618SOmar.Naji@arm.com * @return true if a packet is scheduled to a rank which is available else 62210618SOmar.Naji@arm.com * false 6239974SN/A */ 62410890Swendy.elsasser@arm.com bool reorderQueue(std::deque<DRAMPacket*>& queue, Tick extra_col_delay); 6259974SN/A 6269974SN/A /** 62710211Sandreas.hansson@arm.com * Find which are the earliest banks ready to issue an activate 62810211Sandreas.hansson@arm.com * for the enqueued requests. Assumes maximum of 64 banks per DIMM 62910393Swendy.elsasser@arm.com * Also checks if the bank is already prepped. 6309967SN/A * 63110393Swendy.elsasser@arm.com * @param queue Queued requests to consider 63210890Swendy.elsasser@arm.com * @param time of seamless burst command 6339967SN/A * @return One-hot encoded mask of bank indices 63410890Swendy.elsasser@arm.com * @return boolean indicating burst can issue seamlessly, with no gaps 6359967SN/A */ 63610890Swendy.elsasser@arm.com std::pair<uint64_t, bool> minBankPrep(const std::deque<DRAMPacket*>& queue, 63710890Swendy.elsasser@arm.com Tick min_col_at) const; 6389488SN/A 6399488SN/A /** 6409488SN/A * Keep track of when row activations happen, in order to enforce 6419488SN/A * the maximum number of activations in the activation window. The 6429488SN/A * method updates the time that the banks become available based 6439488SN/A * on the current limits. 64410210Sandreas.hansson@arm.com * 64510618SOmar.Naji@arm.com * @param rank_ref Reference to the rank 64610618SOmar.Naji@arm.com * @param bank_ref Reference to the bank 64710210Sandreas.hansson@arm.com * @param act_tick Time when the activation takes place 64810210Sandreas.hansson@arm.com * @param row Index of the row 6499488SN/A */ 65010618SOmar.Naji@arm.com void activateBank(Rank& rank_ref, Bank& bank_ref, Tick act_tick, 65110618SOmar.Naji@arm.com uint32_t row); 65210207Sandreas.hansson@arm.com 65310207Sandreas.hansson@arm.com /** 65410207Sandreas.hansson@arm.com * Precharge a given bank and also update when the precharge is 65510207Sandreas.hansson@arm.com * done. This will also deal with any stats related to the 65610207Sandreas.hansson@arm.com * accesses to the open page. 65710207Sandreas.hansson@arm.com * 65810618SOmar.Naji@arm.com * @param rank_ref The rank to precharge 65910247Sandreas.hansson@arm.com * @param bank_ref The bank to precharge 66010211Sandreas.hansson@arm.com * @param pre_at Time when the precharge takes place 66110247Sandreas.hansson@arm.com * @param trace Is this an auto precharge then do not add to trace 66210207Sandreas.hansson@arm.com */ 66310618SOmar.Naji@arm.com void prechargeBank(Rank& rank_ref, Bank& bank_ref, 66410618SOmar.Naji@arm.com Tick pre_at, bool trace = true); 6659488SN/A 66610143SN/A /** 66710143SN/A * Used for debugging to observe the contents of the queues. 66810143SN/A */ 6699243SN/A void printQs() const; 6709243SN/A 6719243SN/A /** 67210889Sandreas.hansson@arm.com * Burst-align an address. 67310889Sandreas.hansson@arm.com * 67410889Sandreas.hansson@arm.com * @param addr The potentially unaligned address 67510889Sandreas.hansson@arm.com * 67610889Sandreas.hansson@arm.com * @return An address aligned to a DRAM burst 67710889Sandreas.hansson@arm.com */ 67810889Sandreas.hansson@arm.com Addr burstAlign(Addr addr) const { return (addr & ~(Addr(burstSize - 1))); } 67910889Sandreas.hansson@arm.com 68010889Sandreas.hansson@arm.com /** 6819243SN/A * The controller's main read and write queues 6829243SN/A */ 6839833SN/A std::deque<DRAMPacket*> readQueue; 6849833SN/A std::deque<DRAMPacket*> writeQueue; 6859243SN/A 6869243SN/A /** 68710889Sandreas.hansson@arm.com * To avoid iterating over the write queue to check for 68810889Sandreas.hansson@arm.com * overlapping transactions, maintain a set of burst addresses 68910889Sandreas.hansson@arm.com * that are currently queued. Since we merge writes to the same 69010889Sandreas.hansson@arm.com * location we never have more than one address to the same burst 69110889Sandreas.hansson@arm.com * address. 69210889Sandreas.hansson@arm.com */ 69310889Sandreas.hansson@arm.com std::unordered_set<Addr> isInWriteQueue; 69410889Sandreas.hansson@arm.com 69510889Sandreas.hansson@arm.com /** 6969243SN/A * Response queue where read packets wait after we're done working 6979567SN/A * with them, but it's not time to send the response yet. The 6989567SN/A * responses are stored seperately mostly to keep the code clean 6999567SN/A * and help with events scheduling. For all logical purposes such 7009567SN/A * as sizing the read queue, this and the main read queue need to 7019567SN/A * be added together. 7029243SN/A */ 7039833SN/A std::deque<DRAMPacket*> respQueue; 7049243SN/A 7059567SN/A /** 70610618SOmar.Naji@arm.com * Vector of ranks 7079243SN/A */ 70810618SOmar.Naji@arm.com std::vector<Rank*> ranks; 7099243SN/A 7109243SN/A /** 7119243SN/A * The following are basic design parameters of the memory 7129831SN/A * controller, and are initialized based on parameter values. 7139831SN/A * The rowsPerBank is determined based on the capacity, number of 7149831SN/A * ranks and banks, the burst size, and the row buffer size. 7159243SN/A */ 71610489SOmar.Naji@arm.com const uint32_t deviceSize; 7179831SN/A const uint32_t deviceBusWidth; 7189831SN/A const uint32_t burstLength; 7199831SN/A const uint32_t deviceRowBufferSize; 7209831SN/A const uint32_t devicesPerRank; 7219831SN/A const uint32_t burstSize; 7229831SN/A const uint32_t rowBufferSize; 72310140SN/A const uint32_t columnsPerRowBuffer; 72410286Sandreas.hansson@arm.com const uint32_t columnsPerStripe; 7259243SN/A const uint32_t ranksPerChannel; 72610394Swendy.elsasser@arm.com const uint32_t bankGroupsPerRank; 72710394Swendy.elsasser@arm.com const bool bankGroupArch; 7289243SN/A const uint32_t banksPerRank; 7299566SN/A const uint32_t channels; 7309243SN/A uint32_t rowsPerBank; 7319243SN/A const uint32_t readBufferSize; 7329243SN/A const uint32_t writeBufferSize; 73310140SN/A const uint32_t writeHighThreshold; 73410140SN/A const uint32_t writeLowThreshold; 73510140SN/A const uint32_t minWritesPerSwitch; 73610140SN/A uint32_t writesThisTime; 73710147Sandreas.hansson@arm.com uint32_t readsThisTime; 7389243SN/A 7399243SN/A /** 7409243SN/A * Basic memory timing parameters initialized based on parameter 7419243SN/A * values. 7429243SN/A */ 74310286Sandreas.hansson@arm.com const Tick M5_CLASS_VAR_USED tCK; 7449243SN/A const Tick tWTR; 74510206Sandreas.hansson@arm.com const Tick tRTW; 74610393Swendy.elsasser@arm.com const Tick tCS; 7479243SN/A const Tick tBURST; 74810394Swendy.elsasser@arm.com const Tick tCCD_L; 7499243SN/A const Tick tRCD; 7509243SN/A const Tick tCL; 7519243SN/A const Tick tRP; 7529963SN/A const Tick tRAS; 75310210Sandreas.hansson@arm.com const Tick tWR; 75410212Sandreas.hansson@arm.com const Tick tRTP; 7559243SN/A const Tick tRFC; 7569243SN/A const Tick tREFI; 7579971SN/A const Tick tRRD; 75810394Swendy.elsasser@arm.com const Tick tRRD_L; 7599488SN/A const Tick tXAW; 76011673SOmar.Naji@arm.com const Tick tXP; 76111673SOmar.Naji@arm.com const Tick tXS; 7629488SN/A const uint32_t activationLimit; 7639243SN/A 7649243SN/A /** 7659243SN/A * Memory controller configuration initialized based on parameter 7669243SN/A * values. 7679243SN/A */ 7689243SN/A Enums::MemSched memSchedPolicy; 7699243SN/A Enums::AddrMap addrMapping; 7709243SN/A Enums::PageManage pageMgmt; 7719243SN/A 7729243SN/A /** 77310141SN/A * Max column accesses (read and write) per row, before forefully 77410141SN/A * closing it. 77510141SN/A */ 77610141SN/A const uint32_t maxAccessesPerRow; 77710141SN/A 77810141SN/A /** 7799726SN/A * Pipeline latency of the controller frontend. The frontend 7809726SN/A * contribution is added to writes (that complete when they are in 7819726SN/A * the write buffer) and reads that are serviced the write buffer. 7829726SN/A */ 7839726SN/A const Tick frontendLatency; 7849726SN/A 7859726SN/A /** 7869726SN/A * Pipeline latency of the backend and PHY. Along with the 7879726SN/A * frontend contribution, this latency is added to reads serviced 7889726SN/A * by the DRAM. 7899726SN/A */ 7909726SN/A const Tick backendLatency; 7919726SN/A 7929726SN/A /** 7939243SN/A * Till when has the main data bus been spoken for already? 7949243SN/A */ 7959243SN/A Tick busBusyUntil; 7969243SN/A 7979243SN/A Tick prevArrival; 7989243SN/A 79910206Sandreas.hansson@arm.com /** 80010206Sandreas.hansson@arm.com * The soonest you have to start thinking about the next request 80110206Sandreas.hansson@arm.com * is the longest access time that can occur before 80210206Sandreas.hansson@arm.com * busBusyUntil. Assuming you need to precharge, open a new row, 80310206Sandreas.hansson@arm.com * and access, it is tRP + tRCD + tCL. 80410206Sandreas.hansson@arm.com */ 80510206Sandreas.hansson@arm.com Tick nextReqTime; 8069972SN/A 8079243SN/A // All statistics that the model needs to capture 8089243SN/A Stats::Scalar readReqs; 8099243SN/A Stats::Scalar writeReqs; 8109831SN/A Stats::Scalar readBursts; 8119831SN/A Stats::Scalar writeBursts; 8129975SN/A Stats::Scalar bytesReadDRAM; 8139975SN/A Stats::Scalar bytesReadWrQ; 8149243SN/A Stats::Scalar bytesWritten; 8159977SN/A Stats::Scalar bytesReadSys; 8169977SN/A Stats::Scalar bytesWrittenSys; 8179243SN/A Stats::Scalar servicedByWrQ; 8189977SN/A Stats::Scalar mergedWrBursts; 8199243SN/A Stats::Scalar neitherReadNorWrite; 8209977SN/A Stats::Vector perBankRdBursts; 8219977SN/A Stats::Vector perBankWrBursts; 8229243SN/A Stats::Scalar numRdRetry; 8239243SN/A Stats::Scalar numWrRetry; 8249243SN/A Stats::Scalar totGap; 8259243SN/A Stats::Vector readPktSize; 8269243SN/A Stats::Vector writePktSize; 8279243SN/A Stats::Vector rdQLenPdf; 8289243SN/A Stats::Vector wrQLenPdf; 8299727SN/A Stats::Histogram bytesPerActivate; 83010147Sandreas.hansson@arm.com Stats::Histogram rdPerTurnAround; 83110147Sandreas.hansson@arm.com Stats::Histogram wrPerTurnAround; 8329243SN/A 8339243SN/A // Latencies summed over all requests 8349243SN/A Stats::Scalar totQLat; 8359243SN/A Stats::Scalar totMemAccLat; 8369243SN/A Stats::Scalar totBusLat; 8379243SN/A 8389243SN/A // Average latencies per request 8399243SN/A Stats::Formula avgQLat; 8409243SN/A Stats::Formula avgBusLat; 8419243SN/A Stats::Formula avgMemAccLat; 8429243SN/A 8439243SN/A // Average bandwidth 8449243SN/A Stats::Formula avgRdBW; 8459243SN/A Stats::Formula avgWrBW; 8469977SN/A Stats::Formula avgRdBWSys; 8479977SN/A Stats::Formula avgWrBWSys; 8489243SN/A Stats::Formula peakBW; 8499243SN/A Stats::Formula busUtil; 8509975SN/A Stats::Formula busUtilRead; 8519975SN/A Stats::Formula busUtilWrite; 8529243SN/A 8539243SN/A // Average queue lengths 8549243SN/A Stats::Average avgRdQLen; 8559243SN/A Stats::Average avgWrQLen; 8569243SN/A 8579243SN/A // Row hit count and rate 8589243SN/A Stats::Scalar readRowHits; 8599243SN/A Stats::Scalar writeRowHits; 8609243SN/A Stats::Formula readRowHitRate; 8619243SN/A Stats::Formula writeRowHitRate; 8629243SN/A Stats::Formula avgGap; 8639243SN/A 8649975SN/A // DRAM Power Calculation 8659975SN/A Stats::Formula pageHitRate; 8669975SN/A 86710393Swendy.elsasser@arm.com // Holds the value of the rank of burst issued 86810393Swendy.elsasser@arm.com uint8_t activeRank; 86910393Swendy.elsasser@arm.com 87010432SOmar.Naji@arm.com // timestamp offset 87110432SOmar.Naji@arm.com uint64_t timeStampOffset; 87210432SOmar.Naji@arm.com 87311190Sandreas.hansson@arm.com /** 87411190Sandreas.hansson@arm.com * Upstream caches need this packet until true is returned, so 87511190Sandreas.hansson@arm.com * hold it for deletion until a subsequent call 8769349SN/A */ 87711190Sandreas.hansson@arm.com std::unique_ptr<Packet> pendingDelete; 8789349SN/A 87910432SOmar.Naji@arm.com /** 88010618SOmar.Naji@arm.com * This function increments the energy when called. If stats are 88110618SOmar.Naji@arm.com * dumped periodically, note accumulated energy values will 88210618SOmar.Naji@arm.com * appear in the stats (even if the stats are reset). This is a 88310618SOmar.Naji@arm.com * result of the energy values coming from DRAMPower, and there 88410618SOmar.Naji@arm.com * is currently no support for resetting the state. 88510618SOmar.Naji@arm.com * 88610618SOmar.Naji@arm.com * @param rank Currrent rank 88710618SOmar.Naji@arm.com */ 88810618SOmar.Naji@arm.com void updatePowerStats(Rank& rank_ref); 88910432SOmar.Naji@arm.com 89010432SOmar.Naji@arm.com /** 89111675Swendy.elsasser@arm.com * Function for sorting Command structures based on timeStamp 89210432SOmar.Naji@arm.com * 89311675Swendy.elsasser@arm.com * @param a Memory Command 89411675Swendy.elsasser@arm.com * @param next Memory Command 89511675Swendy.elsasser@arm.com * @return true if timeStamp of Command 1 < timeStamp of Command 2 89610432SOmar.Naji@arm.com */ 89711675Swendy.elsasser@arm.com static bool sortTime(const Command& cmd, const Command& cmd_next) { 89811675Swendy.elsasser@arm.com return cmd.timeStamp < cmd_next.timeStamp; 89910432SOmar.Naji@arm.com }; 90010432SOmar.Naji@arm.com 9019243SN/A public: 9029243SN/A 90311169Sandreas.hansson@arm.com void regStats() override; 9049243SN/A 90510146Sandreas.hansson@arm.com DRAMCtrl(const DRAMCtrlParams* p); 9069243SN/A 90711168Sandreas.hansson@arm.com DrainState drain() override; 9089243SN/A 9099294SN/A virtual BaseSlavePort& getSlavePort(const std::string& if_name, 91011169Sandreas.hansson@arm.com PortID idx = InvalidPortID) override; 9119243SN/A 91211168Sandreas.hansson@arm.com virtual void init() override; 91311168Sandreas.hansson@arm.com virtual void startup() override; 91411168Sandreas.hansson@arm.com virtual void drainResume() override; 9159243SN/A 9169243SN/A protected: 9179243SN/A 9189243SN/A Tick recvAtomic(PacketPtr pkt); 9199243SN/A void recvFunctional(PacketPtr pkt); 9209243SN/A bool recvTimingReq(PacketPtr pkt); 9219243SN/A 9229243SN/A}; 9239243SN/A 92410146Sandreas.hansson@arm.com#endif //__MEM_DRAM_CTRL_HH__ 925