write_queue.cc revision 12727
111375Sandreas.hansson@arm.com/* 211375Sandreas.hansson@arm.com * Copyright (c) 2012-2013, 2015-2016 ARM Limited 311375Sandreas.hansson@arm.com * All rights reserved. 411375Sandreas.hansson@arm.com * 511375Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall 611375Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual 711375Sandreas.hansson@arm.com * property including but not limited to intellectual property relating 811375Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software 911375Sandreas.hansson@arm.com * licensed hereunder. You may use the software subject to the license 1011375Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated 1111375Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software, 1211375Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form. 1311375Sandreas.hansson@arm.com * 1411375Sandreas.hansson@arm.com * Copyright (c) 2003-2005 The Regents of The University of Michigan 1511375Sandreas.hansson@arm.com * All rights reserved. 1611375Sandreas.hansson@arm.com * 1711375Sandreas.hansson@arm.com * Redistribution and use in source and binary forms, with or without 1811375Sandreas.hansson@arm.com * modification, are permitted provided that the following conditions are 1911375Sandreas.hansson@arm.com * met: redistributions of source code must retain the above copyright 2011375Sandreas.hansson@arm.com * notice, this list of conditions and the following disclaimer; 2111375Sandreas.hansson@arm.com * redistributions in binary form must reproduce the above copyright 2211375Sandreas.hansson@arm.com * notice, this list of conditions and the following disclaimer in the 2311375Sandreas.hansson@arm.com * documentation and/or other materials provided with the distribution; 2411375Sandreas.hansson@arm.com * neither the name of the copyright holders nor the names of its 2511375Sandreas.hansson@arm.com * contributors may be used to endorse or promote products derived from 2611375Sandreas.hansson@arm.com * this software without specific prior written permission. 2711375Sandreas.hansson@arm.com * 2811375Sandreas.hansson@arm.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2911375Sandreas.hansson@arm.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 3011375Sandreas.hansson@arm.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 3111375Sandreas.hansson@arm.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 3211375Sandreas.hansson@arm.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 3311375Sandreas.hansson@arm.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3411375Sandreas.hansson@arm.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3511375Sandreas.hansson@arm.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3611375Sandreas.hansson@arm.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3711375Sandreas.hansson@arm.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3811375Sandreas.hansson@arm.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3911375Sandreas.hansson@arm.com * 4011375Sandreas.hansson@arm.com * Authors: Erik Hallnor 4111375Sandreas.hansson@arm.com * Andreas Sandberg 4211375Sandreas.hansson@arm.com * Andreas Hansson 4311375Sandreas.hansson@arm.com */ 4411375Sandreas.hansson@arm.com 4511375Sandreas.hansson@arm.com/** @file 4611375Sandreas.hansson@arm.com * Definition of WriteQueue class functions. 4711375Sandreas.hansson@arm.com */ 4811375Sandreas.hansson@arm.com 4911375Sandreas.hansson@arm.com#include "mem/cache/write_queue.hh" 5011375Sandreas.hansson@arm.com 5112727Snikos.nikoleris@arm.com#include <cassert> 5212727Snikos.nikoleris@arm.com 5312727Snikos.nikoleris@arm.com#include "mem/cache/write_queue_entry.hh" 5412727Snikos.nikoleris@arm.com 5511375Sandreas.hansson@arm.comWriteQueue::WriteQueue(const std::string &_label, 5611375Sandreas.hansson@arm.com int num_entries, int reserve) 5711375Sandreas.hansson@arm.com : Queue<WriteQueueEntry>(_label, num_entries, reserve) 5811375Sandreas.hansson@arm.com{} 5911375Sandreas.hansson@arm.com 6011375Sandreas.hansson@arm.comWriteQueueEntry * 6111375Sandreas.hansson@arm.comWriteQueue::allocate(Addr blk_addr, unsigned blk_size, PacketPtr pkt, 6211375Sandreas.hansson@arm.com Tick when_ready, Counter order) 6311375Sandreas.hansson@arm.com{ 6411375Sandreas.hansson@arm.com assert(!freeList.empty()); 6511375Sandreas.hansson@arm.com WriteQueueEntry *entry = freeList.front(); 6611375Sandreas.hansson@arm.com assert(entry->getNumTargets() == 0); 6711375Sandreas.hansson@arm.com freeList.pop_front(); 6811375Sandreas.hansson@arm.com 6911375Sandreas.hansson@arm.com entry->allocate(blk_addr, blk_size, pkt, when_ready, order); 7011375Sandreas.hansson@arm.com entry->allocIter = allocatedList.insert(allocatedList.end(), entry); 7111375Sandreas.hansson@arm.com entry->readyIter = addToReadyList(entry); 7211375Sandreas.hansson@arm.com 7311375Sandreas.hansson@arm.com allocated += 1; 7411375Sandreas.hansson@arm.com return entry; 7511375Sandreas.hansson@arm.com} 7611375Sandreas.hansson@arm.com 7711375Sandreas.hansson@arm.comvoid 7811375Sandreas.hansson@arm.comWriteQueue::markInService(WriteQueueEntry *entry) 7911375Sandreas.hansson@arm.com{ 8011453Sandreas.hansson@arm.com // for a normal eviction, such as a writeback or a clean evict, 8111453Sandreas.hansson@arm.com // there is no more to do as we are done from the perspective of 8211453Sandreas.hansson@arm.com // this cache, and for uncacheable write we do not need the entry 8311453Sandreas.hansson@arm.com // as part of the response handling 8411453Sandreas.hansson@arm.com entry->popTarget(); 8511453Sandreas.hansson@arm.com deallocate(entry); 8611375Sandreas.hansson@arm.com} 87