write_queue.cc revision 12727
12810SN/A/*
29725Sandreas.hansson@arm.com * Copyright (c) 2012-2013, 2015-2016 ARM Limited
39347SAndreas.Sandberg@arm.com * All rights reserved.
49347SAndreas.Sandberg@arm.com *
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79347SAndreas.Sandberg@arm.com * property including but not limited to intellectual property relating
89347SAndreas.Sandberg@arm.com * to a hardware implementation of the functionality of the software
99347SAndreas.Sandberg@arm.com * licensed hereunder.  You may use the software subject to the license
109347SAndreas.Sandberg@arm.com * terms below provided that you ensure that this notice is replicated
119347SAndreas.Sandberg@arm.com * unmodified and in its entirety in all distributions of the software,
129347SAndreas.Sandberg@arm.com * modified or unmodified, in source code or in binary form.
139347SAndreas.Sandberg@arm.com *
142810SN/A * Copyright (c) 2003-2005 The Regents of The University of Michigan
152810SN/A * All rights reserved.
162810SN/A *
172810SN/A * Redistribution and use in source and binary forms, with or without
182810SN/A * modification, are permitted provided that the following conditions are
192810SN/A * met: redistributions of source code must retain the above copyright
202810SN/A * notice, this list of conditions and the following disclaimer;
212810SN/A * redistributions in binary form must reproduce the above copyright
222810SN/A * notice, this list of conditions and the following disclaimer in the
232810SN/A * documentation and/or other materials provided with the distribution;
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262810SN/A * this software without specific prior written permission.
272810SN/A *
282810SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
292810SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
302810SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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392810SN/A *
402810SN/A * Authors: Erik Hallnor
419347SAndreas.Sandberg@arm.com *          Andreas Sandberg
422810SN/A *          Andreas Hansson
432810SN/A */
442810SN/A
454626SN/A/** @file
462810SN/A * Definition of WriteQueue class functions.
472810SN/A */
4810509SAli.Saidi@ARM.com
495338Sstever@gmail.com#include "mem/cache/write_queue.hh"
5010509SAli.Saidi@ARM.com
512810SN/A#include <cassert>
522810SN/A
532810SN/A#include "mem/cache/write_queue_entry.hh"
545314SN/A
555314SN/AWriteQueue::WriteQueue(const std::string &_label,
569725Sandreas.hansson@arm.com                       int num_entries, int reserve)
579725Sandreas.hansson@arm.com    : Queue<WriteQueueEntry>(_label, num_entries, reserve)
589725Sandreas.hansson@arm.com{}
592810SN/A
604626SN/AWriteQueueEntry *
614626SN/AWriteQueue::allocate(Addr blk_addr, unsigned blk_size, PacketPtr pkt,
622810SN/A                    Tick when_ready, Counter order)
632810SN/A{
642810SN/A    assert(!freeList.empty());
652810SN/A    WriteQueueEntry *entry = freeList.front();
664626SN/A    assert(entry->getNumTargets() == 0);
6710028SGiacomo.Gabrielli@arm.com    freeList.pop_front();
682810SN/A
692810SN/A    entry->allocate(blk_addr, blk_size, pkt, when_ready, order);
702810SN/A    entry->allocIter = allocatedList.insert(allocatedList.end(), entry);
712810SN/A    entry->readyIter = addToReadyList(entry);
722810SN/A
7310028SGiacomo.Gabrielli@arm.com    allocated += 1;
742810SN/A    return entry;
752810SN/A}
762810SN/A
772810SN/Avoid
782810SN/AWriteQueue::markInService(WriteQueueEntry *entry)
792810SN/A{
802810SN/A    // for a normal eviction, such as a writeback or a clean evict,
8110028SGiacomo.Gabrielli@arm.com    // there is no more to do as we are done from the perspective of
822810SN/A    // this cache, and for uncacheable write we do not need the entry
832810SN/A    // as part of the response handling
842810SN/A    entry->popTarget();
852810SN/A    deallocate(entry);
862810SN/A}
872810SN/A