noncoherent_cache.hh revision 13017
12083SN/A/* 22083SN/A * Copyright (c) 2012-2018 ARM Limited 32754Sksewell@umich.edu * All rights reserved. 42083SN/A * 52083SN/A * The license below extends only to copyright in the software and shall 62083SN/A * not be construed as granting a license to any other intellectual 72083SN/A * property including but not limited to intellectual property relating 82083SN/A * to a hardware implementation of the functionality of the software 92083SN/A * licensed hereunder. You may use the software subject to the license 102083SN/A * terms below provided that you ensure that this notice is replicated 112083SN/A * unmodified and in its entirety in all distributions of the software, 122083SN/A * modified or unmodified, in source code or in binary form. 132083SN/A * 142083SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 152083SN/A * All rights reserved. 162083SN/A * 172083SN/A * Redistribution and use in source and binary forms, with or without 182083SN/A * modification, are permitted provided that the following conditions are 192083SN/A * met: redistributions of source code must retain the above copyright 202083SN/A * notice, this list of conditions and the following disclaimer; 212083SN/A * redistributions in binary form must reproduce the above copyright 222083SN/A * notice, this list of conditions and the following disclaimer in the 232083SN/A * documentation and/or other materials provided with the distribution; 242083SN/A * neither the name of the copyright holders nor the names of its 252083SN/A * contributors may be used to endorse or promote products derived from 262083SN/A * this software without specific prior written permission. 272083SN/A * 282665Ssaidi@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292665Ssaidi@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302083SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312649Ssaidi@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322649Ssaidi@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332649Ssaidi@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342649Ssaidi@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352649Ssaidi@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362495SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372686Sksewell@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382686Sksewell@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392686Sksewell@umich.edu * 402686Sksewell@umich.edu * Authors: Erik Hallnor 412686Sksewell@umich.edu * Dave Greene 422686Sksewell@umich.edu * Steve Reinhardt 432686Sksewell@umich.edu * Ron Dreslinski 442686Sksewell@umich.edu * Andreas Hansson 452686Sksewell@umich.edu * Nikos Nikoleris 462686Sksewell@umich.edu */ 472686Sksewell@umich.edu 482686Sksewell@umich.edu/** 492686Sksewell@umich.edu * @file 502686Sksewell@umich.edu * Specifies a non-coherent cache. The non-coherent cache is expected 512686Sksewell@umich.edu * to be located below the point of coherency. All valid blocks in the 522495SN/A * non-coherent cache can always be written to without any prior 532495SN/A * invalidations or snoops. 5412616Sgabeblack@google.com */ 552495SN/A 5612616Sgabeblack@google.com#ifndef __MEM_CACHE_NONCOHERENT_CACHE_HH__ 5712616Sgabeblack@google.com#define __MEM_CACHE_NONCOHERENT_CACHE_HH__ 582686Sksewell@umich.edu 592686Sksewell@umich.edu#include "base/logging.hh" 602495SN/A#include "base/types.hh" 612686Sksewell@umich.edu#include "mem/cache/base.hh" 622083SN/A#include "mem/packet.hh" 632083SN/A 642083SN/Aclass CacheBlk; 652495SN/Aclass MSHR; 662495SN/Astruct NoncoherentCacheParams; 672083SN/A 682083SN/A/** 692083SN/A * A non-coherent cache 702083SN/A */ 712083SN/Aclass NoncoherentCache : public BaseCache 7212234Sgabeblack@google.com{ 732083SN/A protected: 7410474Sandreas.hansson@arm.com bool access(PacketPtr pkt, CacheBlk *&blk, Cycles &lat, 752083SN/A PacketList &writebacks) override; 762083SN/A 772083SN/A void handleTimingReqMiss(PacketPtr pkt, CacheBlk *blk, 782083SN/A Tick forward_time, 792083SN/A Tick request_time) override; 802083SN/A 812083SN/A void recvTimingReq(PacketPtr pkt) override; 82 83 void doWritebacks(PacketList& writebacks, 84 Tick forward_time) override; 85 86 void doWritebacksAtomic(PacketList& writebacks) override; 87 88 void serviceMSHRTargets(MSHR *mshr, const PacketPtr pkt, 89 CacheBlk *blk, PacketList& writebacks) override; 90 91 void recvTimingResp(PacketPtr pkt) override; 92 93 void recvTimingSnoopReq(PacketPtr pkt) override { 94 panic("Unexpected timing snoop request %s", pkt->print()); 95 } 96 97 void recvTimingSnoopResp(PacketPtr pkt) override { 98 panic("Unexpected timing snoop response %s", pkt->print()); 99 } 100 101 Cycles handleAtomicReqMiss(PacketPtr pkt, CacheBlk *&blk, 102 PacketList &writebacks) override; 103 104 Tick recvAtomic(PacketPtr pkt) override; 105 106 Tick recvAtomicSnoop(PacketPtr pkt) override { 107 panic("Unexpected atomic snoop request %s", pkt->print()); 108 } 109 110 void functionalAccess(PacketPtr pkt, bool from_cpu_side) override; 111 112 void satisfyRequest(PacketPtr pkt, CacheBlk *blk, 113 bool deferred_response = false, 114 bool pending_downgrade = false) override; 115 116 /* 117 * Creates a new packet with the request to be send to the memory 118 * below. The noncoherent cache is below the point of coherence 119 * and therefore all fills bring in writable, therefore the 120 * needs_writeble parameter is ignored. 121 */ 122 PacketPtr createMissPacket(PacketPtr cpu_pkt, CacheBlk *blk, 123 bool needs_writable) const override; 124 125 M5_NODISCARD PacketPtr evictBlock(CacheBlk *blk) override; 126 127 void evictBlock(CacheBlk *blk, PacketList &writebacks) override; 128 129 public: 130 NoncoherentCache(const NoncoherentCacheParams *p); 131}; 132 133#endif // __MEM_CACHE_NONCOHERENTCACHE_HH__ 134