mshr.hh revision 4665
12810SN/A/* 211375Sandreas.hansson@arm.com * Copyright (c) 2002-2005 The Regents of The University of Michigan 39663Suri.wiener@arm.com * All rights reserved. 49663Suri.wiener@arm.com * 59663Suri.wiener@arm.com * Redistribution and use in source and binary forms, with or without 69663Suri.wiener@arm.com * modification, are permitted provided that the following conditions are 79663Suri.wiener@arm.com * met: redistributions of source code must retain the above copyright 89663Suri.wiener@arm.com * notice, this list of conditions and the following disclaimer; 99663Suri.wiener@arm.com * redistributions in binary form must reproduce the above copyright 109663Suri.wiener@arm.com * notice, this list of conditions and the following disclaimer in the 119663Suri.wiener@arm.com * documentation and/or other materials provided with the distribution; 129663Suri.wiener@arm.com * neither the name of the copyright holders nor the names of its 139663Suri.wiener@arm.com * contributors may be used to endorse or promote products derived from 142810SN/A * this software without specific prior written permission. 152810SN/A * 162810SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172810SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182810SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192810SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202810SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212810SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222810SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232810SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242810SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252810SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262810SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272810SN/A * 282810SN/A * Authors: Erik Hallnor 292810SN/A */ 302810SN/A 312810SN/A/** 322810SN/A * @file 332810SN/A * Miss Status and Handling Register (MSHR) declaration. 342810SN/A */ 352810SN/A 362810SN/A#ifndef __MSHR_HH__ 372810SN/A#define __MSHR_HH__ 382810SN/A 392810SN/A#include <list> 402810SN/A 412810SN/A#include "mem/packet.hh" 422810SN/A 432810SN/Aclass CacheBlk; 442810SN/Aclass MSHRQueue; 452810SN/A 462810SN/A/** 472810SN/A * Miss Status and handling Register. This class keeps all the information 4810764Sandreas.hansson@arm.com * needed to handle a cache miss including a list of target requests. 4910764Sandreas.hansson@arm.com */ 502810SN/Aclass MSHR : public Packet::SenderState 514626SN/A{ 524626SN/A 535314SN/A public: 5411375Sandreas.hansson@arm.com 552810SN/A class Target { 5611375Sandreas.hansson@arm.com public: 572810SN/A Tick time; //!< Time when request was received (for stats) 582810SN/A PacketPtr pkt; //!< Pending request packet. 592810SN/A bool cpuSide; //!< Did request come from cpu side or mem side? 603374SN/A 619264Sdjordje.kovacevic@arm.com bool isCpuSide() { return cpuSide; } 622810SN/A 6311375Sandreas.hansson@arm.com Target(PacketPtr _pkt, bool _cpuSide, Tick _time = curTick) 644626SN/A : time(_time), pkt(_pkt), cpuSide(_cpuSide) 654626SN/A {} 669725Sandreas.hansson@arm.com }; 6711375Sandreas.hansson@arm.com 689725Sandreas.hansson@arm.com /** Defines the Data structure of the MSHR targetlist. */ 6911375Sandreas.hansson@arm.com typedef std::list<Target> TargetList; 7011375Sandreas.hansson@arm.com /** Target list iterator. */ 719725Sandreas.hansson@arm.com typedef std::list<Target>::iterator TargetListIterator; 729725Sandreas.hansson@arm.com /** A list of MSHRs. */ 739725Sandreas.hansson@arm.com typedef std::list<MSHR *> List; 749725Sandreas.hansson@arm.com /** MSHR list iterator. */ 759725Sandreas.hansson@arm.com typedef List::iterator Iterator; 769725Sandreas.hansson@arm.com /** MSHR list const_iterator. */ 779725Sandreas.hansson@arm.com typedef List::const_iterator ConstIterator; 7811284Sandreas.hansson@arm.com 7911284Sandreas.hansson@arm.com /** Pointer to queue containing this MSHR. */ 8011284Sandreas.hansson@arm.com MSHRQueue *queue; 8111284Sandreas.hansson@arm.com 8211284Sandreas.hansson@arm.com /** Address of the request. */ 8311284Sandreas.hansson@arm.com Addr addr; 8411284Sandreas.hansson@arm.com 8511284Sandreas.hansson@arm.com /** Size of the request. */ 8611284Sandreas.hansson@arm.com int size; 8711284Sandreas.hansson@arm.com 8811284Sandreas.hansson@arm.com /** True if the request has been sent to the bus. */ 8911284Sandreas.hansson@arm.com bool inService; 9011284Sandreas.hansson@arm.com 9111284Sandreas.hansson@arm.com /** True if we will be putting the returned block in the cache */ 9211284Sandreas.hansson@arm.com bool isCacheFill; 9311284Sandreas.hansson@arm.com /** True if we need to get an exclusive copy of the block. */ 9411284Sandreas.hansson@arm.com bool needsExclusive; 9511284Sandreas.hansson@arm.com 9611284Sandreas.hansson@arm.com /** True if the request is uncacheable */ 9711284Sandreas.hansson@arm.com bool _isUncacheable; 9811284Sandreas.hansson@arm.com 9911284Sandreas.hansson@arm.com bool deferredNeedsExclusive; 10011284Sandreas.hansson@arm.com bool pendingInvalidate; 10111284Sandreas.hansson@arm.com 10211284Sandreas.hansson@arm.com /** Thread number of the miss. */ 1039725Sandreas.hansson@arm.com short threadNum; 1049725Sandreas.hansson@arm.com /** The number of currently allocated targets. */ 1059725Sandreas.hansson@arm.com short ntargets; 1069725Sandreas.hansson@arm.com /** Order number of assigned by the miss queue. */ 1079725Sandreas.hansson@arm.com uint64_t order; 1089725Sandreas.hansson@arm.com 1099725Sandreas.hansson@arm.com /** 1102810SN/A * Pointer to this MSHR on the ready list. 1114626SN/A * @sa MissQueue, MSHRQueue::readyList 11211375Sandreas.hansson@arm.com */ 11311375Sandreas.hansson@arm.com Iterator readyIter; 11411375Sandreas.hansson@arm.com 1154626SN/A /** 1164626SN/A * Pointer to this MSHR on the allocated list. 1175875Ssteve.reinhardt@amd.com * @sa MissQueue, MSHRQueue::allocatedList 1185875Ssteve.reinhardt@amd.com */ 1195875Ssteve.reinhardt@amd.com Iterator allocIter; 1205875Ssteve.reinhardt@amd.com 1215875Ssteve.reinhardt@amd.comprivate: 1225875Ssteve.reinhardt@amd.com /** List of all requests that match the address */ 1235875Ssteve.reinhardt@amd.com TargetList targets; 12410766Sandreas.hansson@arm.com 12510766Sandreas.hansson@arm.com TargetList deferredTargets; 12610766Sandreas.hansson@arm.com 12710766Sandreas.hansson@arm.compublic: 12810766Sandreas.hansson@arm.com 12910766Sandreas.hansson@arm.com bool isUncacheable() { return _isUncacheable; } 13010766Sandreas.hansson@arm.com 1314626SN/A /** 1325318SN/A * Allocate a miss to this MSHR. 1335875Ssteve.reinhardt@amd.com * @param cmd The requesting command. 1347823Ssteve.reinhardt@amd.com * @param addr The address of the miss. 1355875Ssteve.reinhardt@amd.com * @param asid The address space id of the miss. 1364626SN/A * @param size The number of bytes to request. 1374626SN/A * @param pkt The original miss. 1384626SN/A */ 1394903SN/A void allocate(Addr addr, int size, PacketPtr pkt); 1404903SN/A 1414903SN/A /** 14211284Sandreas.hansson@arm.com * Allocate this MSHR as a buffer for the given request. 1434903SN/A * @param target The memory request to buffer. 1444903SN/A */ 1454903SN/A void allocateAsBuffer(PacketPtr target); 14611740Snikos.nikoleris@arm.com 14711740Snikos.nikoleris@arm.com /** 14811740Snikos.nikoleris@arm.com * Mark this MSHR as free. 14911740Snikos.nikoleris@arm.com */ 15011740Snikos.nikoleris@arm.com void deallocate(); 15111740Snikos.nikoleris@arm.com 15211740Snikos.nikoleris@arm.com /** 15311740Snikos.nikoleris@arm.com * Add a request to the list of targets. 15411740Snikos.nikoleris@arm.com * @param target The target. 15511740Snikos.nikoleris@arm.com */ 15611284Sandreas.hansson@arm.com void allocateTarget(PacketPtr target); 15711740Snikos.nikoleris@arm.com void allocateSnoopTarget(PacketPtr target); 15811740Snikos.nikoleris@arm.com 15911740Snikos.nikoleris@arm.com /** A simple constructor. */ 16011740Snikos.nikoleris@arm.com MSHR(); 16111740Snikos.nikoleris@arm.com /** A simple destructor. */ 16211740Snikos.nikoleris@arm.com ~MSHR(); 16311740Snikos.nikoleris@arm.com 16411740Snikos.nikoleris@arm.com /** 16511740Snikos.nikoleris@arm.com * Returns the current number of allocated targets. 16611284Sandreas.hansson@arm.com * @return The current number of allocated targets. 1675318SN/A */ 1685875Ssteve.reinhardt@amd.com int getNumTargets() { return ntargets; } 16911357Sstephan.diestelhorst@arm.com 17011357Sstephan.diestelhorst@arm.com /** 17111357Sstephan.diestelhorst@arm.com * Returns a pointer to the target list. 17211357Sstephan.diestelhorst@arm.com * @return a pointer to the target list. 17311357Sstephan.diestelhorst@arm.com */ 1744903SN/A TargetList* getTargetList() { return &targets; } 17511357Sstephan.diestelhorst@arm.com 1764908SN/A /** 1774920SN/A * Returns a reference to the first target. 1785314SN/A * @return A pointer to the first target. 1795314SN/A */ 1804903SN/A Target *getTarget() { return &targets.front(); } 1814903SN/A 1822810SN/A /** 1832810SN/A * Pop first target. 1842810SN/A */ 1852810SN/A void popTarget() 1864903SN/A { 18711197Sandreas.hansson@arm.com --ntargets; 18811197Sandreas.hansson@arm.com targets.pop_front(); 18911197Sandreas.hansson@arm.com } 1907667Ssteve.reinhardt@amd.com 1917667Ssteve.reinhardt@amd.com /** 1927667Ssteve.reinhardt@amd.com * Returns true if there are targets left. 1937667Ssteve.reinhardt@amd.com * @return true if there are targets 1947667Ssteve.reinhardt@amd.com */ 19511284Sandreas.hansson@arm.com bool hasTargets() { return !targets.empty(); } 19611284Sandreas.hansson@arm.com 1979725Sandreas.hansson@arm.com bool isSimpleForward() 19811284Sandreas.hansson@arm.com { 19911284Sandreas.hansson@arm.com if (getNumTargets() != 1) 2007667Ssteve.reinhardt@amd.com return false; 2017667Ssteve.reinhardt@amd.com Target *tgt = getTarget(); 2027667Ssteve.reinhardt@amd.com return tgt->isCpuSide() && !tgt->pkt->needsResponse(); 2037667Ssteve.reinhardt@amd.com } 2047667Ssteve.reinhardt@amd.com 2057667Ssteve.reinhardt@amd.com bool promoteDeferredTargets(); 2067667Ssteve.reinhardt@amd.com 2077667Ssteve.reinhardt@amd.com /** 2087667Ssteve.reinhardt@amd.com * Prints the contents of this MSHR to stderr. 2094665SN/A */ 21011375Sandreas.hansson@arm.com void dump(); 21111375Sandreas.hansson@arm.com}; 2129725Sandreas.hansson@arm.com 2134668SN/A#endif //__MSHR_HH__ 2142810SN/A