mshr.hh revision 4665 
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Erik Hallnor
29 */
30
31/**
32 * @file
33 * Miss Status and Handling Register (MSHR) declaration.
34 */
35
36#ifndef __MSHR_HH__
37#define __MSHR_HH__
38
39#include <list>
40
41#include "mem/packet.hh"
42
43class CacheBlk;
44class MSHRQueue;
45
46/**
47 * Miss Status and handling Register. This class keeps all the information
48 * needed to handle a cache miss including a list of target requests.
49 */
50class MSHR : public Packet::SenderState
51{
52
53  public:
54
55    class Target {
56      public:
57        Tick time;      //!< Time when request was received (for stats)
58        PacketPtr pkt;  //!< Pending request packet.
59        bool cpuSide;   //!< Did request come from cpu side or mem side?
60
61        bool isCpuSide() { return cpuSide; }
62
63        Target(PacketPtr _pkt, bool _cpuSide, Tick _time = curTick)
64            : time(_time), pkt(_pkt), cpuSide(_cpuSide)
65        {}
66    };
67
68    /** Defines the Data structure of the MSHR targetlist. */
69    typedef std::list<Target> TargetList;
70    /** Target list iterator. */
71    typedef std::list<Target>::iterator TargetListIterator;
72    /** A list of MSHRs. */
73    typedef std::list<MSHR *> List;
74    /** MSHR list iterator. */
75    typedef List::iterator Iterator;
76    /** MSHR list const_iterator. */
77    typedef List::const_iterator ConstIterator;
78
79    /** Pointer to queue containing this MSHR. */
80    MSHRQueue *queue;
81
82    /** Address of the request. */
83    Addr addr;
84
85    /** Size of the request. */
86    int size;
87
88    /** True if the request has been sent to the bus. */
89    bool inService;
90
91    /** True if we will be putting the returned block in the cache */
92    bool isCacheFill;
93    /** True if we need to get an exclusive copy of the block. */
94    bool needsExclusive;
95
96    /** True if the request is uncacheable */
97    bool _isUncacheable;
98
99    bool deferredNeedsExclusive;
100    bool pendingInvalidate;
101
102    /** Thread number of the miss. */
103    short threadNum;
104    /** The number of currently allocated targets. */
105    short ntargets;
106    /** Order number of assigned by the miss queue. */
107    uint64_t order;
108
109    /**
110     * Pointer to this MSHR on the ready list.
111     * @sa MissQueue, MSHRQueue::readyList
112     */
113    Iterator readyIter;
114
115    /**
116     * Pointer to this MSHR on the allocated list.
117     * @sa MissQueue, MSHRQueue::allocatedList
118     */
119    Iterator allocIter;
120
121private:
122    /** List of all requests that match the address */
123    TargetList targets;
124
125    TargetList deferredTargets;
126
127public:
128
129    bool isUncacheable() { return _isUncacheable; }
130
131    /**
132     * Allocate a miss to this MSHR.
133     * @param cmd The requesting command.
134     * @param addr The address of the miss.
135     * @param asid The address space id of the miss.
136     * @param size The number of bytes to request.
137     * @param pkt  The original miss.
138     */
139    void allocate(Addr addr, int size, PacketPtr pkt);
140
141    /**
142     * Allocate this MSHR as a buffer for the given request.
143     * @param target The memory request to buffer.
144     */
145    void allocateAsBuffer(PacketPtr target);
146
147    /**
148     * Mark this MSHR as free.
149     */
150    void deallocate();
151
152    /**
153     * Add a request to the list of targets.
154     * @param target The target.
155     */
156    void allocateTarget(PacketPtr target);
157    void allocateSnoopTarget(PacketPtr target);
158
159    /** A simple constructor. */
160    MSHR();
161    /** A simple destructor. */
162    ~MSHR();
163
164    /**
165     * Returns the current number of allocated targets.
166     * @return The current number of allocated targets.
167     */
168    int getNumTargets() { return ntargets; }
169
170    /**
171     * Returns a pointer to the target list.
172     * @return a pointer to the target list.
173     */
174    TargetList* getTargetList() { return &targets; }
175
176    /**
177     * Returns a reference to the first target.
178     * @return A pointer to the first target.
179     */
180    Target *getTarget() { return &targets.front(); }
181
182    /**
183     * Pop first target.
184     */
185    void popTarget()
186    {
187        --ntargets;
188        targets.pop_front();
189    }
190
191    /**
192     * Returns true if there are targets left.
193     * @return true if there are targets
194     */
195    bool hasTargets() { return !targets.empty(); }
196
197    bool isSimpleForward()
198    {
199        if (getNumTargets() != 1)
200            return false;
201        Target *tgt = getTarget();
202        return tgt->isCpuSide() && !tgt->pkt->needsResponse();
203    }
204
205    bool promoteDeferredTargets();
206
207    /**
208     * Prints the contents of this MSHR to stderr.
209     */
210    void dump();
211};
212
213#endif //__MSHR_HH__
214