cache.cc revision 12425
12810Srdreslin@umich.edu/* 212348Snikos.nikoleris@arm.com * Copyright (c) 2010-2017 ARM Limited 311051Sandreas.hansson@arm.com * All rights reserved. 411051Sandreas.hansson@arm.com * 511051Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall 611051Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual 711051Sandreas.hansson@arm.com * property including but not limited to intellectual property relating 811051Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software 911051Sandreas.hansson@arm.com * licensed hereunder. You may use the software subject to the license 1011051Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated 1111051Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software, 1211051Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form. 1311051Sandreas.hansson@arm.com * 1411051Sandreas.hansson@arm.com * Copyright (c) 2002-2005 The Regents of The University of Michigan 1511051Sandreas.hansson@arm.com * Copyright (c) 2010,2015 Advanced Micro Devices, Inc. 162810Srdreslin@umich.edu * All rights reserved. 172810Srdreslin@umich.edu * 182810Srdreslin@umich.edu * Redistribution and use in source and binary forms, with or without 192810Srdreslin@umich.edu * modification, are permitted provided that the following conditions are 202810Srdreslin@umich.edu * met: redistributions of source code must retain the above copyright 212810Srdreslin@umich.edu * notice, this list of conditions and the following disclaimer; 222810Srdreslin@umich.edu * redistributions in binary form must reproduce the above copyright 232810Srdreslin@umich.edu * notice, this list of conditions and the following disclaimer in the 242810Srdreslin@umich.edu * documentation and/or other materials provided with the distribution; 252810Srdreslin@umich.edu * neither the name of the copyright holders nor the names of its 262810Srdreslin@umich.edu * contributors may be used to endorse or promote products derived from 272810Srdreslin@umich.edu * this software without specific prior written permission. 282810Srdreslin@umich.edu * 292810Srdreslin@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 302810Srdreslin@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 312810Srdreslin@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 322810Srdreslin@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 332810Srdreslin@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 342810Srdreslin@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 352810Srdreslin@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 362810Srdreslin@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 372810Srdreslin@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 382810Srdreslin@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 392810Srdreslin@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402810Srdreslin@umich.edu * 412810Srdreslin@umich.edu * Authors: Erik Hallnor 4211051Sandreas.hansson@arm.com * Dave Greene 4311051Sandreas.hansson@arm.com * Nathan Binkert 442810Srdreslin@umich.edu * Steve Reinhardt 4511051Sandreas.hansson@arm.com * Ron Dreslinski 4611051Sandreas.hansson@arm.com * Andreas Sandberg 4712349Snikos.nikoleris@arm.com * Nikos Nikoleris 482810Srdreslin@umich.edu */ 492810Srdreslin@umich.edu 502810Srdreslin@umich.edu/** 512810Srdreslin@umich.edu * @file 5211051Sandreas.hansson@arm.com * Cache definitions. 532810Srdreslin@umich.edu */ 542810Srdreslin@umich.edu 5511051Sandreas.hansson@arm.com#include "mem/cache/cache.hh" 562810Srdreslin@umich.edu 5712334Sgabeblack@google.com#include "base/logging.hh" 5811051Sandreas.hansson@arm.com#include "base/types.hh" 5911051Sandreas.hansson@arm.com#include "debug/Cache.hh" 6011051Sandreas.hansson@arm.com#include "debug/CachePort.hh" 6111051Sandreas.hansson@arm.com#include "debug/CacheTags.hh" 6211288Ssteve.reinhardt@amd.com#include "debug/CacheVerbose.hh" 6311051Sandreas.hansson@arm.com#include "mem/cache/blk.hh" 6411051Sandreas.hansson@arm.com#include "mem/cache/mshr.hh" 6511051Sandreas.hansson@arm.com#include "mem/cache/prefetch/base.hh" 6611051Sandreas.hansson@arm.com#include "sim/sim_exit.hh" 6711051Sandreas.hansson@arm.com 6811053Sandreas.hansson@arm.comCache::Cache(const CacheParams *p) 6911053Sandreas.hansson@arm.com : BaseCache(p, p->system->cacheLineSize()), 7011051Sandreas.hansson@arm.com tags(p->tags), 7111051Sandreas.hansson@arm.com prefetcher(p->prefetcher), 7211051Sandreas.hansson@arm.com doFastWrites(true), 7311197Sandreas.hansson@arm.com prefetchOnAccess(p->prefetch_on_access), 7411197Sandreas.hansson@arm.com clusivity(p->clusivity), 7511199Sandreas.hansson@arm.com writebackClean(p->writeback_clean), 7611197Sandreas.hansson@arm.com tempBlockWriteback(nullptr), 7712084Sspwilson2@wisc.edu writebackTempBlockAtomicEvent([this]{ writebackTempBlockAtomic(); }, 7812084Sspwilson2@wisc.edu name(), false, 7911197Sandreas.hansson@arm.com EventBase::Delayed_Writeback_Pri) 8011051Sandreas.hansson@arm.com{ 8111051Sandreas.hansson@arm.com tempBlock = new CacheBlk(); 8211051Sandreas.hansson@arm.com tempBlock->data = new uint8_t[blkSize]; 8311051Sandreas.hansson@arm.com 8411051Sandreas.hansson@arm.com cpuSidePort = new CpuSidePort(p->name + ".cpu_side", this, 8511051Sandreas.hansson@arm.com "CpuSidePort"); 8611051Sandreas.hansson@arm.com memSidePort = new MemSidePort(p->name + ".mem_side", this, 8711051Sandreas.hansson@arm.com "MemSidePort"); 8811051Sandreas.hansson@arm.com 8911051Sandreas.hansson@arm.com tags->setCache(this); 9011051Sandreas.hansson@arm.com if (prefetcher) 9111051Sandreas.hansson@arm.com prefetcher->setCache(this); 9211051Sandreas.hansson@arm.com} 9311051Sandreas.hansson@arm.com 9411051Sandreas.hansson@arm.comCache::~Cache() 9511051Sandreas.hansson@arm.com{ 9611051Sandreas.hansson@arm.com delete [] tempBlock->data; 9711051Sandreas.hansson@arm.com delete tempBlock; 9811051Sandreas.hansson@arm.com 9911051Sandreas.hansson@arm.com delete cpuSidePort; 10011051Sandreas.hansson@arm.com delete memSidePort; 10111051Sandreas.hansson@arm.com} 10211051Sandreas.hansson@arm.com 10311051Sandreas.hansson@arm.comvoid 10411051Sandreas.hansson@arm.comCache::regStats() 10511051Sandreas.hansson@arm.com{ 10611051Sandreas.hansson@arm.com BaseCache::regStats(); 10711051Sandreas.hansson@arm.com} 10811051Sandreas.hansson@arm.com 10911051Sandreas.hansson@arm.comvoid 11011051Sandreas.hansson@arm.comCache::cmpAndSwap(CacheBlk *blk, PacketPtr pkt) 11111051Sandreas.hansson@arm.com{ 11211051Sandreas.hansson@arm.com assert(pkt->isRequest()); 11311051Sandreas.hansson@arm.com 11411051Sandreas.hansson@arm.com uint64_t overwrite_val; 11511051Sandreas.hansson@arm.com bool overwrite_mem; 11611051Sandreas.hansson@arm.com uint64_t condition_val64; 11711051Sandreas.hansson@arm.com uint32_t condition_val32; 11811051Sandreas.hansson@arm.com 11911051Sandreas.hansson@arm.com int offset = tags->extractBlkOffset(pkt->getAddr()); 12011051Sandreas.hansson@arm.com uint8_t *blk_data = blk->data + offset; 12111051Sandreas.hansson@arm.com 12211051Sandreas.hansson@arm.com assert(sizeof(uint64_t) >= pkt->getSize()); 12311051Sandreas.hansson@arm.com 12411051Sandreas.hansson@arm.com overwrite_mem = true; 12511051Sandreas.hansson@arm.com // keep a copy of our possible write value, and copy what is at the 12611051Sandreas.hansson@arm.com // memory address into the packet 12711051Sandreas.hansson@arm.com pkt->writeData((uint8_t *)&overwrite_val); 12811051Sandreas.hansson@arm.com pkt->setData(blk_data); 12911051Sandreas.hansson@arm.com 13011051Sandreas.hansson@arm.com if (pkt->req->isCondSwap()) { 13111051Sandreas.hansson@arm.com if (pkt->getSize() == sizeof(uint64_t)) { 13211051Sandreas.hansson@arm.com condition_val64 = pkt->req->getExtraData(); 13311051Sandreas.hansson@arm.com overwrite_mem = !std::memcmp(&condition_val64, blk_data, 13411051Sandreas.hansson@arm.com sizeof(uint64_t)); 13511051Sandreas.hansson@arm.com } else if (pkt->getSize() == sizeof(uint32_t)) { 13611051Sandreas.hansson@arm.com condition_val32 = (uint32_t)pkt->req->getExtraData(); 13711051Sandreas.hansson@arm.com overwrite_mem = !std::memcmp(&condition_val32, blk_data, 13811051Sandreas.hansson@arm.com sizeof(uint32_t)); 13911051Sandreas.hansson@arm.com } else 14011051Sandreas.hansson@arm.com panic("Invalid size for conditional read/write\n"); 14111051Sandreas.hansson@arm.com } 14211051Sandreas.hansson@arm.com 14311051Sandreas.hansson@arm.com if (overwrite_mem) { 14411051Sandreas.hansson@arm.com std::memcpy(blk_data, &overwrite_val, pkt->getSize()); 14511051Sandreas.hansson@arm.com blk->status |= BlkDirty; 14611051Sandreas.hansson@arm.com } 14711051Sandreas.hansson@arm.com} 14811051Sandreas.hansson@arm.com 14911051Sandreas.hansson@arm.com 15011051Sandreas.hansson@arm.comvoid 15111601Sandreas.hansson@arm.comCache::satisfyRequest(PacketPtr pkt, CacheBlk *blk, 15211601Sandreas.hansson@arm.com bool deferred_response, bool pending_downgrade) 15311051Sandreas.hansson@arm.com{ 15411051Sandreas.hansson@arm.com assert(pkt->isRequest()); 15511051Sandreas.hansson@arm.com 15611051Sandreas.hansson@arm.com assert(blk && blk->isValid()); 15711051Sandreas.hansson@arm.com // Occasionally this is not true... if we are a lower-level cache 15811051Sandreas.hansson@arm.com // satisfying a string of Read and ReadEx requests from 15911051Sandreas.hansson@arm.com // upper-level caches, a Read will mark the block as shared but we 16011051Sandreas.hansson@arm.com // can satisfy a following ReadEx anyway since we can rely on the 16111051Sandreas.hansson@arm.com // Read requester(s) to have buffered the ReadEx snoop and to 16211051Sandreas.hansson@arm.com // invalidate their blocks after receiving them. 16311284Sandreas.hansson@arm.com // assert(!pkt->needsWritable() || blk->isWritable()); 16411051Sandreas.hansson@arm.com assert(pkt->getOffset(blkSize) + pkt->getSize() <= blkSize); 16511051Sandreas.hansson@arm.com 16611051Sandreas.hansson@arm.com // Check RMW operations first since both isRead() and 16711051Sandreas.hansson@arm.com // isWrite() will be true for them 16811051Sandreas.hansson@arm.com if (pkt->cmd == MemCmd::SwapReq) { 16911051Sandreas.hansson@arm.com cmpAndSwap(blk, pkt); 17011051Sandreas.hansson@arm.com } else if (pkt->isWrite()) { 17111284Sandreas.hansson@arm.com // we have the block in a writable state and can go ahead, 17211284Sandreas.hansson@arm.com // note that the line may be also be considered writable in 17311284Sandreas.hansson@arm.com // downstream caches along the path to memory, but always 17411284Sandreas.hansson@arm.com // Exclusive, and never Modified 17511051Sandreas.hansson@arm.com assert(blk->isWritable()); 17611284Sandreas.hansson@arm.com // Write or WriteLine at the first cache with block in writable state 17711051Sandreas.hansson@arm.com if (blk->checkWrite(pkt)) { 17811051Sandreas.hansson@arm.com pkt->writeDataToBlock(blk->data, blkSize); 17911051Sandreas.hansson@arm.com } 18011284Sandreas.hansson@arm.com // Always mark the line as dirty (and thus transition to the 18111284Sandreas.hansson@arm.com // Modified state) even if we are a failed StoreCond so we 18211284Sandreas.hansson@arm.com // supply data to any snoops that have appended themselves to 18311284Sandreas.hansson@arm.com // this cache before knowing the store will fail. 18411051Sandreas.hansson@arm.com blk->status |= BlkDirty; 18511744Snikos.nikoleris@arm.com DPRINTF(CacheVerbose, "%s for %s (write)\n", __func__, pkt->print()); 18611051Sandreas.hansson@arm.com } else if (pkt->isRead()) { 18711051Sandreas.hansson@arm.com if (pkt->isLLSC()) { 18811051Sandreas.hansson@arm.com blk->trackLoadLocked(pkt); 18911051Sandreas.hansson@arm.com } 19011286Sandreas.hansson@arm.com 19111286Sandreas.hansson@arm.com // all read responses have a data payload 19211286Sandreas.hansson@arm.com assert(pkt->hasRespData()); 19311051Sandreas.hansson@arm.com pkt->setDataFromBlock(blk->data, blkSize); 19411286Sandreas.hansson@arm.com 19511600Sandreas.hansson@arm.com // determine if this read is from a (coherent) cache or not 19611600Sandreas.hansson@arm.com if (pkt->fromCache()) { 19711051Sandreas.hansson@arm.com assert(pkt->getSize() == blkSize); 19811051Sandreas.hansson@arm.com // special handling for coherent block requests from 19911051Sandreas.hansson@arm.com // upper-level caches 20011284Sandreas.hansson@arm.com if (pkt->needsWritable()) { 20111051Sandreas.hansson@arm.com // sanity check 20211051Sandreas.hansson@arm.com assert(pkt->cmd == MemCmd::ReadExReq || 20311051Sandreas.hansson@arm.com pkt->cmd == MemCmd::SCUpgradeFailReq); 20411602Sandreas.hansson@arm.com assert(!pkt->hasSharers()); 20511051Sandreas.hansson@arm.com 20611051Sandreas.hansson@arm.com // if we have a dirty copy, make sure the recipient 20711284Sandreas.hansson@arm.com // keeps it marked dirty (in the modified state) 20811051Sandreas.hansson@arm.com if (blk->isDirty()) { 20911284Sandreas.hansson@arm.com pkt->setCacheResponding(); 21011602Sandreas.hansson@arm.com blk->status &= ~BlkDirty; 21111051Sandreas.hansson@arm.com } 21211051Sandreas.hansson@arm.com } else if (blk->isWritable() && !pending_downgrade && 21311284Sandreas.hansson@arm.com !pkt->hasSharers() && 21411051Sandreas.hansson@arm.com pkt->cmd != MemCmd::ReadCleanReq) { 21511284Sandreas.hansson@arm.com // we can give the requester a writable copy on a read 21611284Sandreas.hansson@arm.com // request if: 21711284Sandreas.hansson@arm.com // - we have a writable copy at this level (& below) 21811051Sandreas.hansson@arm.com // - we don't have a pending snoop from below 21911051Sandreas.hansson@arm.com // signaling another read request 22011051Sandreas.hansson@arm.com // - no other cache above has a copy (otherwise it 22111284Sandreas.hansson@arm.com // would have set hasSharers flag when 22211284Sandreas.hansson@arm.com // snooping the packet) 22311284Sandreas.hansson@arm.com // - the read has explicitly asked for a clean 22411284Sandreas.hansson@arm.com // copy of the line 22511051Sandreas.hansson@arm.com if (blk->isDirty()) { 22611051Sandreas.hansson@arm.com // special considerations if we're owner: 22711051Sandreas.hansson@arm.com if (!deferred_response) { 22811284Sandreas.hansson@arm.com // respond with the line in Modified state 22911284Sandreas.hansson@arm.com // (cacheResponding set, hasSharers not set) 23011284Sandreas.hansson@arm.com pkt->setCacheResponding(); 23111197Sandreas.hansson@arm.com 23211601Sandreas.hansson@arm.com // if this cache is mostly inclusive, we 23311601Sandreas.hansson@arm.com // keep the block in the Exclusive state, 23411601Sandreas.hansson@arm.com // and pass it upwards as Modified 23511601Sandreas.hansson@arm.com // (writable and dirty), hence we have 23611601Sandreas.hansson@arm.com // multiple caches, all on the same path 23711601Sandreas.hansson@arm.com // towards memory, all considering the 23811601Sandreas.hansson@arm.com // same block writable, but only one 23911601Sandreas.hansson@arm.com // considering it Modified 24011197Sandreas.hansson@arm.com 24111601Sandreas.hansson@arm.com // we get away with multiple caches (on 24211601Sandreas.hansson@arm.com // the same path to memory) considering 24311601Sandreas.hansson@arm.com // the block writeable as we always enter 24411601Sandreas.hansson@arm.com // the cache hierarchy through a cache, 24511601Sandreas.hansson@arm.com // and first snoop upwards in all other 24611601Sandreas.hansson@arm.com // branches 24711601Sandreas.hansson@arm.com blk->status &= ~BlkDirty; 24811051Sandreas.hansson@arm.com } else { 24911051Sandreas.hansson@arm.com // if we're responding after our own miss, 25011051Sandreas.hansson@arm.com // there's a window where the recipient didn't 25111051Sandreas.hansson@arm.com // know it was getting ownership and may not 25211051Sandreas.hansson@arm.com // have responded to snoops correctly, so we 25311284Sandreas.hansson@arm.com // have to respond with a shared line 25411284Sandreas.hansson@arm.com pkt->setHasSharers(); 25511051Sandreas.hansson@arm.com } 25611051Sandreas.hansson@arm.com } 25711051Sandreas.hansson@arm.com } else { 25811051Sandreas.hansson@arm.com // otherwise only respond with a shared copy 25911284Sandreas.hansson@arm.com pkt->setHasSharers(); 26011051Sandreas.hansson@arm.com } 26111051Sandreas.hansson@arm.com } 26211602Sandreas.hansson@arm.com } else if (pkt->isUpgrade()) { 26311602Sandreas.hansson@arm.com // sanity check 26411602Sandreas.hansson@arm.com assert(!pkt->hasSharers()); 26511602Sandreas.hansson@arm.com 26611602Sandreas.hansson@arm.com if (blk->isDirty()) { 26711602Sandreas.hansson@arm.com // we were in the Owned state, and a cache above us that 26811602Sandreas.hansson@arm.com // has the line in Shared state needs to be made aware 26911602Sandreas.hansson@arm.com // that the data it already has is in fact dirty 27011602Sandreas.hansson@arm.com pkt->setCacheResponding(); 27111602Sandreas.hansson@arm.com blk->status &= ~BlkDirty; 27211602Sandreas.hansson@arm.com } 27311051Sandreas.hansson@arm.com } else { 27411602Sandreas.hansson@arm.com assert(pkt->isInvalidate()); 27511197Sandreas.hansson@arm.com invalidateBlock(blk); 27611744Snikos.nikoleris@arm.com DPRINTF(CacheVerbose, "%s for %s (invalidation)\n", __func__, 27711744Snikos.nikoleris@arm.com pkt->print()); 27811051Sandreas.hansson@arm.com } 27911051Sandreas.hansson@arm.com} 28011051Sandreas.hansson@arm.com 28111051Sandreas.hansson@arm.com///////////////////////////////////////////////////// 28211051Sandreas.hansson@arm.com// 28311051Sandreas.hansson@arm.com// Access path: requests coming in from the CPU side 28411051Sandreas.hansson@arm.com// 28511051Sandreas.hansson@arm.com///////////////////////////////////////////////////// 28611051Sandreas.hansson@arm.com 28711051Sandreas.hansson@arm.combool 28811051Sandreas.hansson@arm.comCache::access(PacketPtr pkt, CacheBlk *&blk, Cycles &lat, 28911051Sandreas.hansson@arm.com PacketList &writebacks) 29011051Sandreas.hansson@arm.com{ 29111051Sandreas.hansson@arm.com // sanity check 29211051Sandreas.hansson@arm.com assert(pkt->isRequest()); 29311051Sandreas.hansson@arm.com 29411051Sandreas.hansson@arm.com chatty_assert(!(isReadOnly && pkt->isWrite()), 29511051Sandreas.hansson@arm.com "Should never see a write in a read-only cache %s\n", 29611051Sandreas.hansson@arm.com name()); 29711051Sandreas.hansson@arm.com 29811744Snikos.nikoleris@arm.com DPRINTF(CacheVerbose, "%s for %s\n", __func__, pkt->print()); 29911051Sandreas.hansson@arm.com 30011051Sandreas.hansson@arm.com if (pkt->req->isUncacheable()) { 30111744Snikos.nikoleris@arm.com DPRINTF(Cache, "uncacheable: %s\n", pkt->print()); 30211051Sandreas.hansson@arm.com 30311051Sandreas.hansson@arm.com // flush and invalidate any existing block 30411051Sandreas.hansson@arm.com CacheBlk *old_blk(tags->findBlock(pkt->getAddr(), pkt->isSecure())); 30511051Sandreas.hansson@arm.com if (old_blk && old_blk->isValid()) { 30611199Sandreas.hansson@arm.com if (old_blk->isDirty() || writebackClean) 30711051Sandreas.hansson@arm.com writebacks.push_back(writebackBlk(old_blk)); 30811051Sandreas.hansson@arm.com else 30911051Sandreas.hansson@arm.com writebacks.push_back(cleanEvictBlk(old_blk)); 31011867Snikos.nikoleris@arm.com invalidateBlock(old_blk); 31111051Sandreas.hansson@arm.com } 31211051Sandreas.hansson@arm.com 31311484Snikos.nikoleris@arm.com blk = nullptr; 31411051Sandreas.hansson@arm.com // lookupLatency is the latency in case the request is uncacheable. 31511051Sandreas.hansson@arm.com lat = lookupLatency; 31611051Sandreas.hansson@arm.com return false; 31711051Sandreas.hansson@arm.com } 31811051Sandreas.hansson@arm.com 31911051Sandreas.hansson@arm.com // Here lat is the value passed as parameter to accessBlock() function 32011051Sandreas.hansson@arm.com // that can modify its value. 32111870Snikos.nikoleris@arm.com blk = tags->accessBlock(pkt->getAddr(), pkt->isSecure(), lat); 32211051Sandreas.hansson@arm.com 32311744Snikos.nikoleris@arm.com DPRINTF(Cache, "%s %s\n", pkt->print(), 32411051Sandreas.hansson@arm.com blk ? "hit " + blk->print() : "miss"); 32511051Sandreas.hansson@arm.com 32612349Snikos.nikoleris@arm.com if (pkt->req->isCacheMaintenance()) { 32712349Snikos.nikoleris@arm.com // A cache maintenance operation is always forwarded to the 32812349Snikos.nikoleris@arm.com // memory below even if the block is found in dirty state. 32912349Snikos.nikoleris@arm.com 33012349Snikos.nikoleris@arm.com // We defer any changes to the state of the block until we 33112349Snikos.nikoleris@arm.com // create and mark as in service the mshr for the downstream 33212349Snikos.nikoleris@arm.com // packet. 33312349Snikos.nikoleris@arm.com return false; 33412349Snikos.nikoleris@arm.com } 33511051Sandreas.hansson@arm.com 33611199Sandreas.hansson@arm.com if (pkt->isEviction()) { 33711051Sandreas.hansson@arm.com // We check for presence of block in above caches before issuing 33811051Sandreas.hansson@arm.com // Writeback or CleanEvict to write buffer. Therefore the only 33911051Sandreas.hansson@arm.com // possible cases can be of a CleanEvict packet coming from above 34011051Sandreas.hansson@arm.com // encountering a Writeback generated in this cache peer cache and 34111051Sandreas.hansson@arm.com // waiting in the write buffer. Cases of upper level peer caches 34211051Sandreas.hansson@arm.com // generating CleanEvict and Writeback or simply CleanEvict and 34311051Sandreas.hansson@arm.com // CleanEvict almost simultaneously will be caught by snoops sent out 34411051Sandreas.hansson@arm.com // by crossbar. 34511375Sandreas.hansson@arm.com WriteQueueEntry *wb_entry = writeBuffer.findMatch(pkt->getAddr(), 34611375Sandreas.hansson@arm.com pkt->isSecure()); 34711375Sandreas.hansson@arm.com if (wb_entry) { 34811199Sandreas.hansson@arm.com assert(wb_entry->getNumTargets() == 1); 34911199Sandreas.hansson@arm.com PacketPtr wbPkt = wb_entry->getTarget()->pkt; 35011199Sandreas.hansson@arm.com assert(wbPkt->isWriteback()); 35111199Sandreas.hansson@arm.com 35211199Sandreas.hansson@arm.com if (pkt->isCleanEviction()) { 35311199Sandreas.hansson@arm.com // The CleanEvict and WritebackClean snoops into other 35411199Sandreas.hansson@arm.com // peer caches of the same level while traversing the 35511199Sandreas.hansson@arm.com // crossbar. If a copy of the block is found, the 35611199Sandreas.hansson@arm.com // packet is deleted in the crossbar. Hence, none of 35711199Sandreas.hansson@arm.com // the other upper level caches connected to this 35811199Sandreas.hansson@arm.com // cache have the block, so we can clear the 35911199Sandreas.hansson@arm.com // BLOCK_CACHED flag in the Writeback if set and 36011199Sandreas.hansson@arm.com // discard the CleanEvict by returning true. 36111199Sandreas.hansson@arm.com wbPkt->clearBlockCached(); 36211199Sandreas.hansson@arm.com return true; 36311199Sandreas.hansson@arm.com } else { 36411199Sandreas.hansson@arm.com assert(pkt->cmd == MemCmd::WritebackDirty); 36511199Sandreas.hansson@arm.com // Dirty writeback from above trumps our clean 36611199Sandreas.hansson@arm.com // writeback... discard here 36711199Sandreas.hansson@arm.com // Note: markInService will remove entry from writeback buffer. 36811375Sandreas.hansson@arm.com markInService(wb_entry); 36911199Sandreas.hansson@arm.com delete wbPkt; 37011199Sandreas.hansson@arm.com } 37111051Sandreas.hansson@arm.com } 37211051Sandreas.hansson@arm.com } 37311051Sandreas.hansson@arm.com 37411051Sandreas.hansson@arm.com // Writeback handling is special case. We can write the block into 37511051Sandreas.hansson@arm.com // the cache without having a writeable copy (or any copy at all). 37611199Sandreas.hansson@arm.com if (pkt->isWriteback()) { 37711051Sandreas.hansson@arm.com assert(blkSize == pkt->getSize()); 37811199Sandreas.hansson@arm.com 37911199Sandreas.hansson@arm.com // we could get a clean writeback while we are having 38011199Sandreas.hansson@arm.com // outstanding accesses to a block, do the simple thing for 38111199Sandreas.hansson@arm.com // now and drop the clean writeback so that we do not upset 38211199Sandreas.hansson@arm.com // any ordering/decisions about ownership already taken 38311199Sandreas.hansson@arm.com if (pkt->cmd == MemCmd::WritebackClean && 38411199Sandreas.hansson@arm.com mshrQueue.findMatch(pkt->getAddr(), pkt->isSecure())) { 38511199Sandreas.hansson@arm.com DPRINTF(Cache, "Clean writeback %#llx to block with MSHR, " 38611199Sandreas.hansson@arm.com "dropping\n", pkt->getAddr()); 38711199Sandreas.hansson@arm.com return true; 38811199Sandreas.hansson@arm.com } 38911199Sandreas.hansson@arm.com 39011484Snikos.nikoleris@arm.com if (blk == nullptr) { 39111051Sandreas.hansson@arm.com // need to do a replacement 39211051Sandreas.hansson@arm.com blk = allocateBlock(pkt->getAddr(), pkt->isSecure(), writebacks); 39311484Snikos.nikoleris@arm.com if (blk == nullptr) { 39411051Sandreas.hansson@arm.com // no replaceable block available: give up, fwd to next level. 39511051Sandreas.hansson@arm.com incMissCount(pkt); 39611051Sandreas.hansson@arm.com return false; 39711051Sandreas.hansson@arm.com } 39811051Sandreas.hansson@arm.com tags->insertBlock(pkt, blk); 39911051Sandreas.hansson@arm.com 40011051Sandreas.hansson@arm.com blk->status = (BlkValid | BlkReadable); 40111051Sandreas.hansson@arm.com if (pkt->isSecure()) { 40211051Sandreas.hansson@arm.com blk->status |= BlkSecure; 40311051Sandreas.hansson@arm.com } 40411051Sandreas.hansson@arm.com } 40511199Sandreas.hansson@arm.com // only mark the block dirty if we got a writeback command, 40611199Sandreas.hansson@arm.com // and leave it as is for a clean writeback 40711199Sandreas.hansson@arm.com if (pkt->cmd == MemCmd::WritebackDirty) { 40811199Sandreas.hansson@arm.com blk->status |= BlkDirty; 40911199Sandreas.hansson@arm.com } 41011284Sandreas.hansson@arm.com // if the packet does not have sharers, it is passing 41111284Sandreas.hansson@arm.com // writable, and we got the writeback in Modified or Exclusive 41211284Sandreas.hansson@arm.com // state, if not we are in the Owned or Shared state 41311284Sandreas.hansson@arm.com if (!pkt->hasSharers()) { 41411051Sandreas.hansson@arm.com blk->status |= BlkWritable; 41511051Sandreas.hansson@arm.com } 41611051Sandreas.hansson@arm.com // nothing else to do; writeback doesn't expect response 41711051Sandreas.hansson@arm.com assert(!pkt->needsResponse()); 41811051Sandreas.hansson@arm.com std::memcpy(blk->data, pkt->getConstPtr<uint8_t>(), blkSize); 41911051Sandreas.hansson@arm.com DPRINTF(Cache, "%s new state is %s\n", __func__, blk->print()); 42011051Sandreas.hansson@arm.com incHitCount(pkt); 42111051Sandreas.hansson@arm.com return true; 42211051Sandreas.hansson@arm.com } else if (pkt->cmd == MemCmd::CleanEvict) { 42311484Snikos.nikoleris@arm.com if (blk != nullptr) { 42411051Sandreas.hansson@arm.com // Found the block in the tags, need to stop CleanEvict from 42511051Sandreas.hansson@arm.com // propagating further down the hierarchy. Returning true will 42611051Sandreas.hansson@arm.com // treat the CleanEvict like a satisfied write request and delete 42711051Sandreas.hansson@arm.com // it. 42811051Sandreas.hansson@arm.com return true; 42911051Sandreas.hansson@arm.com } 43011051Sandreas.hansson@arm.com // We didn't find the block here, propagate the CleanEvict further 43111051Sandreas.hansson@arm.com // down the memory hierarchy. Returning false will treat the CleanEvict 43211051Sandreas.hansson@arm.com // like a Writeback which could not find a replaceable block so has to 43311051Sandreas.hansson@arm.com // go to next level. 43411051Sandreas.hansson@arm.com return false; 43512345Snikos.nikoleris@arm.com } else if (pkt->cmd == MemCmd::WriteClean) { 43612345Snikos.nikoleris@arm.com // WriteClean handling is a special case. We can allocate a 43712345Snikos.nikoleris@arm.com // block directly if it doesn't exist and we can update the 43812345Snikos.nikoleris@arm.com // block immediately. The WriteClean transfers the ownership 43912345Snikos.nikoleris@arm.com // of the block as well. 44012345Snikos.nikoleris@arm.com assert(blkSize == pkt->getSize()); 44112345Snikos.nikoleris@arm.com 44212345Snikos.nikoleris@arm.com if (!blk) { 44312346Snikos.nikoleris@arm.com if (pkt->writeThrough()) { 44412346Snikos.nikoleris@arm.com // if this is a write through packet, we don't try to 44512346Snikos.nikoleris@arm.com // allocate if the block is not present 44612345Snikos.nikoleris@arm.com return false; 44712346Snikos.nikoleris@arm.com } else { 44812346Snikos.nikoleris@arm.com // a writeback that misses needs to allocate a new block 44912346Snikos.nikoleris@arm.com blk = allocateBlock(pkt->getAddr(), pkt->isSecure(), 45012346Snikos.nikoleris@arm.com writebacks); 45112346Snikos.nikoleris@arm.com if (!blk) { 45212346Snikos.nikoleris@arm.com // no replaceable block available: give up, fwd to 45312346Snikos.nikoleris@arm.com // next level. 45412346Snikos.nikoleris@arm.com incMissCount(pkt); 45512346Snikos.nikoleris@arm.com return false; 45612346Snikos.nikoleris@arm.com } 45712346Snikos.nikoleris@arm.com tags->insertBlock(pkt, blk); 45812346Snikos.nikoleris@arm.com 45912346Snikos.nikoleris@arm.com blk->status = (BlkValid | BlkReadable); 46012346Snikos.nikoleris@arm.com if (pkt->isSecure()) { 46112346Snikos.nikoleris@arm.com blk->status |= BlkSecure; 46212346Snikos.nikoleris@arm.com } 46312345Snikos.nikoleris@arm.com } 46412345Snikos.nikoleris@arm.com } 46512345Snikos.nikoleris@arm.com 46612345Snikos.nikoleris@arm.com // at this point either this is a writeback or a write-through 46712345Snikos.nikoleris@arm.com // write clean operation and the block is already in this 46812345Snikos.nikoleris@arm.com // cache, we need to update the data and the block flags 46912345Snikos.nikoleris@arm.com assert(blk); 47012346Snikos.nikoleris@arm.com if (!pkt->writeThrough()) { 47112346Snikos.nikoleris@arm.com blk->status |= BlkDirty; 47212346Snikos.nikoleris@arm.com } 47312345Snikos.nikoleris@arm.com // nothing else to do; writeback doesn't expect response 47412345Snikos.nikoleris@arm.com assert(!pkt->needsResponse()); 47512345Snikos.nikoleris@arm.com std::memcpy(blk->data, pkt->getConstPtr<uint8_t>(), blkSize); 47612345Snikos.nikoleris@arm.com DPRINTF(Cache, "%s new state is %s\n", __func__, blk->print()); 47712345Snikos.nikoleris@arm.com 47812345Snikos.nikoleris@arm.com incHitCount(pkt); 47912345Snikos.nikoleris@arm.com // populate the time when the block will be ready to access. 48012345Snikos.nikoleris@arm.com blk->whenReady = clockEdge(fillLatency) + pkt->headerDelay + 48112345Snikos.nikoleris@arm.com pkt->payloadDelay; 48212346Snikos.nikoleris@arm.com // if this a write-through packet it will be sent to cache 48312346Snikos.nikoleris@arm.com // below 48412346Snikos.nikoleris@arm.com return !pkt->writeThrough(); 48511601Sandreas.hansson@arm.com } else if (blk && (pkt->needsWritable() ? blk->isWritable() : 48611601Sandreas.hansson@arm.com blk->isReadable())) { 48711051Sandreas.hansson@arm.com // OK to satisfy access 48811051Sandreas.hansson@arm.com incHitCount(pkt); 48911601Sandreas.hansson@arm.com satisfyRequest(pkt, blk); 49011601Sandreas.hansson@arm.com maintainClusivity(pkt->fromCache(), blk); 49111601Sandreas.hansson@arm.com 49211051Sandreas.hansson@arm.com return true; 49311051Sandreas.hansson@arm.com } 49411051Sandreas.hansson@arm.com 49511484Snikos.nikoleris@arm.com // Can't satisfy access normally... either no block (blk == nullptr) 49611284Sandreas.hansson@arm.com // or have block but need writable 49711051Sandreas.hansson@arm.com 49811051Sandreas.hansson@arm.com incMissCount(pkt); 49911051Sandreas.hansson@arm.com 50011484Snikos.nikoleris@arm.com if (blk == nullptr && pkt->isLLSC() && pkt->isWrite()) { 50111051Sandreas.hansson@arm.com // complete miss on store conditional... just give up now 50211051Sandreas.hansson@arm.com pkt->req->setExtraData(0); 50311051Sandreas.hansson@arm.com return true; 50411051Sandreas.hansson@arm.com } 50511051Sandreas.hansson@arm.com 50611051Sandreas.hansson@arm.com return false; 50711051Sandreas.hansson@arm.com} 50811051Sandreas.hansson@arm.com 50911051Sandreas.hansson@arm.comvoid 51011601Sandreas.hansson@arm.comCache::maintainClusivity(bool from_cache, CacheBlk *blk) 51111601Sandreas.hansson@arm.com{ 51211601Sandreas.hansson@arm.com if (from_cache && blk && blk->isValid() && !blk->isDirty() && 51311601Sandreas.hansson@arm.com clusivity == Enums::mostly_excl) { 51411601Sandreas.hansson@arm.com // if we have responded to a cache, and our block is still 51511601Sandreas.hansson@arm.com // valid, but not dirty, and this cache is mostly exclusive 51611601Sandreas.hansson@arm.com // with respect to the cache above, drop the block 51711601Sandreas.hansson@arm.com invalidateBlock(blk); 51811601Sandreas.hansson@arm.com } 51911601Sandreas.hansson@arm.com} 52011601Sandreas.hansson@arm.com 52111601Sandreas.hansson@arm.comvoid 52211051Sandreas.hansson@arm.comCache::doWritebacks(PacketList& writebacks, Tick forward_time) 52311051Sandreas.hansson@arm.com{ 52411051Sandreas.hansson@arm.com while (!writebacks.empty()) { 52511051Sandreas.hansson@arm.com PacketPtr wbPkt = writebacks.front(); 52611051Sandreas.hansson@arm.com // We use forwardLatency here because we are copying writebacks to 52712345Snikos.nikoleris@arm.com // write buffer. 52812345Snikos.nikoleris@arm.com 52912345Snikos.nikoleris@arm.com // Call isCachedAbove for Writebacks, CleanEvicts and 53012345Snikos.nikoleris@arm.com // WriteCleans to discover if the block is cached above. 53111051Sandreas.hansson@arm.com if (isCachedAbove(wbPkt)) { 53211051Sandreas.hansson@arm.com if (wbPkt->cmd == MemCmd::CleanEvict) { 53311051Sandreas.hansson@arm.com // Delete CleanEvict because cached copies exist above. The 53411051Sandreas.hansson@arm.com // packet destructor will delete the request object because 53511051Sandreas.hansson@arm.com // this is a non-snoop request packet which does not require a 53611051Sandreas.hansson@arm.com // response. 53711051Sandreas.hansson@arm.com delete wbPkt; 53811199Sandreas.hansson@arm.com } else if (wbPkt->cmd == MemCmd::WritebackClean) { 53911199Sandreas.hansson@arm.com // clean writeback, do not send since the block is 54011199Sandreas.hansson@arm.com // still cached above 54111199Sandreas.hansson@arm.com assert(writebackClean); 54211199Sandreas.hansson@arm.com delete wbPkt; 54311051Sandreas.hansson@arm.com } else { 54412345Snikos.nikoleris@arm.com assert(wbPkt->cmd == MemCmd::WritebackDirty || 54512345Snikos.nikoleris@arm.com wbPkt->cmd == MemCmd::WriteClean); 54611051Sandreas.hansson@arm.com // Set BLOCK_CACHED flag in Writeback and send below, so that 54711051Sandreas.hansson@arm.com // the Writeback does not reset the bit corresponding to this 54811051Sandreas.hansson@arm.com // address in the snoop filter below. 54911051Sandreas.hansson@arm.com wbPkt->setBlockCached(); 55011051Sandreas.hansson@arm.com allocateWriteBuffer(wbPkt, forward_time); 55111051Sandreas.hansson@arm.com } 55211051Sandreas.hansson@arm.com } else { 55311051Sandreas.hansson@arm.com // If the block is not cached above, send packet below. Both 55411051Sandreas.hansson@arm.com // CleanEvict and Writeback with BLOCK_CACHED flag cleared will 55511051Sandreas.hansson@arm.com // reset the bit corresponding to this address in the snoop filter 55611051Sandreas.hansson@arm.com // below. 55711051Sandreas.hansson@arm.com allocateWriteBuffer(wbPkt, forward_time); 55811051Sandreas.hansson@arm.com } 55911051Sandreas.hansson@arm.com writebacks.pop_front(); 56011051Sandreas.hansson@arm.com } 56111051Sandreas.hansson@arm.com} 56211051Sandreas.hansson@arm.com 56311130Sali.jafri@arm.comvoid 56411130Sali.jafri@arm.comCache::doWritebacksAtomic(PacketList& writebacks) 56511130Sali.jafri@arm.com{ 56611130Sali.jafri@arm.com while (!writebacks.empty()) { 56711130Sali.jafri@arm.com PacketPtr wbPkt = writebacks.front(); 56811130Sali.jafri@arm.com // Call isCachedAbove for both Writebacks and CleanEvicts. If 56911130Sali.jafri@arm.com // isCachedAbove returns true we set BLOCK_CACHED flag in Writebacks 57011130Sali.jafri@arm.com // and discard CleanEvicts. 57111130Sali.jafri@arm.com if (isCachedAbove(wbPkt, false)) { 57212345Snikos.nikoleris@arm.com if (wbPkt->cmd == MemCmd::WritebackDirty || 57312345Snikos.nikoleris@arm.com wbPkt->cmd == MemCmd::WriteClean) { 57411130Sali.jafri@arm.com // Set BLOCK_CACHED flag in Writeback and send below, 57511130Sali.jafri@arm.com // so that the Writeback does not reset the bit 57611130Sali.jafri@arm.com // corresponding to this address in the snoop filter 57711130Sali.jafri@arm.com // below. We can discard CleanEvicts because cached 57811130Sali.jafri@arm.com // copies exist above. Atomic mode isCachedAbove 57911130Sali.jafri@arm.com // modifies packet to set BLOCK_CACHED flag 58011130Sali.jafri@arm.com memSidePort->sendAtomic(wbPkt); 58111130Sali.jafri@arm.com } 58211130Sali.jafri@arm.com } else { 58311130Sali.jafri@arm.com // If the block is not cached above, send packet below. Both 58411130Sali.jafri@arm.com // CleanEvict and Writeback with BLOCK_CACHED flag cleared will 58511130Sali.jafri@arm.com // reset the bit corresponding to this address in the snoop filter 58611130Sali.jafri@arm.com // below. 58711130Sali.jafri@arm.com memSidePort->sendAtomic(wbPkt); 58811130Sali.jafri@arm.com } 58911130Sali.jafri@arm.com writebacks.pop_front(); 59011130Sali.jafri@arm.com // In case of CleanEvicts, the packet destructor will delete the 59111130Sali.jafri@arm.com // request object because this is a non-snoop request packet which 59211130Sali.jafri@arm.com // does not require a response. 59311130Sali.jafri@arm.com delete wbPkt; 59411130Sali.jafri@arm.com } 59511130Sali.jafri@arm.com} 59611130Sali.jafri@arm.com 59711051Sandreas.hansson@arm.com 59811051Sandreas.hansson@arm.comvoid 59911051Sandreas.hansson@arm.comCache::recvTimingSnoopResp(PacketPtr pkt) 60011051Sandreas.hansson@arm.com{ 60111744Snikos.nikoleris@arm.com DPRINTF(Cache, "%s for %s\n", __func__, pkt->print()); 60211051Sandreas.hansson@arm.com 60311051Sandreas.hansson@arm.com assert(pkt->isResponse()); 60411051Sandreas.hansson@arm.com assert(!system->bypassCaches()); 60511051Sandreas.hansson@arm.com 60611276Sandreas.hansson@arm.com // determine if the response is from a snoop request we created 60711276Sandreas.hansson@arm.com // (in which case it should be in the outstandingSnoop), or if we 60811276Sandreas.hansson@arm.com // merely forwarded someone else's snoop request 60911276Sandreas.hansson@arm.com const bool forwardAsSnoop = outstandingSnoop.find(pkt->req) == 61011276Sandreas.hansson@arm.com outstandingSnoop.end(); 61111276Sandreas.hansson@arm.com 61211276Sandreas.hansson@arm.com if (!forwardAsSnoop) { 61311276Sandreas.hansson@arm.com // the packet came from this cache, so sink it here and do not 61411276Sandreas.hansson@arm.com // forward it 61511051Sandreas.hansson@arm.com assert(pkt->cmd == MemCmd::HardPFResp); 61611276Sandreas.hansson@arm.com 61711276Sandreas.hansson@arm.com outstandingSnoop.erase(pkt->req); 61811276Sandreas.hansson@arm.com 61911276Sandreas.hansson@arm.com DPRINTF(Cache, "Got prefetch response from above for addr " 62011276Sandreas.hansson@arm.com "%#llx (%s)\n", pkt->getAddr(), pkt->isSecure() ? "s" : "ns"); 62111051Sandreas.hansson@arm.com recvTimingResp(pkt); 62211051Sandreas.hansson@arm.com return; 62311051Sandreas.hansson@arm.com } 62411051Sandreas.hansson@arm.com 62511051Sandreas.hansson@arm.com // forwardLatency is set here because there is a response from an 62611051Sandreas.hansson@arm.com // upper level cache. 62711051Sandreas.hansson@arm.com // To pay the delay that occurs if the packet comes from the bus, 62811051Sandreas.hansson@arm.com // we charge also headerDelay. 62911051Sandreas.hansson@arm.com Tick snoop_resp_time = clockEdge(forwardLatency) + pkt->headerDelay; 63011051Sandreas.hansson@arm.com // Reset the timing of the packet. 63111051Sandreas.hansson@arm.com pkt->headerDelay = pkt->payloadDelay = 0; 63211051Sandreas.hansson@arm.com memSidePort->schedTimingSnoopResp(pkt, snoop_resp_time); 63311051Sandreas.hansson@arm.com} 63411051Sandreas.hansson@arm.com 63511051Sandreas.hansson@arm.comvoid 63611051Sandreas.hansson@arm.comCache::promoteWholeLineWrites(PacketPtr pkt) 63711051Sandreas.hansson@arm.com{ 63811051Sandreas.hansson@arm.com // Cache line clearing instructions 63911051Sandreas.hansson@arm.com if (doFastWrites && (pkt->cmd == MemCmd::WriteReq) && 64011051Sandreas.hansson@arm.com (pkt->getSize() == blkSize) && (pkt->getOffset(blkSize) == 0)) { 64111051Sandreas.hansson@arm.com pkt->cmd = MemCmd::WriteLineReq; 64211051Sandreas.hansson@arm.com DPRINTF(Cache, "packet promoted from Write to WriteLineReq\n"); 64311051Sandreas.hansson@arm.com } 64411051Sandreas.hansson@arm.com} 64511051Sandreas.hansson@arm.com 64611051Sandreas.hansson@arm.combool 64711051Sandreas.hansson@arm.comCache::recvTimingReq(PacketPtr pkt) 64811051Sandreas.hansson@arm.com{ 64911830Sbaz21@cam.ac.uk DPRINTF(CacheTags, "%s tags:\n%s\n", __func__, tags->print()); 65011051Sandreas.hansson@arm.com 65111051Sandreas.hansson@arm.com assert(pkt->isRequest()); 65211051Sandreas.hansson@arm.com 65311051Sandreas.hansson@arm.com // Just forward the packet if caches are disabled. 65411051Sandreas.hansson@arm.com if (system->bypassCaches()) { 65511051Sandreas.hansson@arm.com // @todo This should really enqueue the packet rather 65611051Sandreas.hansson@arm.com bool M5_VAR_USED success = memSidePort->sendTimingReq(pkt); 65711051Sandreas.hansson@arm.com assert(success); 65811051Sandreas.hansson@arm.com return true; 65911051Sandreas.hansson@arm.com } 66011051Sandreas.hansson@arm.com 66111051Sandreas.hansson@arm.com promoteWholeLineWrites(pkt); 66211051Sandreas.hansson@arm.com 66312349Snikos.nikoleris@arm.com // Cache maintenance operations have to visit all the caches down 66412349Snikos.nikoleris@arm.com // to the specified xbar (PoC, PoU, etc.). Even if a cache above 66512349Snikos.nikoleris@arm.com // is responding we forward the packet to the memory below rather 66612349Snikos.nikoleris@arm.com // than creating an express snoop. 66711284Sandreas.hansson@arm.com if (pkt->cacheResponding()) { 66811051Sandreas.hansson@arm.com // a cache above us (but not where the packet came from) is 66911284Sandreas.hansson@arm.com // responding to the request, in other words it has the line 67011284Sandreas.hansson@arm.com // in Modified or Owned state 67111744Snikos.nikoleris@arm.com DPRINTF(Cache, "Cache above responding to %s: not responding\n", 67211744Snikos.nikoleris@arm.com pkt->print()); 67311051Sandreas.hansson@arm.com 67411284Sandreas.hansson@arm.com // if the packet needs the block to be writable, and the cache 67511284Sandreas.hansson@arm.com // that has promised to respond (setting the cache responding 67611284Sandreas.hansson@arm.com // flag) is not providing writable (it is in Owned rather than 67711284Sandreas.hansson@arm.com // the Modified state), we know that there may be other Shared 67811284Sandreas.hansson@arm.com // copies in the system; go out and invalidate them all 67911334Sandreas.hansson@arm.com assert(pkt->needsWritable() && !pkt->responderHadWritable()); 68011284Sandreas.hansson@arm.com 68111334Sandreas.hansson@arm.com // an upstream cache that had the line in Owned state 68211334Sandreas.hansson@arm.com // (dirty, but not writable), is responding and thus 68311334Sandreas.hansson@arm.com // transferring the dirty line from one branch of the 68411334Sandreas.hansson@arm.com // cache hierarchy to another 68511284Sandreas.hansson@arm.com 68611334Sandreas.hansson@arm.com // send out an express snoop and invalidate all other 68711334Sandreas.hansson@arm.com // copies (snooping a packet that needs writable is the 68811334Sandreas.hansson@arm.com // same as an invalidation), thus turning the Owned line 68911334Sandreas.hansson@arm.com // into a Modified line, note that we don't invalidate the 69011334Sandreas.hansson@arm.com // block in the current cache or any other cache on the 69111334Sandreas.hansson@arm.com // path to memory 69211051Sandreas.hansson@arm.com 69311334Sandreas.hansson@arm.com // create a downstream express snoop with cleared packet 69411334Sandreas.hansson@arm.com // flags, there is no need to allocate any data as the 69511334Sandreas.hansson@arm.com // packet is merely used to co-ordinate state transitions 69611334Sandreas.hansson@arm.com Packet *snoop_pkt = new Packet(pkt, true, false); 69711051Sandreas.hansson@arm.com 69811334Sandreas.hansson@arm.com // also reset the bus time that the original packet has 69911334Sandreas.hansson@arm.com // not yet paid for 70011334Sandreas.hansson@arm.com snoop_pkt->headerDelay = snoop_pkt->payloadDelay = 0; 70111051Sandreas.hansson@arm.com 70211334Sandreas.hansson@arm.com // make this an instantaneous express snoop, and let the 70311334Sandreas.hansson@arm.com // other caches in the system know that the another cache 70411334Sandreas.hansson@arm.com // is responding, because we have found the authorative 70511334Sandreas.hansson@arm.com // copy (Modified or Owned) that will supply the right 70611334Sandreas.hansson@arm.com // data 70711334Sandreas.hansson@arm.com snoop_pkt->setExpressSnoop(); 70811334Sandreas.hansson@arm.com snoop_pkt->setCacheResponding(); 70911051Sandreas.hansson@arm.com 71011334Sandreas.hansson@arm.com // this express snoop travels towards the memory, and at 71111334Sandreas.hansson@arm.com // every crossbar it is snooped upwards thus reaching 71211334Sandreas.hansson@arm.com // every cache in the system 71311334Sandreas.hansson@arm.com bool M5_VAR_USED success = memSidePort->sendTimingReq(snoop_pkt); 71411334Sandreas.hansson@arm.com // express snoops always succeed 71511334Sandreas.hansson@arm.com assert(success); 71611334Sandreas.hansson@arm.com 71711334Sandreas.hansson@arm.com // main memory will delete the snoop packet 71811051Sandreas.hansson@arm.com 71911284Sandreas.hansson@arm.com // queue for deletion, as opposed to immediate deletion, as 72011284Sandreas.hansson@arm.com // the sending cache is still relying on the packet 72111190Sandreas.hansson@arm.com pendingDelete.reset(pkt); 72211051Sandreas.hansson@arm.com 72311334Sandreas.hansson@arm.com // no need to take any further action in this particular cache 72411334Sandreas.hansson@arm.com // as an upstram cache has already committed to responding, 72511334Sandreas.hansson@arm.com // and we have already sent out any express snoops in the 72611334Sandreas.hansson@arm.com // section above to ensure all other copies in the system are 72711334Sandreas.hansson@arm.com // invalidated 72811051Sandreas.hansson@arm.com return true; 72911051Sandreas.hansson@arm.com } 73011051Sandreas.hansson@arm.com 73111051Sandreas.hansson@arm.com // anything that is merely forwarded pays for the forward latency and 73211051Sandreas.hansson@arm.com // the delay provided by the crossbar 73311051Sandreas.hansson@arm.com Tick forward_time = clockEdge(forwardLatency) + pkt->headerDelay; 73411051Sandreas.hansson@arm.com 73511051Sandreas.hansson@arm.com // We use lookupLatency here because it is used to specify the latency 73611051Sandreas.hansson@arm.com // to access. 73711051Sandreas.hansson@arm.com Cycles lat = lookupLatency; 73811484Snikos.nikoleris@arm.com CacheBlk *blk = nullptr; 73911051Sandreas.hansson@arm.com bool satisfied = false; 74011051Sandreas.hansson@arm.com { 74111051Sandreas.hansson@arm.com PacketList writebacks; 74211051Sandreas.hansson@arm.com // Note that lat is passed by reference here. The function 74311051Sandreas.hansson@arm.com // access() calls accessBlock() which can modify lat value. 74411051Sandreas.hansson@arm.com satisfied = access(pkt, blk, lat, writebacks); 74511051Sandreas.hansson@arm.com 74611051Sandreas.hansson@arm.com // copy writebacks to write buffer here to ensure they logically 74711051Sandreas.hansson@arm.com // proceed anything happening below 74811051Sandreas.hansson@arm.com doWritebacks(writebacks, forward_time); 74911051Sandreas.hansson@arm.com } 75011051Sandreas.hansson@arm.com 75111051Sandreas.hansson@arm.com // Here we charge the headerDelay that takes into account the latencies 75211051Sandreas.hansson@arm.com // of the bus, if the packet comes from it. 75311051Sandreas.hansson@arm.com // The latency charged it is just lat that is the value of lookupLatency 75411051Sandreas.hansson@arm.com // modified by access() function, or if not just lookupLatency. 75511051Sandreas.hansson@arm.com // In case of a hit we are neglecting response latency. 75611051Sandreas.hansson@arm.com // In case of a miss we are neglecting forward latency. 75711051Sandreas.hansson@arm.com Tick request_time = clockEdge(lat) + pkt->headerDelay; 75811051Sandreas.hansson@arm.com // Here we reset the timing of the packet. 75911051Sandreas.hansson@arm.com pkt->headerDelay = pkt->payloadDelay = 0; 76011051Sandreas.hansson@arm.com 76111051Sandreas.hansson@arm.com // track time of availability of next prefetch, if any 76211051Sandreas.hansson@arm.com Tick next_pf_time = MaxTick; 76311051Sandreas.hansson@arm.com 76411051Sandreas.hansson@arm.com bool needsResponse = pkt->needsResponse(); 76511051Sandreas.hansson@arm.com 76611051Sandreas.hansson@arm.com if (satisfied) { 76711051Sandreas.hansson@arm.com // should never be satisfying an uncacheable access as we 76811051Sandreas.hansson@arm.com // flush and invalidate any existing block as part of the 76911051Sandreas.hansson@arm.com // lookup 77011051Sandreas.hansson@arm.com assert(!pkt->req->isUncacheable()); 77111051Sandreas.hansson@arm.com 77211051Sandreas.hansson@arm.com // hit (for all other request types) 77311051Sandreas.hansson@arm.com 77411483Snikos.nikoleris@arm.com if (prefetcher && (prefetchOnAccess || 77511483Snikos.nikoleris@arm.com (blk && blk->wasPrefetched()))) { 77611051Sandreas.hansson@arm.com if (blk) 77711051Sandreas.hansson@arm.com blk->status &= ~BlkHWPrefetched; 77811051Sandreas.hansson@arm.com 77911051Sandreas.hansson@arm.com // Don't notify on SWPrefetch 78012349Snikos.nikoleris@arm.com if (!pkt->cmd.isSWPrefetch()) { 78112349Snikos.nikoleris@arm.com assert(!pkt->req->isCacheMaintenance()); 78211051Sandreas.hansson@arm.com next_pf_time = prefetcher->notify(pkt); 78312349Snikos.nikoleris@arm.com } 78411051Sandreas.hansson@arm.com } 78511051Sandreas.hansson@arm.com 78611051Sandreas.hansson@arm.com if (needsResponse) { 78711051Sandreas.hansson@arm.com pkt->makeTimingResponse(); 78811051Sandreas.hansson@arm.com // @todo: Make someone pay for this 78911051Sandreas.hansson@arm.com pkt->headerDelay = pkt->payloadDelay = 0; 79011051Sandreas.hansson@arm.com 79111051Sandreas.hansson@arm.com // In this case we are considering request_time that takes 79211051Sandreas.hansson@arm.com // into account the delay of the xbar, if any, and just 79311051Sandreas.hansson@arm.com // lat, neglecting responseLatency, modelling hit latency 79411051Sandreas.hansson@arm.com // just as lookupLatency or or the value of lat overriden 79511051Sandreas.hansson@arm.com // by access(), that calls accessBlock() function. 79611194Sali.jafri@arm.com cpuSidePort->schedTimingResp(pkt, request_time, true); 79711051Sandreas.hansson@arm.com } else { 79811744Snikos.nikoleris@arm.com DPRINTF(Cache, "%s satisfied %s, no response needed\n", __func__, 79911744Snikos.nikoleris@arm.com pkt->print()); 80011199Sandreas.hansson@arm.com 80111190Sandreas.hansson@arm.com // queue the packet for deletion, as the sending cache is 80211190Sandreas.hansson@arm.com // still relying on it; if the block is found in access(), 80311190Sandreas.hansson@arm.com // CleanEvict and Writeback messages will be deleted 80411190Sandreas.hansson@arm.com // here as well 80511190Sandreas.hansson@arm.com pendingDelete.reset(pkt); 80611051Sandreas.hansson@arm.com } 80711051Sandreas.hansson@arm.com } else { 80811051Sandreas.hansson@arm.com // miss 80911051Sandreas.hansson@arm.com 81011892Snikos.nikoleris@arm.com Addr blk_addr = pkt->getBlockAddr(blkSize); 81111051Sandreas.hansson@arm.com 81211051Sandreas.hansson@arm.com // ignore any existing MSHR if we are dealing with an 81311051Sandreas.hansson@arm.com // uncacheable request 81411051Sandreas.hansson@arm.com MSHR *mshr = pkt->req->isUncacheable() ? nullptr : 81511051Sandreas.hansson@arm.com mshrQueue.findMatch(blk_addr, pkt->isSecure()); 81611051Sandreas.hansson@arm.com 81711051Sandreas.hansson@arm.com // Software prefetch handling: 81811051Sandreas.hansson@arm.com // To keep the core from waiting on data it won't look at 81911051Sandreas.hansson@arm.com // anyway, send back a response with dummy data. Miss handling 82011051Sandreas.hansson@arm.com // will continue asynchronously. Unfortunately, the core will 82111051Sandreas.hansson@arm.com // insist upon freeing original Packet/Request, so we have to 82211051Sandreas.hansson@arm.com // create a new pair with a different lifecycle. Note that this 82311051Sandreas.hansson@arm.com // processing happens before any MSHR munging on the behalf of 82411051Sandreas.hansson@arm.com // this request because this new Request will be the one stored 82511051Sandreas.hansson@arm.com // into the MSHRs, not the original. 82611051Sandreas.hansson@arm.com if (pkt->cmd.isSWPrefetch()) { 82711051Sandreas.hansson@arm.com assert(needsResponse); 82811051Sandreas.hansson@arm.com assert(pkt->req->hasPaddr()); 82911051Sandreas.hansson@arm.com assert(!pkt->req->isUncacheable()); 83011051Sandreas.hansson@arm.com 83111051Sandreas.hansson@arm.com // There's no reason to add a prefetch as an additional target 83211051Sandreas.hansson@arm.com // to an existing MSHR. If an outstanding request is already 83311051Sandreas.hansson@arm.com // in progress, there is nothing for the prefetch to do. 83411051Sandreas.hansson@arm.com // If this is the case, we don't even create a request at all. 83511051Sandreas.hansson@arm.com PacketPtr pf = nullptr; 83611051Sandreas.hansson@arm.com 83711051Sandreas.hansson@arm.com if (!mshr) { 83811051Sandreas.hansson@arm.com // copy the request and create a new SoftPFReq packet 83911051Sandreas.hansson@arm.com RequestPtr req = new Request(pkt->req->getPaddr(), 84011051Sandreas.hansson@arm.com pkt->req->getSize(), 84111051Sandreas.hansson@arm.com pkt->req->getFlags(), 84211051Sandreas.hansson@arm.com pkt->req->masterId()); 84311051Sandreas.hansson@arm.com pf = new Packet(req, pkt->cmd); 84411051Sandreas.hansson@arm.com pf->allocate(); 84511051Sandreas.hansson@arm.com assert(pf->getAddr() == pkt->getAddr()); 84611051Sandreas.hansson@arm.com assert(pf->getSize() == pkt->getSize()); 84711051Sandreas.hansson@arm.com } 84811051Sandreas.hansson@arm.com 84911051Sandreas.hansson@arm.com pkt->makeTimingResponse(); 85011286Sandreas.hansson@arm.com 85111051Sandreas.hansson@arm.com // request_time is used here, taking into account lat and the delay 85211051Sandreas.hansson@arm.com // charged if the packet comes from the xbar. 85311194Sali.jafri@arm.com cpuSidePort->schedTimingResp(pkt, request_time, true); 85411051Sandreas.hansson@arm.com 85511051Sandreas.hansson@arm.com // If an outstanding request is in progress (we found an 85611051Sandreas.hansson@arm.com // MSHR) this is set to null 85711051Sandreas.hansson@arm.com pkt = pf; 85811051Sandreas.hansson@arm.com } 85911051Sandreas.hansson@arm.com 86011051Sandreas.hansson@arm.com if (mshr) { 86111051Sandreas.hansson@arm.com /// MSHR hit 86211051Sandreas.hansson@arm.com /// @note writebacks will be checked in getNextMSHR() 86311051Sandreas.hansson@arm.com /// for any conflicting requests to the same block 86411051Sandreas.hansson@arm.com 86511051Sandreas.hansson@arm.com //@todo remove hw_pf here 86611051Sandreas.hansson@arm.com 86711051Sandreas.hansson@arm.com // Coalesce unless it was a software prefetch (see above). 86811051Sandreas.hansson@arm.com if (pkt) { 86911199Sandreas.hansson@arm.com assert(!pkt->isWriteback()); 87011199Sandreas.hansson@arm.com // CleanEvicts corresponding to blocks which have 87111199Sandreas.hansson@arm.com // outstanding requests in MSHRs are simply sunk here 87211051Sandreas.hansson@arm.com if (pkt->cmd == MemCmd::CleanEvict) { 87311190Sandreas.hansson@arm.com pendingDelete.reset(pkt); 87412349Snikos.nikoleris@arm.com } else if (pkt->cmd == MemCmd::WriteClean) { 87512349Snikos.nikoleris@arm.com // A WriteClean should never coalesce with any 87612349Snikos.nikoleris@arm.com // outstanding cache maintenance requests. 87712349Snikos.nikoleris@arm.com 87812349Snikos.nikoleris@arm.com // We use forward_time here because there is an 87912349Snikos.nikoleris@arm.com // uncached memory write, forwarded to WriteBuffer. 88012349Snikos.nikoleris@arm.com allocateWriteBuffer(pkt, forward_time); 88111051Sandreas.hansson@arm.com } else { 88211744Snikos.nikoleris@arm.com DPRINTF(Cache, "%s coalescing MSHR for %s\n", __func__, 88311744Snikos.nikoleris@arm.com pkt->print()); 88411051Sandreas.hansson@arm.com 88511051Sandreas.hansson@arm.com assert(pkt->req->masterId() < system->maxMasters()); 88611051Sandreas.hansson@arm.com mshr_hits[pkt->cmdToIndex()][pkt->req->masterId()]++; 88711051Sandreas.hansson@arm.com // We use forward_time here because it is the same 88811051Sandreas.hansson@arm.com // considering new targets. We have multiple 88911051Sandreas.hansson@arm.com // requests for the same address here. It 89011051Sandreas.hansson@arm.com // specifies the latency to allocate an internal 89111051Sandreas.hansson@arm.com // buffer and to schedule an event to the queued 89211051Sandreas.hansson@arm.com // port and also takes into account the additional 89311051Sandreas.hansson@arm.com // delay of the xbar. 89411197Sandreas.hansson@arm.com mshr->allocateTarget(pkt, forward_time, order++, 89511197Sandreas.hansson@arm.com allocOnFill(pkt->cmd)); 89611051Sandreas.hansson@arm.com if (mshr->getNumTargets() == numTarget) { 89711051Sandreas.hansson@arm.com noTargetMSHR = mshr; 89811051Sandreas.hansson@arm.com setBlocked(Blocked_NoTargets); 89911051Sandreas.hansson@arm.com // need to be careful with this... if this mshr isn't 90011051Sandreas.hansson@arm.com // ready yet (i.e. time > curTick()), we don't want to 90111051Sandreas.hansson@arm.com // move it ahead of mshrs that are ready 90211051Sandreas.hansson@arm.com // mshrQueue.moveToFront(mshr); 90311051Sandreas.hansson@arm.com } 90411051Sandreas.hansson@arm.com } 90511051Sandreas.hansson@arm.com // We should call the prefetcher reguardless if the request is 90611483Snikos.nikoleris@arm.com // satisfied or not, reguardless if the request is in the MSHR 90711483Snikos.nikoleris@arm.com // or not. The request could be a ReadReq hit, but still not 90811051Sandreas.hansson@arm.com // satisfied (potentially because of a prior write to the same 90911051Sandreas.hansson@arm.com // cache line. So, even when not satisfied, tehre is an MSHR 91011483Snikos.nikoleris@arm.com // already allocated for this, we need to let the prefetcher 91111483Snikos.nikoleris@arm.com // know about the request 91211051Sandreas.hansson@arm.com if (prefetcher) { 91311051Sandreas.hansson@arm.com // Don't notify on SWPrefetch 91412349Snikos.nikoleris@arm.com if (!pkt->cmd.isSWPrefetch() && 91512349Snikos.nikoleris@arm.com !pkt->req->isCacheMaintenance()) 91611051Sandreas.hansson@arm.com next_pf_time = prefetcher->notify(pkt); 91711051Sandreas.hansson@arm.com } 91811051Sandreas.hansson@arm.com } 91911051Sandreas.hansson@arm.com } else { 92011051Sandreas.hansson@arm.com // no MSHR 92111051Sandreas.hansson@arm.com assert(pkt->req->masterId() < system->maxMasters()); 92211051Sandreas.hansson@arm.com if (pkt->req->isUncacheable()) { 92311051Sandreas.hansson@arm.com mshr_uncacheable[pkt->cmdToIndex()][pkt->req->masterId()]++; 92411051Sandreas.hansson@arm.com } else { 92511051Sandreas.hansson@arm.com mshr_misses[pkt->cmdToIndex()][pkt->req->masterId()]++; 92611051Sandreas.hansson@arm.com } 92711051Sandreas.hansson@arm.com 92812345Snikos.nikoleris@arm.com if (pkt->isEviction() || pkt->cmd == MemCmd::WriteClean || 92911051Sandreas.hansson@arm.com (pkt->req->isUncacheable() && pkt->isWrite())) { 93011051Sandreas.hansson@arm.com // We use forward_time here because there is an 93111051Sandreas.hansson@arm.com // uncached memory write, forwarded to WriteBuffer. 93211051Sandreas.hansson@arm.com allocateWriteBuffer(pkt, forward_time); 93311051Sandreas.hansson@arm.com } else { 93411051Sandreas.hansson@arm.com if (blk && blk->isValid()) { 93511051Sandreas.hansson@arm.com // should have flushed and have no valid block 93611051Sandreas.hansson@arm.com assert(!pkt->req->isUncacheable()); 93711051Sandreas.hansson@arm.com 93811051Sandreas.hansson@arm.com // If we have a write miss to a valid block, we 93911051Sandreas.hansson@arm.com // need to mark the block non-readable. Otherwise 94011051Sandreas.hansson@arm.com // if we allow reads while there's an outstanding 94111051Sandreas.hansson@arm.com // write miss, the read could return stale data 94211051Sandreas.hansson@arm.com // out of the cache block... a more aggressive 94311051Sandreas.hansson@arm.com // system could detect the overlap (if any) and 94411051Sandreas.hansson@arm.com // forward data out of the MSHRs, but we don't do 94511051Sandreas.hansson@arm.com // that yet. Note that we do need to leave the 94611051Sandreas.hansson@arm.com // block valid so that it stays in the cache, in 94711051Sandreas.hansson@arm.com // case we get an upgrade response (and hence no 94811051Sandreas.hansson@arm.com // new data) when the write miss completes. 94911051Sandreas.hansson@arm.com // As long as CPUs do proper store/load forwarding 95011051Sandreas.hansson@arm.com // internally, and have a sufficiently weak memory 95111051Sandreas.hansson@arm.com // model, this is probably unnecessary, but at some 95211051Sandreas.hansson@arm.com // point it must have seemed like we needed it... 95312349Snikos.nikoleris@arm.com assert((pkt->needsWritable() && !blk->isWritable()) || 95412349Snikos.nikoleris@arm.com pkt->req->isCacheMaintenance()); 95511051Sandreas.hansson@arm.com blk->status &= ~BlkReadable; 95611051Sandreas.hansson@arm.com } 95711051Sandreas.hansson@arm.com // Here we are using forward_time, modelling the latency of 95811051Sandreas.hansson@arm.com // a miss (outbound) just as forwardLatency, neglecting the 95911051Sandreas.hansson@arm.com // lookupLatency component. 96011051Sandreas.hansson@arm.com allocateMissBuffer(pkt, forward_time); 96111051Sandreas.hansson@arm.com } 96211051Sandreas.hansson@arm.com 96311051Sandreas.hansson@arm.com if (prefetcher) { 96411051Sandreas.hansson@arm.com // Don't notify on SWPrefetch 96512349Snikos.nikoleris@arm.com if (!pkt->cmd.isSWPrefetch() && 96612349Snikos.nikoleris@arm.com !pkt->req->isCacheMaintenance()) 96711051Sandreas.hansson@arm.com next_pf_time = prefetcher->notify(pkt); 96811051Sandreas.hansson@arm.com } 96911051Sandreas.hansson@arm.com } 97011051Sandreas.hansson@arm.com } 97111051Sandreas.hansson@arm.com 97211051Sandreas.hansson@arm.com if (next_pf_time != MaxTick) 97311051Sandreas.hansson@arm.com schedMemSideSendEvent(next_pf_time); 97411051Sandreas.hansson@arm.com 97511051Sandreas.hansson@arm.com return true; 97611051Sandreas.hansson@arm.com} 97711051Sandreas.hansson@arm.com 97811051Sandreas.hansson@arm.comPacketPtr 97911452Sandreas.hansson@arm.comCache::createMissPacket(PacketPtr cpu_pkt, CacheBlk *blk, 98011452Sandreas.hansson@arm.com bool needsWritable) const 98111051Sandreas.hansson@arm.com{ 98211452Sandreas.hansson@arm.com // should never see evictions here 98311452Sandreas.hansson@arm.com assert(!cpu_pkt->isEviction()); 98411452Sandreas.hansson@arm.com 98511051Sandreas.hansson@arm.com bool blkValid = blk && blk->isValid(); 98611051Sandreas.hansson@arm.com 98711452Sandreas.hansson@arm.com if (cpu_pkt->req->isUncacheable() || 98811745Sandreas.hansson@arm.com (!blkValid && cpu_pkt->isUpgrade()) || 98912349Snikos.nikoleris@arm.com cpu_pkt->cmd == MemCmd::InvalidateReq || cpu_pkt->isClean()) { 99011452Sandreas.hansson@arm.com // uncacheable requests and upgrades from upper-level caches 99111452Sandreas.hansson@arm.com // that missed completely just go through as is 99211452Sandreas.hansson@arm.com return nullptr; 99311051Sandreas.hansson@arm.com } 99411051Sandreas.hansson@arm.com 99511051Sandreas.hansson@arm.com assert(cpu_pkt->needsResponse()); 99611051Sandreas.hansson@arm.com 99711051Sandreas.hansson@arm.com MemCmd cmd; 99811051Sandreas.hansson@arm.com // @TODO make useUpgrades a parameter. 99911051Sandreas.hansson@arm.com // Note that ownership protocols require upgrade, otherwise a 100011051Sandreas.hansson@arm.com // write miss on a shared owned block will generate a ReadExcl, 100111051Sandreas.hansson@arm.com // which will clobber the owned copy. 100211051Sandreas.hansson@arm.com const bool useUpgrades = true; 100311747Snikos.nikoleris@arm.com if (cpu_pkt->cmd == MemCmd::WriteLineReq) { 100411747Snikos.nikoleris@arm.com assert(!blkValid || !blk->isWritable()); 100511747Snikos.nikoleris@arm.com // forward as invalidate to all other caches, this gives us 100611747Snikos.nikoleris@arm.com // the line in Exclusive state, and invalidates all other 100711747Snikos.nikoleris@arm.com // copies 100811747Snikos.nikoleris@arm.com cmd = MemCmd::InvalidateReq; 100911747Snikos.nikoleris@arm.com } else if (blkValid && useUpgrades) { 101011284Sandreas.hansson@arm.com // only reason to be here is that blk is read only and we need 101111284Sandreas.hansson@arm.com // it to be writable 101211284Sandreas.hansson@arm.com assert(needsWritable); 101311051Sandreas.hansson@arm.com assert(!blk->isWritable()); 101411051Sandreas.hansson@arm.com cmd = cpu_pkt->isLLSC() ? MemCmd::SCUpgradeReq : MemCmd::UpgradeReq; 101511051Sandreas.hansson@arm.com } else if (cpu_pkt->cmd == MemCmd::SCUpgradeFailReq || 101611051Sandreas.hansson@arm.com cpu_pkt->cmd == MemCmd::StoreCondFailReq) { 101711051Sandreas.hansson@arm.com // Even though this SC will fail, we still need to send out the 101811051Sandreas.hansson@arm.com // request and get the data to supply it to other snoopers in the case 101911051Sandreas.hansson@arm.com // where the determination the StoreCond fails is delayed due to 102011051Sandreas.hansson@arm.com // all caches not being on the same local bus. 102111051Sandreas.hansson@arm.com cmd = MemCmd::SCUpgradeFailReq; 102211051Sandreas.hansson@arm.com } else { 102311051Sandreas.hansson@arm.com // block is invalid 102412425Snikos.nikoleris@arm.com 102512425Snikos.nikoleris@arm.com // If the request does not need a writable there are two cases 102612425Snikos.nikoleris@arm.com // where we need to ensure the response will not fetch the 102712425Snikos.nikoleris@arm.com // block in dirty state: 102812425Snikos.nikoleris@arm.com // * this cache is read only and it does not perform 102912425Snikos.nikoleris@arm.com // writebacks, 103012425Snikos.nikoleris@arm.com // * this cache is mostly exclusive and will not fill (since 103112425Snikos.nikoleris@arm.com // it does not fill it will have to writeback the dirty data 103212425Snikos.nikoleris@arm.com // immediately which generates uneccesary writebacks). 103312425Snikos.nikoleris@arm.com bool force_clean_rsp = isReadOnly || clusivity == Enums::mostly_excl; 103411284Sandreas.hansson@arm.com cmd = needsWritable ? MemCmd::ReadExReq : 103512425Snikos.nikoleris@arm.com (force_clean_rsp ? MemCmd::ReadCleanReq : MemCmd::ReadSharedReq); 103611051Sandreas.hansson@arm.com } 103711051Sandreas.hansson@arm.com PacketPtr pkt = new Packet(cpu_pkt->req, cmd, blkSize); 103811051Sandreas.hansson@arm.com 103911284Sandreas.hansson@arm.com // if there are upstream caches that have already marked the 104011284Sandreas.hansson@arm.com // packet as having sharers (not passing writable), pass that info 104111284Sandreas.hansson@arm.com // downstream 104211602Sandreas.hansson@arm.com if (cpu_pkt->hasSharers() && !needsWritable) { 104311051Sandreas.hansson@arm.com // note that cpu_pkt may have spent a considerable time in the 104411051Sandreas.hansson@arm.com // MSHR queue and that the information could possibly be out 104511051Sandreas.hansson@arm.com // of date, however, there is no harm in conservatively 104611284Sandreas.hansson@arm.com // assuming the block has sharers 104711284Sandreas.hansson@arm.com pkt->setHasSharers(); 104811744Snikos.nikoleris@arm.com DPRINTF(Cache, "%s: passing hasSharers from %s to %s\n", 104911744Snikos.nikoleris@arm.com __func__, cpu_pkt->print(), pkt->print()); 105011051Sandreas.hansson@arm.com } 105111051Sandreas.hansson@arm.com 105211051Sandreas.hansson@arm.com // the packet should be block aligned 105311892Snikos.nikoleris@arm.com assert(pkt->getAddr() == pkt->getBlockAddr(blkSize)); 105411051Sandreas.hansson@arm.com 105511051Sandreas.hansson@arm.com pkt->allocate(); 105611744Snikos.nikoleris@arm.com DPRINTF(Cache, "%s: created %s from %s\n", __func__, pkt->print(), 105711744Snikos.nikoleris@arm.com cpu_pkt->print()); 105811051Sandreas.hansson@arm.com return pkt; 105911051Sandreas.hansson@arm.com} 106011051Sandreas.hansson@arm.com 106111051Sandreas.hansson@arm.com 106211051Sandreas.hansson@arm.comTick 106311051Sandreas.hansson@arm.comCache::recvAtomic(PacketPtr pkt) 106411051Sandreas.hansson@arm.com{ 106511051Sandreas.hansson@arm.com // We are in atomic mode so we pay just for lookupLatency here. 106611051Sandreas.hansson@arm.com Cycles lat = lookupLatency; 106711051Sandreas.hansson@arm.com 106811051Sandreas.hansson@arm.com // Forward the request if the system is in cache bypass mode. 106911051Sandreas.hansson@arm.com if (system->bypassCaches()) 107011051Sandreas.hansson@arm.com return ticksToCycles(memSidePort->sendAtomic(pkt)); 107111051Sandreas.hansson@arm.com 107211051Sandreas.hansson@arm.com promoteWholeLineWrites(pkt); 107311051Sandreas.hansson@arm.com 107411333Sandreas.hansson@arm.com // follow the same flow as in recvTimingReq, and check if a cache 107511333Sandreas.hansson@arm.com // above us is responding 107612349Snikos.nikoleris@arm.com if (pkt->cacheResponding() && !pkt->isClean()) { 107712349Snikos.nikoleris@arm.com assert(!pkt->req->isCacheInvalidate()); 107811744Snikos.nikoleris@arm.com DPRINTF(Cache, "Cache above responding to %s: not responding\n", 107911744Snikos.nikoleris@arm.com pkt->print()); 108011333Sandreas.hansson@arm.com 108111333Sandreas.hansson@arm.com // if a cache is responding, and it had the line in Owned 108211333Sandreas.hansson@arm.com // rather than Modified state, we need to invalidate any 108311333Sandreas.hansson@arm.com // copies that are not on the same path to memory 108411334Sandreas.hansson@arm.com assert(pkt->needsWritable() && !pkt->responderHadWritable()); 108511334Sandreas.hansson@arm.com lat += ticksToCycles(memSidePort->sendAtomic(pkt)); 108611051Sandreas.hansson@arm.com 108711051Sandreas.hansson@arm.com return lat * clockPeriod(); 108811051Sandreas.hansson@arm.com } 108911051Sandreas.hansson@arm.com 109011051Sandreas.hansson@arm.com // should assert here that there are no outstanding MSHRs or 109111051Sandreas.hansson@arm.com // writebacks... that would mean that someone used an atomic 109211051Sandreas.hansson@arm.com // access in timing mode 109311051Sandreas.hansson@arm.com 109411484Snikos.nikoleris@arm.com CacheBlk *blk = nullptr; 109511051Sandreas.hansson@arm.com PacketList writebacks; 109611051Sandreas.hansson@arm.com bool satisfied = access(pkt, blk, lat, writebacks); 109711051Sandreas.hansson@arm.com 109812349Snikos.nikoleris@arm.com if (pkt->isClean() && blk && blk->isDirty()) { 109912349Snikos.nikoleris@arm.com // A cache clean opearation is looking for a dirty 110012349Snikos.nikoleris@arm.com // block. If a dirty block is encountered a WriteClean 110112349Snikos.nikoleris@arm.com // will update any copies to the path to the memory 110212349Snikos.nikoleris@arm.com // until the point of reference. 110312349Snikos.nikoleris@arm.com DPRINTF(CacheVerbose, "%s: packet %s found block: %s\n", 110412349Snikos.nikoleris@arm.com __func__, pkt->print(), blk->print()); 110512351Snikos.nikoleris@arm.com PacketPtr wb_pkt = writecleanBlk(blk, pkt->req->getDest(), pkt->id); 110612349Snikos.nikoleris@arm.com writebacks.push_back(wb_pkt); 110712349Snikos.nikoleris@arm.com pkt->setSatisfied(); 110812349Snikos.nikoleris@arm.com } 110912349Snikos.nikoleris@arm.com 111011051Sandreas.hansson@arm.com // handle writebacks resulting from the access here to ensure they 111111051Sandreas.hansson@arm.com // logically proceed anything happening below 111211130Sali.jafri@arm.com doWritebacksAtomic(writebacks); 111311051Sandreas.hansson@arm.com 111411051Sandreas.hansson@arm.com if (!satisfied) { 111511051Sandreas.hansson@arm.com // MISS 111611051Sandreas.hansson@arm.com 111711452Sandreas.hansson@arm.com // deal with the packets that go through the write path of 111812345Snikos.nikoleris@arm.com // the cache, i.e. any evictions and writes 111912345Snikos.nikoleris@arm.com if (pkt->isEviction() || pkt->cmd == MemCmd::WriteClean || 112011452Sandreas.hansson@arm.com (pkt->req->isUncacheable() && pkt->isWrite())) { 112111452Sandreas.hansson@arm.com lat += ticksToCycles(memSidePort->sendAtomic(pkt)); 112211452Sandreas.hansson@arm.com return lat * clockPeriod(); 112311452Sandreas.hansson@arm.com } 112411452Sandreas.hansson@arm.com // only misses left 112511452Sandreas.hansson@arm.com 112611452Sandreas.hansson@arm.com PacketPtr bus_pkt = createMissPacket(pkt, blk, pkt->needsWritable()); 112711051Sandreas.hansson@arm.com 112811484Snikos.nikoleris@arm.com bool is_forward = (bus_pkt == nullptr); 112911051Sandreas.hansson@arm.com 113011051Sandreas.hansson@arm.com if (is_forward) { 113111051Sandreas.hansson@arm.com // just forwarding the same request to the next level 113211051Sandreas.hansson@arm.com // no local cache operation involved 113311051Sandreas.hansson@arm.com bus_pkt = pkt; 113411051Sandreas.hansson@arm.com } 113511051Sandreas.hansson@arm.com 113611744Snikos.nikoleris@arm.com DPRINTF(Cache, "%s: Sending an atomic %s\n", __func__, 113711744Snikos.nikoleris@arm.com bus_pkt->print()); 113811051Sandreas.hansson@arm.com 113911051Sandreas.hansson@arm.com#if TRACING_ON 114011051Sandreas.hansson@arm.com CacheBlk::State old_state = blk ? blk->status : 0; 114111051Sandreas.hansson@arm.com#endif 114211051Sandreas.hansson@arm.com 114311051Sandreas.hansson@arm.com lat += ticksToCycles(memSidePort->sendAtomic(bus_pkt)); 114411051Sandreas.hansson@arm.com 114511452Sandreas.hansson@arm.com bool is_invalidate = bus_pkt->isInvalidate(); 114611452Sandreas.hansson@arm.com 114711051Sandreas.hansson@arm.com // We are now dealing with the response handling 114811744Snikos.nikoleris@arm.com DPRINTF(Cache, "%s: Receive response: %s in state %i\n", __func__, 114911744Snikos.nikoleris@arm.com bus_pkt->print(), old_state); 115011051Sandreas.hansson@arm.com 115111051Sandreas.hansson@arm.com // If packet was a forward, the response (if any) is already 115211051Sandreas.hansson@arm.com // in place in the bus_pkt == pkt structure, so we don't need 115311051Sandreas.hansson@arm.com // to do anything. Otherwise, use the separate bus_pkt to 115411051Sandreas.hansson@arm.com // generate response to pkt and then delete it. 115511051Sandreas.hansson@arm.com if (!is_forward) { 115611051Sandreas.hansson@arm.com if (pkt->needsResponse()) { 115711051Sandreas.hansson@arm.com assert(bus_pkt->isResponse()); 115811051Sandreas.hansson@arm.com if (bus_pkt->isError()) { 115911051Sandreas.hansson@arm.com pkt->makeAtomicResponse(); 116011051Sandreas.hansson@arm.com pkt->copyError(bus_pkt); 116111051Sandreas.hansson@arm.com } else if (pkt->cmd == MemCmd::WriteLineReq) { 116211051Sandreas.hansson@arm.com // note the use of pkt, not bus_pkt here. 116311051Sandreas.hansson@arm.com 116411051Sandreas.hansson@arm.com // write-line request to the cache that promoted 116511051Sandreas.hansson@arm.com // the write to a whole line 116611197Sandreas.hansson@arm.com blk = handleFill(pkt, blk, writebacks, 116711197Sandreas.hansson@arm.com allocOnFill(pkt->cmd)); 116811452Sandreas.hansson@arm.com assert(blk != NULL); 116911452Sandreas.hansson@arm.com is_invalidate = false; 117011601Sandreas.hansson@arm.com satisfyRequest(pkt, blk); 117111051Sandreas.hansson@arm.com } else if (bus_pkt->isRead() || 117211051Sandreas.hansson@arm.com bus_pkt->cmd == MemCmd::UpgradeResp) { 117311051Sandreas.hansson@arm.com // we're updating cache state to allow us to 117411051Sandreas.hansson@arm.com // satisfy the upstream request from the cache 117511197Sandreas.hansson@arm.com blk = handleFill(bus_pkt, blk, writebacks, 117611197Sandreas.hansson@arm.com allocOnFill(pkt->cmd)); 117711601Sandreas.hansson@arm.com satisfyRequest(pkt, blk); 117811601Sandreas.hansson@arm.com maintainClusivity(pkt->fromCache(), blk); 117911051Sandreas.hansson@arm.com } else { 118011051Sandreas.hansson@arm.com // we're satisfying the upstream request without 118111051Sandreas.hansson@arm.com // modifying cache state, e.g., a write-through 118211051Sandreas.hansson@arm.com pkt->makeAtomicResponse(); 118311051Sandreas.hansson@arm.com } 118411051Sandreas.hansson@arm.com } 118511051Sandreas.hansson@arm.com delete bus_pkt; 118611051Sandreas.hansson@arm.com } 118711452Sandreas.hansson@arm.com 118811452Sandreas.hansson@arm.com if (is_invalidate && blk && blk->isValid()) { 118911452Sandreas.hansson@arm.com invalidateBlock(blk); 119011452Sandreas.hansson@arm.com } 119111051Sandreas.hansson@arm.com } 119211051Sandreas.hansson@arm.com 119311051Sandreas.hansson@arm.com // Note that we don't invoke the prefetcher at all in atomic mode. 119411051Sandreas.hansson@arm.com // It's not clear how to do it properly, particularly for 119511051Sandreas.hansson@arm.com // prefetchers that aggressively generate prefetch candidates and 119611051Sandreas.hansson@arm.com // rely on bandwidth contention to throttle them; these will tend 119711051Sandreas.hansson@arm.com // to pollute the cache in atomic mode since there is no bandwidth 119811051Sandreas.hansson@arm.com // contention. If we ever do want to enable prefetching in atomic 119911051Sandreas.hansson@arm.com // mode, though, this is the place to do it... see timingAccess() 120011051Sandreas.hansson@arm.com // for an example (though we'd want to issue the prefetch(es) 120111051Sandreas.hansson@arm.com // immediately rather than calling requestMemSideBus() as we do 120211051Sandreas.hansson@arm.com // there). 120311051Sandreas.hansson@arm.com 120411197Sandreas.hansson@arm.com // do any writebacks resulting from the response handling 120511130Sali.jafri@arm.com doWritebacksAtomic(writebacks); 120611051Sandreas.hansson@arm.com 120711197Sandreas.hansson@arm.com // if we used temp block, check to see if its valid and if so 120811197Sandreas.hansson@arm.com // clear it out, but only do so after the call to recvAtomic is 120911197Sandreas.hansson@arm.com // finished so that any downstream observers (such as a snoop 121011197Sandreas.hansson@arm.com // filter), first see the fill, and only then see the eviction 121111197Sandreas.hansson@arm.com if (blk == tempBlock && tempBlock->isValid()) { 121211197Sandreas.hansson@arm.com // the atomic CPU calls recvAtomic for fetch and load/store 121311197Sandreas.hansson@arm.com // sequentuially, and we may already have a tempBlock 121411197Sandreas.hansson@arm.com // writeback from the fetch that we have not yet sent 121511197Sandreas.hansson@arm.com if (tempBlockWriteback) { 121611197Sandreas.hansson@arm.com // if that is the case, write the prevoius one back, and 121711197Sandreas.hansson@arm.com // do not schedule any new event 121811197Sandreas.hansson@arm.com writebackTempBlockAtomic(); 121911197Sandreas.hansson@arm.com } else { 122011197Sandreas.hansson@arm.com // the writeback/clean eviction happens after the call to 122111197Sandreas.hansson@arm.com // recvAtomic has finished (but before any successive 122211197Sandreas.hansson@arm.com // calls), so that the response handling from the fill is 122311197Sandreas.hansson@arm.com // allowed to happen first 122411197Sandreas.hansson@arm.com schedule(writebackTempBlockAtomicEvent, curTick()); 122511197Sandreas.hansson@arm.com } 122611197Sandreas.hansson@arm.com 122711199Sandreas.hansson@arm.com tempBlockWriteback = (blk->isDirty() || writebackClean) ? 122811199Sandreas.hansson@arm.com writebackBlk(blk) : cleanEvictBlk(blk); 122911867Snikos.nikoleris@arm.com invalidateBlock(blk); 123011197Sandreas.hansson@arm.com } 123111197Sandreas.hansson@arm.com 123211051Sandreas.hansson@arm.com if (pkt->needsResponse()) { 123311051Sandreas.hansson@arm.com pkt->makeAtomicResponse(); 123411051Sandreas.hansson@arm.com } 123511051Sandreas.hansson@arm.com 123611051Sandreas.hansson@arm.com return lat * clockPeriod(); 123711051Sandreas.hansson@arm.com} 123811051Sandreas.hansson@arm.com 123911051Sandreas.hansson@arm.com 124011051Sandreas.hansson@arm.comvoid 124111051Sandreas.hansson@arm.comCache::functionalAccess(PacketPtr pkt, bool fromCpuSide) 124211051Sandreas.hansson@arm.com{ 124311051Sandreas.hansson@arm.com if (system->bypassCaches()) { 124411051Sandreas.hansson@arm.com // Packets from the memory side are snoop request and 124511051Sandreas.hansson@arm.com // shouldn't happen in bypass mode. 124611051Sandreas.hansson@arm.com assert(fromCpuSide); 124711051Sandreas.hansson@arm.com 124811051Sandreas.hansson@arm.com // The cache should be flushed if we are in cache bypass mode, 124911051Sandreas.hansson@arm.com // so we don't need to check if we need to update anything. 125011051Sandreas.hansson@arm.com memSidePort->sendFunctional(pkt); 125111051Sandreas.hansson@arm.com return; 125211051Sandreas.hansson@arm.com } 125311051Sandreas.hansson@arm.com 125411892Snikos.nikoleris@arm.com Addr blk_addr = pkt->getBlockAddr(blkSize); 125511051Sandreas.hansson@arm.com bool is_secure = pkt->isSecure(); 125611051Sandreas.hansson@arm.com CacheBlk *blk = tags->findBlock(pkt->getAddr(), is_secure); 125711051Sandreas.hansson@arm.com MSHR *mshr = mshrQueue.findMatch(blk_addr, is_secure); 125811051Sandreas.hansson@arm.com 125911051Sandreas.hansson@arm.com pkt->pushLabel(name()); 126011051Sandreas.hansson@arm.com 126111051Sandreas.hansson@arm.com CacheBlkPrintWrapper cbpw(blk); 126211051Sandreas.hansson@arm.com 126311051Sandreas.hansson@arm.com // Note that just because an L2/L3 has valid data doesn't mean an 126411051Sandreas.hansson@arm.com // L1 doesn't have a more up-to-date modified copy that still 126511051Sandreas.hansson@arm.com // needs to be found. As a result we always update the request if 126611051Sandreas.hansson@arm.com // we have it, but only declare it satisfied if we are the owner. 126711051Sandreas.hansson@arm.com 126811051Sandreas.hansson@arm.com // see if we have data at all (owned or otherwise) 126911051Sandreas.hansson@arm.com bool have_data = blk && blk->isValid() 127011051Sandreas.hansson@arm.com && pkt->checkFunctional(&cbpw, blk_addr, is_secure, blkSize, 127111051Sandreas.hansson@arm.com blk->data); 127211051Sandreas.hansson@arm.com 127311284Sandreas.hansson@arm.com // data we have is dirty if marked as such or if we have an 127411284Sandreas.hansson@arm.com // in-service MSHR that is pending a modified line 127511051Sandreas.hansson@arm.com bool have_dirty = 127611051Sandreas.hansson@arm.com have_data && (blk->isDirty() || 127711284Sandreas.hansson@arm.com (mshr && mshr->inService && mshr->isPendingModified())); 127811051Sandreas.hansson@arm.com 127911051Sandreas.hansson@arm.com bool done = have_dirty 128011051Sandreas.hansson@arm.com || cpuSidePort->checkFunctional(pkt) 128111051Sandreas.hansson@arm.com || mshrQueue.checkFunctional(pkt, blk_addr) 128211051Sandreas.hansson@arm.com || writeBuffer.checkFunctional(pkt, blk_addr) 128311051Sandreas.hansson@arm.com || memSidePort->checkFunctional(pkt); 128411051Sandreas.hansson@arm.com 128511744Snikos.nikoleris@arm.com DPRINTF(CacheVerbose, "%s: %s %s%s%s\n", __func__, pkt->print(), 128611051Sandreas.hansson@arm.com (blk && blk->isValid()) ? "valid " : "", 128711051Sandreas.hansson@arm.com have_data ? "data " : "", done ? "done " : ""); 128811051Sandreas.hansson@arm.com 128911051Sandreas.hansson@arm.com // We're leaving the cache, so pop cache->name() label 129011051Sandreas.hansson@arm.com pkt->popLabel(); 129111051Sandreas.hansson@arm.com 129211051Sandreas.hansson@arm.com if (done) { 129311051Sandreas.hansson@arm.com pkt->makeResponse(); 129411051Sandreas.hansson@arm.com } else { 129511051Sandreas.hansson@arm.com // if it came as a request from the CPU side then make sure it 129611051Sandreas.hansson@arm.com // continues towards the memory side 129711051Sandreas.hansson@arm.com if (fromCpuSide) { 129811051Sandreas.hansson@arm.com memSidePort->sendFunctional(pkt); 129911485Snikos.nikoleris@arm.com } else if (cpuSidePort->isSnooping()) { 130011051Sandreas.hansson@arm.com // if it came from the memory side, it must be a snoop request 130111051Sandreas.hansson@arm.com // and we should only forward it if we are forwarding snoops 130211051Sandreas.hansson@arm.com cpuSidePort->sendFunctionalSnoop(pkt); 130311051Sandreas.hansson@arm.com } 130411051Sandreas.hansson@arm.com } 130511051Sandreas.hansson@arm.com} 130611051Sandreas.hansson@arm.com 130711051Sandreas.hansson@arm.com 130811051Sandreas.hansson@arm.com///////////////////////////////////////////////////// 130911051Sandreas.hansson@arm.com// 131011051Sandreas.hansson@arm.com// Response handling: responses from the memory side 131111051Sandreas.hansson@arm.com// 131211051Sandreas.hansson@arm.com///////////////////////////////////////////////////// 131311051Sandreas.hansson@arm.com 131411051Sandreas.hansson@arm.com 131511051Sandreas.hansson@arm.comvoid 131611375Sandreas.hansson@arm.comCache::handleUncacheableWriteResp(PacketPtr pkt) 131711375Sandreas.hansson@arm.com{ 131811375Sandreas.hansson@arm.com Tick completion_time = clockEdge(responseLatency) + 131911375Sandreas.hansson@arm.com pkt->headerDelay + pkt->payloadDelay; 132011375Sandreas.hansson@arm.com 132111453Sandreas.hansson@arm.com // Reset the bus additional time as it is now accounted for 132211453Sandreas.hansson@arm.com pkt->headerDelay = pkt->payloadDelay = 0; 132311375Sandreas.hansson@arm.com 132411453Sandreas.hansson@arm.com cpuSidePort->schedTimingResp(pkt, completion_time, true); 132511375Sandreas.hansson@arm.com} 132611375Sandreas.hansson@arm.com 132711375Sandreas.hansson@arm.comvoid 132811051Sandreas.hansson@arm.comCache::recvTimingResp(PacketPtr pkt) 132911051Sandreas.hansson@arm.com{ 133011051Sandreas.hansson@arm.com assert(pkt->isResponse()); 133111051Sandreas.hansson@arm.com 133211051Sandreas.hansson@arm.com // all header delay should be paid for by the crossbar, unless 133311051Sandreas.hansson@arm.com // this is a prefetch response from above 133411051Sandreas.hansson@arm.com panic_if(pkt->headerDelay != 0 && pkt->cmd != MemCmd::HardPFResp, 133511051Sandreas.hansson@arm.com "%s saw a non-zero packet delay\n", name()); 133611051Sandreas.hansson@arm.com 133711051Sandreas.hansson@arm.com bool is_error = pkt->isError(); 133811051Sandreas.hansson@arm.com 133911051Sandreas.hansson@arm.com if (is_error) { 134011744Snikos.nikoleris@arm.com DPRINTF(Cache, "%s: Cache received %s with error\n", __func__, 134111744Snikos.nikoleris@arm.com pkt->print()); 134211051Sandreas.hansson@arm.com } 134311051Sandreas.hansson@arm.com 134411744Snikos.nikoleris@arm.com DPRINTF(Cache, "%s: Handling response %s\n", __func__, 134511744Snikos.nikoleris@arm.com pkt->print()); 134611051Sandreas.hansson@arm.com 134711375Sandreas.hansson@arm.com // if this is a write, we should be looking at an uncacheable 134811375Sandreas.hansson@arm.com // write 134911375Sandreas.hansson@arm.com if (pkt->isWrite()) { 135011375Sandreas.hansson@arm.com assert(pkt->req->isUncacheable()); 135111375Sandreas.hansson@arm.com handleUncacheableWriteResp(pkt); 135211375Sandreas.hansson@arm.com return; 135311375Sandreas.hansson@arm.com } 135411375Sandreas.hansson@arm.com 135511375Sandreas.hansson@arm.com // we have dealt with any (uncacheable) writes above, from here on 135611375Sandreas.hansson@arm.com // we know we are dealing with an MSHR due to a miss or a prefetch 135711453Sandreas.hansson@arm.com MSHR *mshr = dynamic_cast<MSHR*>(pkt->popSenderState()); 135811375Sandreas.hansson@arm.com assert(mshr); 135911051Sandreas.hansson@arm.com 136011051Sandreas.hansson@arm.com if (mshr == noTargetMSHR) { 136111051Sandreas.hansson@arm.com // we always clear at least one target 136211051Sandreas.hansson@arm.com clearBlocked(Blocked_NoTargets); 136311484Snikos.nikoleris@arm.com noTargetMSHR = nullptr; 136411051Sandreas.hansson@arm.com } 136511051Sandreas.hansson@arm.com 136611051Sandreas.hansson@arm.com // Initial target is used just for stats 136711051Sandreas.hansson@arm.com MSHR::Target *initial_tgt = mshr->getTarget(); 136811051Sandreas.hansson@arm.com int stats_cmd_idx = initial_tgt->pkt->cmdToIndex(); 136911051Sandreas.hansson@arm.com Tick miss_latency = curTick() - initial_tgt->recvTime; 137011051Sandreas.hansson@arm.com 137111051Sandreas.hansson@arm.com if (pkt->req->isUncacheable()) { 137211051Sandreas.hansson@arm.com assert(pkt->req->masterId() < system->maxMasters()); 137311051Sandreas.hansson@arm.com mshr_uncacheable_lat[stats_cmd_idx][pkt->req->masterId()] += 137411051Sandreas.hansson@arm.com miss_latency; 137511051Sandreas.hansson@arm.com } else { 137611051Sandreas.hansson@arm.com assert(pkt->req->masterId() < system->maxMasters()); 137711051Sandreas.hansson@arm.com mshr_miss_latency[stats_cmd_idx][pkt->req->masterId()] += 137811051Sandreas.hansson@arm.com miss_latency; 137911051Sandreas.hansson@arm.com } 138011051Sandreas.hansson@arm.com 138111375Sandreas.hansson@arm.com bool wasFull = mshrQueue.isFull(); 138211375Sandreas.hansson@arm.com 138311375Sandreas.hansson@arm.com PacketList writebacks; 138411375Sandreas.hansson@arm.com 138511375Sandreas.hansson@arm.com Tick forward_time = clockEdge(forwardLatency) + pkt->headerDelay; 138611375Sandreas.hansson@arm.com 138712348Snikos.nikoleris@arm.com bool is_fill = !mshr->isForward && 138812348Snikos.nikoleris@arm.com (pkt->isRead() || pkt->cmd == MemCmd::UpgradeResp); 138912348Snikos.nikoleris@arm.com 139012348Snikos.nikoleris@arm.com CacheBlk *blk = tags->findBlock(pkt->getAddr(), pkt->isSecure()); 139112348Snikos.nikoleris@arm.com const bool valid_blk = blk && blk->isValid(); 139212348Snikos.nikoleris@arm.com // If the response indicates that there are no sharers and we 139312348Snikos.nikoleris@arm.com // either had the block already or the response is filling we can 139412348Snikos.nikoleris@arm.com // promote our copy to writable 139512349Snikos.nikoleris@arm.com if (!pkt->hasSharers() && 139612349Snikos.nikoleris@arm.com (is_fill || (valid_blk && !pkt->req->isCacheInvalidate()))) { 139711284Sandreas.hansson@arm.com mshr->promoteWritable(); 139811177Sandreas.hansson@arm.com } 139911177Sandreas.hansson@arm.com 140011051Sandreas.hansson@arm.com if (is_fill && !is_error) { 140111051Sandreas.hansson@arm.com DPRINTF(Cache, "Block for addr %#llx being updated in Cache\n", 140211051Sandreas.hansson@arm.com pkt->getAddr()); 140311051Sandreas.hansson@arm.com 140411741Snikos.nikoleris@arm.com blk = handleFill(pkt, blk, writebacks, mshr->allocOnFill()); 140511484Snikos.nikoleris@arm.com assert(blk != nullptr); 140611051Sandreas.hansson@arm.com } 140711051Sandreas.hansson@arm.com 140811051Sandreas.hansson@arm.com // allow invalidation responses originating from write-line 140911051Sandreas.hansson@arm.com // requests to be discarded 141011136Sandreas.hansson@arm.com bool is_invalidate = pkt->isInvalidate(); 141111051Sandreas.hansson@arm.com 141212349Snikos.nikoleris@arm.com // The block was marked as not readable while there was a pending 141312349Snikos.nikoleris@arm.com // cache maintenance operation, restore its flag. 141412349Snikos.nikoleris@arm.com if (pkt->isClean() && !is_invalidate && valid_blk) { 141512349Snikos.nikoleris@arm.com blk->status |= BlkReadable; 141612349Snikos.nikoleris@arm.com } 141712349Snikos.nikoleris@arm.com 141811051Sandreas.hansson@arm.com // First offset for critical word first calculations 141911051Sandreas.hansson@arm.com int initial_offset = initial_tgt->pkt->getOffset(blkSize); 142011051Sandreas.hansson@arm.com 142111601Sandreas.hansson@arm.com bool from_cache = false; 142211742Snikos.nikoleris@arm.com MSHR::TargetList targets = mshr->extractServiceableTargets(pkt); 142311742Snikos.nikoleris@arm.com for (auto &target: targets) { 142411742Snikos.nikoleris@arm.com Packet *tgt_pkt = target.pkt; 142511742Snikos.nikoleris@arm.com switch (target.source) { 142611051Sandreas.hansson@arm.com case MSHR::Target::FromCPU: 142711051Sandreas.hansson@arm.com Tick completion_time; 142811051Sandreas.hansson@arm.com // Here we charge on completion_time the delay of the xbar if the 142911051Sandreas.hansson@arm.com // packet comes from it, charged on headerDelay. 143011051Sandreas.hansson@arm.com completion_time = pkt->headerDelay; 143111051Sandreas.hansson@arm.com 143211051Sandreas.hansson@arm.com // Software prefetch handling for cache closest to core 143311051Sandreas.hansson@arm.com if (tgt_pkt->cmd.isSWPrefetch()) { 143411483Snikos.nikoleris@arm.com // a software prefetch would have already been ack'd 143511483Snikos.nikoleris@arm.com // immediately with dummy data so the core would be able to 143611483Snikos.nikoleris@arm.com // retire it. This request completes right here, so we 143711483Snikos.nikoleris@arm.com // deallocate it. 143811051Sandreas.hansson@arm.com delete tgt_pkt->req; 143911051Sandreas.hansson@arm.com delete tgt_pkt; 144011051Sandreas.hansson@arm.com break; // skip response 144111051Sandreas.hansson@arm.com } 144211051Sandreas.hansson@arm.com 144311601Sandreas.hansson@arm.com // keep track of whether we have responded to another 144411601Sandreas.hansson@arm.com // cache 144511601Sandreas.hansson@arm.com from_cache = from_cache || tgt_pkt->fromCache(); 144611601Sandreas.hansson@arm.com 144711051Sandreas.hansson@arm.com // unlike the other packet flows, where data is found in other 144811051Sandreas.hansson@arm.com // caches or memory and brought back, write-line requests always 144911051Sandreas.hansson@arm.com // have the data right away, so the above check for "is fill?" 145011051Sandreas.hansson@arm.com // cannot actually be determined until examining the stored MSHR 145111051Sandreas.hansson@arm.com // state. We "catch up" with that logic here, which is duplicated 145211051Sandreas.hansson@arm.com // from above. 145311051Sandreas.hansson@arm.com if (tgt_pkt->cmd == MemCmd::WriteLineReq) { 145411051Sandreas.hansson@arm.com assert(!is_error); 145511284Sandreas.hansson@arm.com // we got the block in a writable state, so promote 145611284Sandreas.hansson@arm.com // any deferred targets if possible 145711284Sandreas.hansson@arm.com mshr->promoteWritable(); 145811051Sandreas.hansson@arm.com // NB: we use the original packet here and not the response! 145911741Snikos.nikoleris@arm.com blk = handleFill(tgt_pkt, blk, writebacks, 146011742Snikos.nikoleris@arm.com targets.allocOnFill); 146111484Snikos.nikoleris@arm.com assert(blk != nullptr); 146211051Sandreas.hansson@arm.com 146311051Sandreas.hansson@arm.com // treat as a fill, and discard the invalidation 146411051Sandreas.hansson@arm.com // response 146511051Sandreas.hansson@arm.com is_fill = true; 146611136Sandreas.hansson@arm.com is_invalidate = false; 146711051Sandreas.hansson@arm.com } 146811051Sandreas.hansson@arm.com 146911051Sandreas.hansson@arm.com if (is_fill) { 147011601Sandreas.hansson@arm.com satisfyRequest(tgt_pkt, blk, true, mshr->hasPostDowngrade()); 147111051Sandreas.hansson@arm.com 147211051Sandreas.hansson@arm.com // How many bytes past the first request is this one 147311051Sandreas.hansson@arm.com int transfer_offset = 147411051Sandreas.hansson@arm.com tgt_pkt->getOffset(blkSize) - initial_offset; 147511051Sandreas.hansson@arm.com if (transfer_offset < 0) { 147611051Sandreas.hansson@arm.com transfer_offset += blkSize; 147711051Sandreas.hansson@arm.com } 147811051Sandreas.hansson@arm.com 147911051Sandreas.hansson@arm.com // If not critical word (offset) return payloadDelay. 148011051Sandreas.hansson@arm.com // responseLatency is the latency of the return path 148111051Sandreas.hansson@arm.com // from lower level caches/memory to an upper level cache or 148211051Sandreas.hansson@arm.com // the core. 148311051Sandreas.hansson@arm.com completion_time += clockEdge(responseLatency) + 148411051Sandreas.hansson@arm.com (transfer_offset ? pkt->payloadDelay : 0); 148511051Sandreas.hansson@arm.com 148611051Sandreas.hansson@arm.com assert(!tgt_pkt->req->isUncacheable()); 148711051Sandreas.hansson@arm.com 148811051Sandreas.hansson@arm.com assert(tgt_pkt->req->masterId() < system->maxMasters()); 148911051Sandreas.hansson@arm.com missLatency[tgt_pkt->cmdToIndex()][tgt_pkt->req->masterId()] += 149011742Snikos.nikoleris@arm.com completion_time - target.recvTime; 149111051Sandreas.hansson@arm.com } else if (pkt->cmd == MemCmd::UpgradeFailResp) { 149211051Sandreas.hansson@arm.com // failed StoreCond upgrade 149311051Sandreas.hansson@arm.com assert(tgt_pkt->cmd == MemCmd::StoreCondReq || 149411051Sandreas.hansson@arm.com tgt_pkt->cmd == MemCmd::StoreCondFailReq || 149511051Sandreas.hansson@arm.com tgt_pkt->cmd == MemCmd::SCUpgradeFailReq); 149611051Sandreas.hansson@arm.com // responseLatency is the latency of the return path 149711051Sandreas.hansson@arm.com // from lower level caches/memory to an upper level cache or 149811051Sandreas.hansson@arm.com // the core. 149911051Sandreas.hansson@arm.com completion_time += clockEdge(responseLatency) + 150011051Sandreas.hansson@arm.com pkt->payloadDelay; 150111051Sandreas.hansson@arm.com tgt_pkt->req->setExtraData(0); 150211051Sandreas.hansson@arm.com } else { 150311750Snikos.nikoleris@arm.com // We are about to send a response to a cache above 150411750Snikos.nikoleris@arm.com // that asked for an invalidation; we need to 150511750Snikos.nikoleris@arm.com // invalidate our copy immediately as the most 150611750Snikos.nikoleris@arm.com // up-to-date copy of the block will now be in the 150711750Snikos.nikoleris@arm.com // cache above. It will also prevent this cache from 150811750Snikos.nikoleris@arm.com // responding (if the block was previously dirty) to 150911750Snikos.nikoleris@arm.com // snoops as they should snoop the caches above where 151011750Snikos.nikoleris@arm.com // they will get the response from. 151111750Snikos.nikoleris@arm.com if (is_invalidate && blk && blk->isValid()) { 151211750Snikos.nikoleris@arm.com invalidateBlock(blk); 151311750Snikos.nikoleris@arm.com } 151411051Sandreas.hansson@arm.com // not a cache fill, just forwarding response 151511051Sandreas.hansson@arm.com // responseLatency is the latency of the return path 151611051Sandreas.hansson@arm.com // from lower level cahces/memory to the core. 151711051Sandreas.hansson@arm.com completion_time += clockEdge(responseLatency) + 151811051Sandreas.hansson@arm.com pkt->payloadDelay; 151911051Sandreas.hansson@arm.com if (pkt->isRead() && !is_error) { 152011051Sandreas.hansson@arm.com // sanity check 152111051Sandreas.hansson@arm.com assert(pkt->getAddr() == tgt_pkt->getAddr()); 152211051Sandreas.hansson@arm.com assert(pkt->getSize() >= tgt_pkt->getSize()); 152311051Sandreas.hansson@arm.com 152411051Sandreas.hansson@arm.com tgt_pkt->setData(pkt->getConstPtr<uint8_t>()); 152511051Sandreas.hansson@arm.com } 152611051Sandreas.hansson@arm.com } 152711051Sandreas.hansson@arm.com tgt_pkt->makeTimingResponse(); 152811051Sandreas.hansson@arm.com // if this packet is an error copy that to the new packet 152911051Sandreas.hansson@arm.com if (is_error) 153011051Sandreas.hansson@arm.com tgt_pkt->copyError(pkt); 153111051Sandreas.hansson@arm.com if (tgt_pkt->cmd == MemCmd::ReadResp && 153211136Sandreas.hansson@arm.com (is_invalidate || mshr->hasPostInvalidate())) { 153311051Sandreas.hansson@arm.com // If intermediate cache got ReadRespWithInvalidate, 153411051Sandreas.hansson@arm.com // propagate that. Response should not have 153511051Sandreas.hansson@arm.com // isInvalidate() set otherwise. 153611051Sandreas.hansson@arm.com tgt_pkt->cmd = MemCmd::ReadRespWithInvalidate; 153711744Snikos.nikoleris@arm.com DPRINTF(Cache, "%s: updated cmd to %s\n", __func__, 153811744Snikos.nikoleris@arm.com tgt_pkt->print()); 153911051Sandreas.hansson@arm.com } 154011051Sandreas.hansson@arm.com // Reset the bus additional time as it is now accounted for 154111051Sandreas.hansson@arm.com tgt_pkt->headerDelay = tgt_pkt->payloadDelay = 0; 154211194Sali.jafri@arm.com cpuSidePort->schedTimingResp(tgt_pkt, completion_time, true); 154311051Sandreas.hansson@arm.com break; 154411051Sandreas.hansson@arm.com 154511051Sandreas.hansson@arm.com case MSHR::Target::FromPrefetcher: 154611051Sandreas.hansson@arm.com assert(tgt_pkt->cmd == MemCmd::HardPFReq); 154711051Sandreas.hansson@arm.com if (blk) 154811051Sandreas.hansson@arm.com blk->status |= BlkHWPrefetched; 154911051Sandreas.hansson@arm.com delete tgt_pkt->req; 155011051Sandreas.hansson@arm.com delete tgt_pkt; 155111051Sandreas.hansson@arm.com break; 155211051Sandreas.hansson@arm.com 155311051Sandreas.hansson@arm.com case MSHR::Target::FromSnoop: 155411051Sandreas.hansson@arm.com // I don't believe that a snoop can be in an error state 155511051Sandreas.hansson@arm.com assert(!is_error); 155611051Sandreas.hansson@arm.com // response to snoop request 155711051Sandreas.hansson@arm.com DPRINTF(Cache, "processing deferred snoop...\n"); 155811749Snikos.nikoleris@arm.com // If the response is invalidating, a snooping target can 155911749Snikos.nikoleris@arm.com // be satisfied if it is also invalidating. If the reponse is, not 156012349Snikos.nikoleris@arm.com // only invalidating, but more specifically an InvalidateResp and 156112349Snikos.nikoleris@arm.com // the MSHR was created due to an InvalidateReq then a cache above 156212349Snikos.nikoleris@arm.com // is waiting to satisfy a WriteLineReq. In this case even an 156311749Snikos.nikoleris@arm.com // non-invalidating snoop is added as a target here since this is 156411749Snikos.nikoleris@arm.com // the ordering point. When the InvalidateResp reaches this cache, 156511749Snikos.nikoleris@arm.com // the snooping target will snoop further the cache above with the 156611749Snikos.nikoleris@arm.com // WriteLineReq. 156712349Snikos.nikoleris@arm.com assert(!is_invalidate || pkt->cmd == MemCmd::InvalidateResp || 156812349Snikos.nikoleris@arm.com pkt->req->isCacheMaintenance() || 156912349Snikos.nikoleris@arm.com mshr->hasPostInvalidate()); 157011051Sandreas.hansson@arm.com handleSnoop(tgt_pkt, blk, true, true, mshr->hasPostInvalidate()); 157111051Sandreas.hansson@arm.com break; 157211051Sandreas.hansson@arm.com 157311051Sandreas.hansson@arm.com default: 157411742Snikos.nikoleris@arm.com panic("Illegal target->source enum %d\n", target.source); 157511051Sandreas.hansson@arm.com } 157611051Sandreas.hansson@arm.com } 157711051Sandreas.hansson@arm.com 157811601Sandreas.hansson@arm.com maintainClusivity(from_cache, blk); 157911601Sandreas.hansson@arm.com 158011051Sandreas.hansson@arm.com if (blk && blk->isValid()) { 158111051Sandreas.hansson@arm.com // an invalidate response stemming from a write line request 158211051Sandreas.hansson@arm.com // should not invalidate the block, so check if the 158311051Sandreas.hansson@arm.com // invalidation should be discarded 158411136Sandreas.hansson@arm.com if (is_invalidate || mshr->hasPostInvalidate()) { 158511197Sandreas.hansson@arm.com invalidateBlock(blk); 158611051Sandreas.hansson@arm.com } else if (mshr->hasPostDowngrade()) { 158711051Sandreas.hansson@arm.com blk->status &= ~BlkWritable; 158811051Sandreas.hansson@arm.com } 158911051Sandreas.hansson@arm.com } 159011051Sandreas.hansson@arm.com 159111051Sandreas.hansson@arm.com if (mshr->promoteDeferredTargets()) { 159211051Sandreas.hansson@arm.com // avoid later read getting stale data while write miss is 159311051Sandreas.hansson@arm.com // outstanding.. see comment in timingAccess() 159411051Sandreas.hansson@arm.com if (blk) { 159511051Sandreas.hansson@arm.com blk->status &= ~BlkReadable; 159611051Sandreas.hansson@arm.com } 159711375Sandreas.hansson@arm.com mshrQueue.markPending(mshr); 159811051Sandreas.hansson@arm.com schedMemSideSendEvent(clockEdge() + pkt->payloadDelay); 159911051Sandreas.hansson@arm.com } else { 160011375Sandreas.hansson@arm.com mshrQueue.deallocate(mshr); 160111375Sandreas.hansson@arm.com if (wasFull && !mshrQueue.isFull()) { 160211375Sandreas.hansson@arm.com clearBlocked(Blocked_NoMSHRs); 160311051Sandreas.hansson@arm.com } 160411051Sandreas.hansson@arm.com 160511051Sandreas.hansson@arm.com // Request the bus for a prefetch if this deallocation freed enough 160611051Sandreas.hansson@arm.com // MSHRs for a prefetch to take place 160711375Sandreas.hansson@arm.com if (prefetcher && mshrQueue.canPrefetch()) { 160811051Sandreas.hansson@arm.com Tick next_pf_time = std::max(prefetcher->nextPrefetchReadyTime(), 160911051Sandreas.hansson@arm.com clockEdge()); 161011051Sandreas.hansson@arm.com if (next_pf_time != MaxTick) 161111051Sandreas.hansson@arm.com schedMemSideSendEvent(next_pf_time); 161211051Sandreas.hansson@arm.com } 161311051Sandreas.hansson@arm.com } 161411051Sandreas.hansson@arm.com // reset the xbar additional timinig as it is now accounted for 161511051Sandreas.hansson@arm.com pkt->headerDelay = pkt->payloadDelay = 0; 161611051Sandreas.hansson@arm.com 161711051Sandreas.hansson@arm.com // copy writebacks to write buffer 161811051Sandreas.hansson@arm.com doWritebacks(writebacks, forward_time); 161911051Sandreas.hansson@arm.com 162011051Sandreas.hansson@arm.com // if we used temp block, check to see if its valid and then clear it out 162111051Sandreas.hansson@arm.com if (blk == tempBlock && tempBlock->isValid()) { 162211051Sandreas.hansson@arm.com // We use forwardLatency here because we are copying 162311051Sandreas.hansson@arm.com // Writebacks/CleanEvicts to write buffer. It specifies the latency to 162411051Sandreas.hansson@arm.com // allocate an internal buffer and to schedule an event to the 162511051Sandreas.hansson@arm.com // queued port. 162611199Sandreas.hansson@arm.com if (blk->isDirty() || writebackClean) { 162711051Sandreas.hansson@arm.com PacketPtr wbPkt = writebackBlk(blk); 162811051Sandreas.hansson@arm.com allocateWriteBuffer(wbPkt, forward_time); 162911051Sandreas.hansson@arm.com // Set BLOCK_CACHED flag if cached above. 163011051Sandreas.hansson@arm.com if (isCachedAbove(wbPkt)) 163111051Sandreas.hansson@arm.com wbPkt->setBlockCached(); 163211051Sandreas.hansson@arm.com } else { 163311051Sandreas.hansson@arm.com PacketPtr wcPkt = cleanEvictBlk(blk); 163411051Sandreas.hansson@arm.com // Check to see if block is cached above. If not allocate 163511051Sandreas.hansson@arm.com // write buffer 163611051Sandreas.hansson@arm.com if (isCachedAbove(wcPkt)) 163711051Sandreas.hansson@arm.com delete wcPkt; 163811051Sandreas.hansson@arm.com else 163911051Sandreas.hansson@arm.com allocateWriteBuffer(wcPkt, forward_time); 164011051Sandreas.hansson@arm.com } 164111867Snikos.nikoleris@arm.com invalidateBlock(blk); 164211051Sandreas.hansson@arm.com } 164311051Sandreas.hansson@arm.com 164411744Snikos.nikoleris@arm.com DPRINTF(CacheVerbose, "%s: Leaving with %s\n", __func__, pkt->print()); 164511051Sandreas.hansson@arm.com delete pkt; 164611051Sandreas.hansson@arm.com} 164711051Sandreas.hansson@arm.com 164811051Sandreas.hansson@arm.comPacketPtr 164911051Sandreas.hansson@arm.comCache::writebackBlk(CacheBlk *blk) 165011051Sandreas.hansson@arm.com{ 165111199Sandreas.hansson@arm.com chatty_assert(!isReadOnly || writebackClean, 165211199Sandreas.hansson@arm.com "Writeback from read-only cache"); 165311199Sandreas.hansson@arm.com assert(blk && blk->isValid() && (blk->isDirty() || writebackClean)); 165411051Sandreas.hansson@arm.com 165511051Sandreas.hansson@arm.com writebacks[Request::wbMasterId]++; 165611051Sandreas.hansson@arm.com 165711199Sandreas.hansson@arm.com Request *req = new Request(tags->regenerateBlkAddr(blk->tag, blk->set), 165811199Sandreas.hansson@arm.com blkSize, 0, Request::wbMasterId); 165911051Sandreas.hansson@arm.com if (blk->isSecure()) 166011199Sandreas.hansson@arm.com req->setFlags(Request::SECURE); 166111051Sandreas.hansson@arm.com 166211199Sandreas.hansson@arm.com req->taskId(blk->task_id); 166311051Sandreas.hansson@arm.com blk->task_id= ContextSwitchTaskId::Unknown; 166411051Sandreas.hansson@arm.com blk->tickInserted = curTick(); 166511051Sandreas.hansson@arm.com 166611199Sandreas.hansson@arm.com PacketPtr pkt = 166711199Sandreas.hansson@arm.com new Packet(req, blk->isDirty() ? 166811199Sandreas.hansson@arm.com MemCmd::WritebackDirty : MemCmd::WritebackClean); 166911199Sandreas.hansson@arm.com 167011744Snikos.nikoleris@arm.com DPRINTF(Cache, "Create Writeback %s writable: %d, dirty: %d\n", 167111744Snikos.nikoleris@arm.com pkt->print(), blk->isWritable(), blk->isDirty()); 167211199Sandreas.hansson@arm.com 167311051Sandreas.hansson@arm.com if (blk->isWritable()) { 167411051Sandreas.hansson@arm.com // not asserting shared means we pass the block in modified 167511051Sandreas.hansson@arm.com // state, mark our own block non-writeable 167611051Sandreas.hansson@arm.com blk->status &= ~BlkWritable; 167711051Sandreas.hansson@arm.com } else { 167811284Sandreas.hansson@arm.com // we are in the Owned state, tell the receiver 167911284Sandreas.hansson@arm.com pkt->setHasSharers(); 168011051Sandreas.hansson@arm.com } 168111051Sandreas.hansson@arm.com 168211199Sandreas.hansson@arm.com // make sure the block is not marked dirty 168311199Sandreas.hansson@arm.com blk->status &= ~BlkDirty; 168411051Sandreas.hansson@arm.com 168511199Sandreas.hansson@arm.com pkt->allocate(); 168611199Sandreas.hansson@arm.com std::memcpy(pkt->getPtr<uint8_t>(), blk->data, blkSize); 168711199Sandreas.hansson@arm.com 168811199Sandreas.hansson@arm.com return pkt; 168911051Sandreas.hansson@arm.com} 169011051Sandreas.hansson@arm.com 169111051Sandreas.hansson@arm.comPacketPtr 169212351Snikos.nikoleris@arm.comCache::writecleanBlk(CacheBlk *blk, Request::Flags dest, PacketId id) 169312345Snikos.nikoleris@arm.com{ 169412345Snikos.nikoleris@arm.com Request *req = new Request(tags->regenerateBlkAddr(blk->tag, blk->set), 169512345Snikos.nikoleris@arm.com blkSize, 0, Request::wbMasterId); 169612345Snikos.nikoleris@arm.com if (blk->isSecure()) { 169712345Snikos.nikoleris@arm.com req->setFlags(Request::SECURE); 169812345Snikos.nikoleris@arm.com } 169912345Snikos.nikoleris@arm.com req->taskId(blk->task_id); 170012345Snikos.nikoleris@arm.com blk->task_id = ContextSwitchTaskId::Unknown; 170112351Snikos.nikoleris@arm.com PacketPtr pkt = new Packet(req, MemCmd::WriteClean, blkSize, id); 170212345Snikos.nikoleris@arm.com DPRINTF(Cache, "Create %s writable: %d, dirty: %d\n", pkt->print(), 170312345Snikos.nikoleris@arm.com blk->isWritable(), blk->isDirty()); 170412345Snikos.nikoleris@arm.com // make sure the block is not marked dirty 170512345Snikos.nikoleris@arm.com blk->status &= ~BlkDirty; 170612345Snikos.nikoleris@arm.com pkt->allocate(); 170712345Snikos.nikoleris@arm.com // We inform the cache below that the block has sharers in the 170812345Snikos.nikoleris@arm.com // system as we retain our copy. 170912345Snikos.nikoleris@arm.com pkt->setHasSharers(); 171012346Snikos.nikoleris@arm.com if (dest) { 171112346Snikos.nikoleris@arm.com req->setFlags(dest); 171212346Snikos.nikoleris@arm.com pkt->setWriteThrough(); 171312346Snikos.nikoleris@arm.com } 171412345Snikos.nikoleris@arm.com std::memcpy(pkt->getPtr<uint8_t>(), blk->data, blkSize); 171512345Snikos.nikoleris@arm.com return pkt; 171612345Snikos.nikoleris@arm.com} 171712345Snikos.nikoleris@arm.com 171812345Snikos.nikoleris@arm.com 171912345Snikos.nikoleris@arm.comPacketPtr 172011051Sandreas.hansson@arm.comCache::cleanEvictBlk(CacheBlk *blk) 172111051Sandreas.hansson@arm.com{ 172211199Sandreas.hansson@arm.com assert(!writebackClean); 172311051Sandreas.hansson@arm.com assert(blk && blk->isValid() && !blk->isDirty()); 172411051Sandreas.hansson@arm.com // Creating a zero sized write, a message to the snoop filter 172511051Sandreas.hansson@arm.com Request *req = 172611051Sandreas.hansson@arm.com new Request(tags->regenerateBlkAddr(blk->tag, blk->set), blkSize, 0, 172711051Sandreas.hansson@arm.com Request::wbMasterId); 172811051Sandreas.hansson@arm.com if (blk->isSecure()) 172911051Sandreas.hansson@arm.com req->setFlags(Request::SECURE); 173011051Sandreas.hansson@arm.com 173111051Sandreas.hansson@arm.com req->taskId(blk->task_id); 173211051Sandreas.hansson@arm.com blk->task_id = ContextSwitchTaskId::Unknown; 173311051Sandreas.hansson@arm.com blk->tickInserted = curTick(); 173411051Sandreas.hansson@arm.com 173511051Sandreas.hansson@arm.com PacketPtr pkt = new Packet(req, MemCmd::CleanEvict); 173611051Sandreas.hansson@arm.com pkt->allocate(); 173711744Snikos.nikoleris@arm.com DPRINTF(Cache, "Create CleanEvict %s\n", pkt->print()); 173811051Sandreas.hansson@arm.com 173911051Sandreas.hansson@arm.com return pkt; 174011051Sandreas.hansson@arm.com} 174111051Sandreas.hansson@arm.com 174211051Sandreas.hansson@arm.comvoid 174311051Sandreas.hansson@arm.comCache::memWriteback() 174411051Sandreas.hansson@arm.com{ 174511051Sandreas.hansson@arm.com CacheBlkVisitorWrapper visitor(*this, &Cache::writebackVisitor); 174611051Sandreas.hansson@arm.com tags->forEachBlk(visitor); 174711051Sandreas.hansson@arm.com} 174811051Sandreas.hansson@arm.com 174911051Sandreas.hansson@arm.comvoid 175011051Sandreas.hansson@arm.comCache::memInvalidate() 175111051Sandreas.hansson@arm.com{ 175211051Sandreas.hansson@arm.com CacheBlkVisitorWrapper visitor(*this, &Cache::invalidateVisitor); 175311051Sandreas.hansson@arm.com tags->forEachBlk(visitor); 175411051Sandreas.hansson@arm.com} 175511051Sandreas.hansson@arm.com 175611051Sandreas.hansson@arm.combool 175711051Sandreas.hansson@arm.comCache::isDirty() const 175811051Sandreas.hansson@arm.com{ 175911051Sandreas.hansson@arm.com CacheBlkIsDirtyVisitor visitor; 176011051Sandreas.hansson@arm.com tags->forEachBlk(visitor); 176111051Sandreas.hansson@arm.com 176211051Sandreas.hansson@arm.com return visitor.isDirty(); 176311051Sandreas.hansson@arm.com} 176411051Sandreas.hansson@arm.com 176511051Sandreas.hansson@arm.combool 176611051Sandreas.hansson@arm.comCache::writebackVisitor(CacheBlk &blk) 176711051Sandreas.hansson@arm.com{ 176811051Sandreas.hansson@arm.com if (blk.isDirty()) { 176911051Sandreas.hansson@arm.com assert(blk.isValid()); 177011051Sandreas.hansson@arm.com 177111051Sandreas.hansson@arm.com Request request(tags->regenerateBlkAddr(blk.tag, blk.set), 177211051Sandreas.hansson@arm.com blkSize, 0, Request::funcMasterId); 177311051Sandreas.hansson@arm.com request.taskId(blk.task_id); 177411865Snikos.nikoleris@arm.com if (blk.isSecure()) { 177511865Snikos.nikoleris@arm.com request.setFlags(Request::SECURE); 177611865Snikos.nikoleris@arm.com } 177711051Sandreas.hansson@arm.com 177811051Sandreas.hansson@arm.com Packet packet(&request, MemCmd::WriteReq); 177911051Sandreas.hansson@arm.com packet.dataStatic(blk.data); 178011051Sandreas.hansson@arm.com 178111051Sandreas.hansson@arm.com memSidePort->sendFunctional(&packet); 178211051Sandreas.hansson@arm.com 178311051Sandreas.hansson@arm.com blk.status &= ~BlkDirty; 178411051Sandreas.hansson@arm.com } 178511051Sandreas.hansson@arm.com 178611051Sandreas.hansson@arm.com return true; 178711051Sandreas.hansson@arm.com} 178811051Sandreas.hansson@arm.com 178911051Sandreas.hansson@arm.combool 179011051Sandreas.hansson@arm.comCache::invalidateVisitor(CacheBlk &blk) 179111051Sandreas.hansson@arm.com{ 179211051Sandreas.hansson@arm.com 179311051Sandreas.hansson@arm.com if (blk.isDirty()) 179411051Sandreas.hansson@arm.com warn_once("Invalidating dirty cache lines. Expect things to break.\n"); 179511051Sandreas.hansson@arm.com 179611051Sandreas.hansson@arm.com if (blk.isValid()) { 179711051Sandreas.hansson@arm.com assert(!blk.isDirty()); 179811867Snikos.nikoleris@arm.com invalidateBlock(&blk); 179911051Sandreas.hansson@arm.com } 180011051Sandreas.hansson@arm.com 180111051Sandreas.hansson@arm.com return true; 180211051Sandreas.hansson@arm.com} 180311051Sandreas.hansson@arm.com 180411051Sandreas.hansson@arm.comCacheBlk* 180511051Sandreas.hansson@arm.comCache::allocateBlock(Addr addr, bool is_secure, PacketList &writebacks) 180611051Sandreas.hansson@arm.com{ 180711051Sandreas.hansson@arm.com CacheBlk *blk = tags->findVictim(addr); 180811051Sandreas.hansson@arm.com 180911484Snikos.nikoleris@arm.com // It is valid to return nullptr if there is no victim 181011051Sandreas.hansson@arm.com if (!blk) 181111051Sandreas.hansson@arm.com return nullptr; 181211051Sandreas.hansson@arm.com 181311051Sandreas.hansson@arm.com if (blk->isValid()) { 181411051Sandreas.hansson@arm.com Addr repl_addr = tags->regenerateBlkAddr(blk->tag, blk->set); 181511051Sandreas.hansson@arm.com MSHR *repl_mshr = mshrQueue.findMatch(repl_addr, blk->isSecure()); 181611051Sandreas.hansson@arm.com if (repl_mshr) { 181711051Sandreas.hansson@arm.com // must be an outstanding upgrade request 181811051Sandreas.hansson@arm.com // on a block we're about to replace... 181911051Sandreas.hansson@arm.com assert(!blk->isWritable() || blk->isDirty()); 182011284Sandreas.hansson@arm.com assert(repl_mshr->needsWritable()); 182111051Sandreas.hansson@arm.com // too hard to replace block with transient state 182211051Sandreas.hansson@arm.com // allocation failed, block not inserted 182311484Snikos.nikoleris@arm.com return nullptr; 182411051Sandreas.hansson@arm.com } else { 182511483Snikos.nikoleris@arm.com DPRINTF(Cache, "replacement: replacing %#llx (%s) with %#llx " 182611483Snikos.nikoleris@arm.com "(%s): %s\n", repl_addr, blk->isSecure() ? "s" : "ns", 182711051Sandreas.hansson@arm.com addr, is_secure ? "s" : "ns", 182811051Sandreas.hansson@arm.com blk->isDirty() ? "writeback" : "clean"); 182911051Sandreas.hansson@arm.com 183011436SRekai.GonzalezAlberquilla@arm.com if (blk->wasPrefetched()) { 183111436SRekai.GonzalezAlberquilla@arm.com unusedPrefetches++; 183211436SRekai.GonzalezAlberquilla@arm.com } 183311051Sandreas.hansson@arm.com // Will send up Writeback/CleanEvict snoops via isCachedAbove 183411051Sandreas.hansson@arm.com // when pushing this writeback list into the write buffer. 183511199Sandreas.hansson@arm.com if (blk->isDirty() || writebackClean) { 183611051Sandreas.hansson@arm.com // Save writeback packet for handling by caller 183711051Sandreas.hansson@arm.com writebacks.push_back(writebackBlk(blk)); 183811051Sandreas.hansson@arm.com } else { 183911051Sandreas.hansson@arm.com writebacks.push_back(cleanEvictBlk(blk)); 184011051Sandreas.hansson@arm.com } 184111051Sandreas.hansson@arm.com } 184211051Sandreas.hansson@arm.com } 184311051Sandreas.hansson@arm.com 184411051Sandreas.hansson@arm.com return blk; 184511051Sandreas.hansson@arm.com} 184611051Sandreas.hansson@arm.com 184711197Sandreas.hansson@arm.comvoid 184811197Sandreas.hansson@arm.comCache::invalidateBlock(CacheBlk *blk) 184911197Sandreas.hansson@arm.com{ 185011197Sandreas.hansson@arm.com if (blk != tempBlock) 185111197Sandreas.hansson@arm.com tags->invalidate(blk); 185211197Sandreas.hansson@arm.com blk->invalidate(); 185311197Sandreas.hansson@arm.com} 185411051Sandreas.hansson@arm.com 185511051Sandreas.hansson@arm.com// Note that the reason we return a list of writebacks rather than 185611051Sandreas.hansson@arm.com// inserting them directly in the write buffer is that this function 185711051Sandreas.hansson@arm.com// is called by both atomic and timing-mode accesses, and in atomic 185811051Sandreas.hansson@arm.com// mode we don't mess with the write buffer (we just perform the 185911051Sandreas.hansson@arm.com// writebacks atomically once the original request is complete). 186011051Sandreas.hansson@arm.comCacheBlk* 186111197Sandreas.hansson@arm.comCache::handleFill(PacketPtr pkt, CacheBlk *blk, PacketList &writebacks, 186211197Sandreas.hansson@arm.com bool allocate) 186311051Sandreas.hansson@arm.com{ 186411051Sandreas.hansson@arm.com assert(pkt->isResponse() || pkt->cmd == MemCmd::WriteLineReq); 186511051Sandreas.hansson@arm.com Addr addr = pkt->getAddr(); 186611051Sandreas.hansson@arm.com bool is_secure = pkt->isSecure(); 186711051Sandreas.hansson@arm.com#if TRACING_ON 186811051Sandreas.hansson@arm.com CacheBlk::State old_state = blk ? blk->status : 0; 186911051Sandreas.hansson@arm.com#endif 187011051Sandreas.hansson@arm.com 187111375Sandreas.hansson@arm.com // When handling a fill, we should have no writes to this line. 187211892Snikos.nikoleris@arm.com assert(addr == pkt->getBlockAddr(blkSize)); 187311375Sandreas.hansson@arm.com assert(!writeBuffer.findMatch(addr, is_secure)); 187411051Sandreas.hansson@arm.com 187511484Snikos.nikoleris@arm.com if (blk == nullptr) { 187611051Sandreas.hansson@arm.com // better have read new data... 187711051Sandreas.hansson@arm.com assert(pkt->hasData()); 187811051Sandreas.hansson@arm.com 187911051Sandreas.hansson@arm.com // only read responses and write-line requests have data; 188011051Sandreas.hansson@arm.com // note that we don't write the data here for write-line - that 188111601Sandreas.hansson@arm.com // happens in the subsequent call to satisfyRequest 188211051Sandreas.hansson@arm.com assert(pkt->isRead() || pkt->cmd == MemCmd::WriteLineReq); 188311051Sandreas.hansson@arm.com 188411197Sandreas.hansson@arm.com // need to do a replacement if allocating, otherwise we stick 188511197Sandreas.hansson@arm.com // with the temporary storage 188611484Snikos.nikoleris@arm.com blk = allocate ? allocateBlock(addr, is_secure, writebacks) : nullptr; 188711197Sandreas.hansson@arm.com 188811484Snikos.nikoleris@arm.com if (blk == nullptr) { 188911197Sandreas.hansson@arm.com // No replaceable block or a mostly exclusive 189011197Sandreas.hansson@arm.com // cache... just use temporary storage to complete the 189111197Sandreas.hansson@arm.com // current request and then get rid of it 189211051Sandreas.hansson@arm.com assert(!tempBlock->isValid()); 189311051Sandreas.hansson@arm.com blk = tempBlock; 189411051Sandreas.hansson@arm.com tempBlock->set = tags->extractSet(addr); 189511051Sandreas.hansson@arm.com tempBlock->tag = tags->extractTag(addr); 189611051Sandreas.hansson@arm.com // @todo: set security state as well... 189711051Sandreas.hansson@arm.com DPRINTF(Cache, "using temp block for %#llx (%s)\n", addr, 189811051Sandreas.hansson@arm.com is_secure ? "s" : "ns"); 189911051Sandreas.hansson@arm.com } else { 190011051Sandreas.hansson@arm.com tags->insertBlock(pkt, blk); 190111051Sandreas.hansson@arm.com } 190211051Sandreas.hansson@arm.com 190311051Sandreas.hansson@arm.com // we should never be overwriting a valid block 190411051Sandreas.hansson@arm.com assert(!blk->isValid()); 190511051Sandreas.hansson@arm.com } else { 190611051Sandreas.hansson@arm.com // existing block... probably an upgrade 190711051Sandreas.hansson@arm.com assert(blk->tag == tags->extractTag(addr)); 190811051Sandreas.hansson@arm.com // either we're getting new data or the block should already be valid 190911051Sandreas.hansson@arm.com assert(pkt->hasData() || blk->isValid()); 191011051Sandreas.hansson@arm.com // don't clear block status... if block is already dirty we 191111051Sandreas.hansson@arm.com // don't want to lose that 191211051Sandreas.hansson@arm.com } 191311051Sandreas.hansson@arm.com 191411051Sandreas.hansson@arm.com if (is_secure) 191511051Sandreas.hansson@arm.com blk->status |= BlkSecure; 191611051Sandreas.hansson@arm.com blk->status |= BlkValid | BlkReadable; 191711051Sandreas.hansson@arm.com 191811137Sandreas.hansson@arm.com // sanity check for whole-line writes, which should always be 191911137Sandreas.hansson@arm.com // marked as writable as part of the fill, and then later marked 192011601Sandreas.hansson@arm.com // dirty as part of satisfyRequest 192111137Sandreas.hansson@arm.com if (pkt->cmd == MemCmd::WriteLineReq) { 192211284Sandreas.hansson@arm.com assert(!pkt->hasSharers()); 192311137Sandreas.hansson@arm.com } 192411137Sandreas.hansson@arm.com 192511284Sandreas.hansson@arm.com // here we deal with setting the appropriate state of the line, 192611284Sandreas.hansson@arm.com // and we start by looking at the hasSharers flag, and ignore the 192711284Sandreas.hansson@arm.com // cacheResponding flag (normally signalling dirty data) if the 192811284Sandreas.hansson@arm.com // packet has sharers, thus the line is never allocated as Owned 192911284Sandreas.hansson@arm.com // (dirty but not writable), and always ends up being either 193011284Sandreas.hansson@arm.com // Shared, Exclusive or Modified, see Packet::setCacheResponding 193111284Sandreas.hansson@arm.com // for more details 193211284Sandreas.hansson@arm.com if (!pkt->hasSharers()) { 193311284Sandreas.hansson@arm.com // we could get a writable line from memory (rather than a 193411284Sandreas.hansson@arm.com // cache) even in a read-only cache, note that we set this bit 193511284Sandreas.hansson@arm.com // even for a read-only cache, possibly revisit this decision 193611051Sandreas.hansson@arm.com blk->status |= BlkWritable; 193711051Sandreas.hansson@arm.com 193811284Sandreas.hansson@arm.com // check if we got this via cache-to-cache transfer (i.e., from a 193911284Sandreas.hansson@arm.com // cache that had the block in Modified or Owned state) 194011284Sandreas.hansson@arm.com if (pkt->cacheResponding()) { 194111284Sandreas.hansson@arm.com // we got the block in Modified state, and invalidated the 194211284Sandreas.hansson@arm.com // owners copy 194311051Sandreas.hansson@arm.com blk->status |= BlkDirty; 194411051Sandreas.hansson@arm.com 194511051Sandreas.hansson@arm.com chatty_assert(!isReadOnly, "Should never see dirty snoop response " 194611051Sandreas.hansson@arm.com "in read-only cache %s\n", name()); 194711051Sandreas.hansson@arm.com } 194811051Sandreas.hansson@arm.com } 194911051Sandreas.hansson@arm.com 195011051Sandreas.hansson@arm.com DPRINTF(Cache, "Block addr %#llx (%s) moving from state %x to %s\n", 195111051Sandreas.hansson@arm.com addr, is_secure ? "s" : "ns", old_state, blk->print()); 195211051Sandreas.hansson@arm.com 195311051Sandreas.hansson@arm.com // if we got new data, copy it in (checking for a read response 195411051Sandreas.hansson@arm.com // and a response that has data is the same in the end) 195511051Sandreas.hansson@arm.com if (pkt->isRead()) { 195611051Sandreas.hansson@arm.com // sanity checks 195711051Sandreas.hansson@arm.com assert(pkt->hasData()); 195811051Sandreas.hansson@arm.com assert(pkt->getSize() == blkSize); 195911051Sandreas.hansson@arm.com 196011051Sandreas.hansson@arm.com std::memcpy(blk->data, pkt->getConstPtr<uint8_t>(), blkSize); 196111051Sandreas.hansson@arm.com } 196211051Sandreas.hansson@arm.com // We pay for fillLatency here. 196311051Sandreas.hansson@arm.com blk->whenReady = clockEdge() + fillLatency * clockPeriod() + 196411051Sandreas.hansson@arm.com pkt->payloadDelay; 196511051Sandreas.hansson@arm.com 196611051Sandreas.hansson@arm.com return blk; 196711051Sandreas.hansson@arm.com} 196811051Sandreas.hansson@arm.com 196911051Sandreas.hansson@arm.com 197011051Sandreas.hansson@arm.com///////////////////////////////////////////////////// 197111051Sandreas.hansson@arm.com// 197211051Sandreas.hansson@arm.com// Snoop path: requests coming in from the memory side 197311051Sandreas.hansson@arm.com// 197411051Sandreas.hansson@arm.com///////////////////////////////////////////////////// 197511051Sandreas.hansson@arm.com 197611051Sandreas.hansson@arm.comvoid 197711051Sandreas.hansson@arm.comCache::doTimingSupplyResponse(PacketPtr req_pkt, const uint8_t *blk_data, 197811051Sandreas.hansson@arm.com bool already_copied, bool pending_inval) 197911051Sandreas.hansson@arm.com{ 198011051Sandreas.hansson@arm.com // sanity check 198111051Sandreas.hansson@arm.com assert(req_pkt->isRequest()); 198211051Sandreas.hansson@arm.com assert(req_pkt->needsResponse()); 198311051Sandreas.hansson@arm.com 198411744Snikos.nikoleris@arm.com DPRINTF(Cache, "%s: for %s\n", __func__, req_pkt->print()); 198511051Sandreas.hansson@arm.com // timing-mode snoop responses require a new packet, unless we 198611051Sandreas.hansson@arm.com // already made a copy... 198711051Sandreas.hansson@arm.com PacketPtr pkt = req_pkt; 198811051Sandreas.hansson@arm.com if (!already_copied) 198911051Sandreas.hansson@arm.com // do not clear flags, and allocate space for data if the 199011051Sandreas.hansson@arm.com // packet needs it (the only packets that carry data are read 199111051Sandreas.hansson@arm.com // responses) 199211051Sandreas.hansson@arm.com pkt = new Packet(req_pkt, false, req_pkt->isRead()); 199311051Sandreas.hansson@arm.com 199411051Sandreas.hansson@arm.com assert(req_pkt->req->isUncacheable() || req_pkt->isInvalidate() || 199511284Sandreas.hansson@arm.com pkt->hasSharers()); 199611051Sandreas.hansson@arm.com pkt->makeTimingResponse(); 199711051Sandreas.hansson@arm.com if (pkt->isRead()) { 199811051Sandreas.hansson@arm.com pkt->setDataFromBlock(blk_data, blkSize); 199911051Sandreas.hansson@arm.com } 200011051Sandreas.hansson@arm.com if (pkt->cmd == MemCmd::ReadResp && pending_inval) { 200111051Sandreas.hansson@arm.com // Assume we defer a response to a read from a far-away cache 200211051Sandreas.hansson@arm.com // A, then later defer a ReadExcl from a cache B on the same 200311284Sandreas.hansson@arm.com // bus as us. We'll assert cacheResponding in both cases, but 200411284Sandreas.hansson@arm.com // in the latter case cacheResponding will keep the 200511284Sandreas.hansson@arm.com // invalidation from reaching cache A. This special response 200611284Sandreas.hansson@arm.com // tells cache A that it gets the block to satisfy its read, 200711284Sandreas.hansson@arm.com // but must immediately invalidate it. 200811051Sandreas.hansson@arm.com pkt->cmd = MemCmd::ReadRespWithInvalidate; 200911051Sandreas.hansson@arm.com } 201011051Sandreas.hansson@arm.com // Here we consider forward_time, paying for just forward latency and 201111051Sandreas.hansson@arm.com // also charging the delay provided by the xbar. 201211051Sandreas.hansson@arm.com // forward_time is used as send_time in next allocateWriteBuffer(). 201311051Sandreas.hansson@arm.com Tick forward_time = clockEdge(forwardLatency) + pkt->headerDelay; 201411051Sandreas.hansson@arm.com // Here we reset the timing of the packet. 201511051Sandreas.hansson@arm.com pkt->headerDelay = pkt->payloadDelay = 0; 201611744Snikos.nikoleris@arm.com DPRINTF(CacheVerbose, "%s: created response: %s tick: %lu\n", __func__, 201711744Snikos.nikoleris@arm.com pkt->print(), forward_time); 201811051Sandreas.hansson@arm.com memSidePort->schedTimingSnoopResp(pkt, forward_time, true); 201911051Sandreas.hansson@arm.com} 202011051Sandreas.hansson@arm.com 202111127Sandreas.hansson@arm.comuint32_t 202211051Sandreas.hansson@arm.comCache::handleSnoop(PacketPtr pkt, CacheBlk *blk, bool is_timing, 202311051Sandreas.hansson@arm.com bool is_deferred, bool pending_inval) 202411051Sandreas.hansson@arm.com{ 202511744Snikos.nikoleris@arm.com DPRINTF(CacheVerbose, "%s: for %s\n", __func__, pkt->print()); 202611051Sandreas.hansson@arm.com // deferred snoops can only happen in timing mode 202711051Sandreas.hansson@arm.com assert(!(is_deferred && !is_timing)); 202811051Sandreas.hansson@arm.com // pending_inval only makes sense on deferred snoops 202911051Sandreas.hansson@arm.com assert(!(pending_inval && !is_deferred)); 203011051Sandreas.hansson@arm.com assert(pkt->isRequest()); 203111051Sandreas.hansson@arm.com 203211051Sandreas.hansson@arm.com // the packet may get modified if we or a forwarded snooper 203311051Sandreas.hansson@arm.com // responds in atomic mode, so remember a few things about the 203411051Sandreas.hansson@arm.com // original packet up front 203511051Sandreas.hansson@arm.com bool invalidate = pkt->isInvalidate(); 203611284Sandreas.hansson@arm.com bool M5_VAR_USED needs_writable = pkt->needsWritable(); 203711051Sandreas.hansson@arm.com 203811285Sandreas.hansson@arm.com // at the moment we could get an uncacheable write which does not 203911285Sandreas.hansson@arm.com // have the invalidate flag, and we need a suitable way of dealing 204011285Sandreas.hansson@arm.com // with this case 204111285Sandreas.hansson@arm.com panic_if(invalidate && pkt->req->isUncacheable(), 204211744Snikos.nikoleris@arm.com "%s got an invalidating uncacheable snoop request %s", 204311744Snikos.nikoleris@arm.com name(), pkt->print()); 204411285Sandreas.hansson@arm.com 204511127Sandreas.hansson@arm.com uint32_t snoop_delay = 0; 204611127Sandreas.hansson@arm.com 204711051Sandreas.hansson@arm.com if (forwardSnoops) { 204811051Sandreas.hansson@arm.com // first propagate snoop upward to see if anyone above us wants to 204911051Sandreas.hansson@arm.com // handle it. save & restore packet src since it will get 205011051Sandreas.hansson@arm.com // rewritten to be relative to cpu-side bus (if any) 205111284Sandreas.hansson@arm.com bool alreadyResponded = pkt->cacheResponding(); 205211051Sandreas.hansson@arm.com if (is_timing) { 205311051Sandreas.hansson@arm.com // copy the packet so that we can clear any flags before 205411051Sandreas.hansson@arm.com // forwarding it upwards, we also allocate data (passing 205511051Sandreas.hansson@arm.com // the pointer along in case of static data), in case 205611051Sandreas.hansson@arm.com // there is a snoop hit in upper levels 205711051Sandreas.hansson@arm.com Packet snoopPkt(pkt, true, true); 205811051Sandreas.hansson@arm.com snoopPkt.setExpressSnoop(); 205911051Sandreas.hansson@arm.com // the snoop packet does not need to wait any additional 206011051Sandreas.hansson@arm.com // time 206111051Sandreas.hansson@arm.com snoopPkt.headerDelay = snoopPkt.payloadDelay = 0; 206211051Sandreas.hansson@arm.com cpuSidePort->sendTimingSnoopReq(&snoopPkt); 206311127Sandreas.hansson@arm.com 206411127Sandreas.hansson@arm.com // add the header delay (including crossbar and snoop 206511127Sandreas.hansson@arm.com // delays) of the upward snoop to the snoop delay for this 206611127Sandreas.hansson@arm.com // cache 206711127Sandreas.hansson@arm.com snoop_delay += snoopPkt.headerDelay; 206811127Sandreas.hansson@arm.com 206911284Sandreas.hansson@arm.com if (snoopPkt.cacheResponding()) { 207011051Sandreas.hansson@arm.com // cache-to-cache response from some upper cache 207111051Sandreas.hansson@arm.com assert(!alreadyResponded); 207211284Sandreas.hansson@arm.com pkt->setCacheResponding(); 207311051Sandreas.hansson@arm.com } 207411284Sandreas.hansson@arm.com // upstream cache has the block, or has an outstanding 207511284Sandreas.hansson@arm.com // MSHR, pass the flag on 207611284Sandreas.hansson@arm.com if (snoopPkt.hasSharers()) { 207711284Sandreas.hansson@arm.com pkt->setHasSharers(); 207811051Sandreas.hansson@arm.com } 207911051Sandreas.hansson@arm.com // If this request is a prefetch or clean evict and an upper level 208011051Sandreas.hansson@arm.com // signals block present, make sure to propagate the block 208111051Sandreas.hansson@arm.com // presence to the requester. 208211051Sandreas.hansson@arm.com if (snoopPkt.isBlockCached()) { 208311051Sandreas.hansson@arm.com pkt->setBlockCached(); 208411051Sandreas.hansson@arm.com } 208512349Snikos.nikoleris@arm.com // If the request was satisfied by snooping the cache 208612349Snikos.nikoleris@arm.com // above, mark the original packet as satisfied too. 208712349Snikos.nikoleris@arm.com if (snoopPkt.satisfied()) { 208812349Snikos.nikoleris@arm.com pkt->setSatisfied(); 208912349Snikos.nikoleris@arm.com } 209011051Sandreas.hansson@arm.com } else { 209111051Sandreas.hansson@arm.com cpuSidePort->sendAtomicSnoop(pkt); 209211284Sandreas.hansson@arm.com if (!alreadyResponded && pkt->cacheResponding()) { 209311051Sandreas.hansson@arm.com // cache-to-cache response from some upper cache: 209411051Sandreas.hansson@arm.com // forward response to original requester 209511051Sandreas.hansson@arm.com assert(pkt->isResponse()); 209611051Sandreas.hansson@arm.com } 209711051Sandreas.hansson@arm.com } 209811051Sandreas.hansson@arm.com } 209911051Sandreas.hansson@arm.com 210012349Snikos.nikoleris@arm.com bool respond = false; 210112349Snikos.nikoleris@arm.com bool blk_valid = blk && blk->isValid(); 210212349Snikos.nikoleris@arm.com if (pkt->isClean()) { 210312349Snikos.nikoleris@arm.com if (blk_valid && blk->isDirty()) { 210412349Snikos.nikoleris@arm.com DPRINTF(CacheVerbose, "%s: packet (snoop) %s found block: %s\n", 210512349Snikos.nikoleris@arm.com __func__, pkt->print(), blk->print()); 210612351Snikos.nikoleris@arm.com PacketPtr wb_pkt = writecleanBlk(blk, pkt->req->getDest(), pkt->id); 210712349Snikos.nikoleris@arm.com PacketList writebacks; 210812349Snikos.nikoleris@arm.com writebacks.push_back(wb_pkt); 210912349Snikos.nikoleris@arm.com 211012349Snikos.nikoleris@arm.com if (is_timing) { 211112349Snikos.nikoleris@arm.com // anything that is merely forwarded pays for the forward 211212349Snikos.nikoleris@arm.com // latency and the delay provided by the crossbar 211312349Snikos.nikoleris@arm.com Tick forward_time = clockEdge(forwardLatency) + 211412349Snikos.nikoleris@arm.com pkt->headerDelay; 211512349Snikos.nikoleris@arm.com doWritebacks(writebacks, forward_time); 211612349Snikos.nikoleris@arm.com } else { 211712349Snikos.nikoleris@arm.com doWritebacksAtomic(writebacks); 211812349Snikos.nikoleris@arm.com } 211912349Snikos.nikoleris@arm.com pkt->setSatisfied(); 212012349Snikos.nikoleris@arm.com } 212112349Snikos.nikoleris@arm.com } else if (!blk_valid) { 212211744Snikos.nikoleris@arm.com DPRINTF(CacheVerbose, "%s: snoop miss for %s\n", __func__, 212311744Snikos.nikoleris@arm.com pkt->print()); 212411493Sandreas.hansson@arm.com if (is_deferred) { 212511493Sandreas.hansson@arm.com // we no longer have the block, and will not respond, but a 212611493Sandreas.hansson@arm.com // packet was allocated in MSHR::handleSnoop and we have 212711493Sandreas.hansson@arm.com // to delete it 212811493Sandreas.hansson@arm.com assert(pkt->needsResponse()); 212911493Sandreas.hansson@arm.com 213011493Sandreas.hansson@arm.com // we have passed the block to a cache upstream, that 213111493Sandreas.hansson@arm.com // cache should be responding 213211493Sandreas.hansson@arm.com assert(pkt->cacheResponding()); 213311493Sandreas.hansson@arm.com 213411493Sandreas.hansson@arm.com delete pkt; 213511493Sandreas.hansson@arm.com } 213611127Sandreas.hansson@arm.com return snoop_delay; 213711051Sandreas.hansson@arm.com } else { 213811744Snikos.nikoleris@arm.com DPRINTF(Cache, "%s: snoop hit for %s, old state is %s\n", __func__, 213911744Snikos.nikoleris@arm.com pkt->print(), blk->print()); 214012349Snikos.nikoleris@arm.com 214112349Snikos.nikoleris@arm.com // We may end up modifying both the block state and the packet (if 214212349Snikos.nikoleris@arm.com // we respond in atomic mode), so just figure out what to do now 214312349Snikos.nikoleris@arm.com // and then do it later. We respond to all snoops that need 214412349Snikos.nikoleris@arm.com // responses provided we have the block in dirty state. The 214512349Snikos.nikoleris@arm.com // invalidation itself is taken care of below. We don't respond to 214612349Snikos.nikoleris@arm.com // cache maintenance operations as this is done by the destination 214712349Snikos.nikoleris@arm.com // xbar. 214812349Snikos.nikoleris@arm.com respond = blk->isDirty() && pkt->needsResponse(); 214912349Snikos.nikoleris@arm.com 215012349Snikos.nikoleris@arm.com chatty_assert(!(isReadOnly && blk->isDirty()), "Should never have " 215112349Snikos.nikoleris@arm.com "a dirty block in a read-only cache %s\n", name()); 215211051Sandreas.hansson@arm.com } 215311051Sandreas.hansson@arm.com 215411051Sandreas.hansson@arm.com // Invalidate any prefetch's from below that would strip write permissions 215511051Sandreas.hansson@arm.com // MemCmd::HardPFReq is only observed by upstream caches. After missing 215611051Sandreas.hansson@arm.com // above and in it's own cache, a new MemCmd::ReadReq is created that 215711051Sandreas.hansson@arm.com // downstream caches observe. 215811051Sandreas.hansson@arm.com if (pkt->mustCheckAbove()) { 215911483Snikos.nikoleris@arm.com DPRINTF(Cache, "Found addr %#llx in upper level cache for snoop %s " 216011744Snikos.nikoleris@arm.com "from lower cache\n", pkt->getAddr(), pkt->print()); 216111051Sandreas.hansson@arm.com pkt->setBlockCached(); 216211127Sandreas.hansson@arm.com return snoop_delay; 216311051Sandreas.hansson@arm.com } 216411051Sandreas.hansson@arm.com 216511285Sandreas.hansson@arm.com if (pkt->isRead() && !invalidate) { 216611285Sandreas.hansson@arm.com // reading without requiring the line in a writable state 216711284Sandreas.hansson@arm.com assert(!needs_writable); 216811284Sandreas.hansson@arm.com pkt->setHasSharers(); 216911285Sandreas.hansson@arm.com 217011285Sandreas.hansson@arm.com // if the requesting packet is uncacheable, retain the line in 217111285Sandreas.hansson@arm.com // the current state, otherwhise unset the writable flag, 217211285Sandreas.hansson@arm.com // which means we go from Modified to Owned (and will respond 217311285Sandreas.hansson@arm.com // below), remain in Owned (and will respond below), from 217411285Sandreas.hansson@arm.com // Exclusive to Shared, or remain in Shared 217511285Sandreas.hansson@arm.com if (!pkt->req->isUncacheable()) 217611285Sandreas.hansson@arm.com blk->status &= ~BlkWritable; 217712349Snikos.nikoleris@arm.com DPRINTF(Cache, "new state is %s\n", blk->print()); 217811051Sandreas.hansson@arm.com } 217911051Sandreas.hansson@arm.com 218011051Sandreas.hansson@arm.com if (respond) { 218111051Sandreas.hansson@arm.com // prevent anyone else from responding, cache as well as 218211051Sandreas.hansson@arm.com // memory, and also prevent any memory from even seeing the 218311284Sandreas.hansson@arm.com // request 218411284Sandreas.hansson@arm.com pkt->setCacheResponding(); 218512349Snikos.nikoleris@arm.com if (!pkt->isClean() && blk->isWritable()) { 218611284Sandreas.hansson@arm.com // inform the cache hierarchy that this cache had the line 218711284Sandreas.hansson@arm.com // in the Modified state so that we avoid unnecessary 218811284Sandreas.hansson@arm.com // invalidations (see Packet::setResponderHadWritable) 218911284Sandreas.hansson@arm.com pkt->setResponderHadWritable(); 219011284Sandreas.hansson@arm.com 219111081Sandreas.hansson@arm.com // in the case of an uncacheable request there is no point 219211284Sandreas.hansson@arm.com // in setting the responderHadWritable flag, but since the 219311284Sandreas.hansson@arm.com // recipient does not care there is no harm in doing so 219411284Sandreas.hansson@arm.com } else { 219511284Sandreas.hansson@arm.com // if the packet has needsWritable set we invalidate our 219611284Sandreas.hansson@arm.com // copy below and all other copies will be invalidates 219711284Sandreas.hansson@arm.com // through express snoops, and if needsWritable is not set 219811284Sandreas.hansson@arm.com // we already called setHasSharers above 219911051Sandreas.hansson@arm.com } 220011284Sandreas.hansson@arm.com 220111285Sandreas.hansson@arm.com // if we are returning a writable and dirty (Modified) line, 220211285Sandreas.hansson@arm.com // we should be invalidating the line 220311285Sandreas.hansson@arm.com panic_if(!invalidate && !pkt->hasSharers(), 220411744Snikos.nikoleris@arm.com "%s is passing a Modified line through %s, " 220511744Snikos.nikoleris@arm.com "but keeping the block", name(), pkt->print()); 220611285Sandreas.hansson@arm.com 220711051Sandreas.hansson@arm.com if (is_timing) { 220811051Sandreas.hansson@arm.com doTimingSupplyResponse(pkt, blk->data, is_deferred, pending_inval); 220911051Sandreas.hansson@arm.com } else { 221011051Sandreas.hansson@arm.com pkt->makeAtomicResponse(); 221111286Sandreas.hansson@arm.com // packets such as upgrades do not actually have any data 221211286Sandreas.hansson@arm.com // payload 221311286Sandreas.hansson@arm.com if (pkt->hasData()) 221411286Sandreas.hansson@arm.com pkt->setDataFromBlock(blk->data, blkSize); 221511051Sandreas.hansson@arm.com } 221611051Sandreas.hansson@arm.com } 221711051Sandreas.hansson@arm.com 221811602Sandreas.hansson@arm.com if (!respond && is_deferred) { 221911051Sandreas.hansson@arm.com assert(pkt->needsResponse()); 222011602Sandreas.hansson@arm.com 222111602Sandreas.hansson@arm.com // if we copied the deferred packet with the intention to 222211602Sandreas.hansson@arm.com // respond, but are not responding, then a cache above us must 222311602Sandreas.hansson@arm.com // be, and we can use this as the indication of whether this 222411602Sandreas.hansson@arm.com // is a packet where we created a copy of the request or not 222511602Sandreas.hansson@arm.com if (!pkt->cacheResponding()) { 222611602Sandreas.hansson@arm.com delete pkt->req; 222711602Sandreas.hansson@arm.com } 222811602Sandreas.hansson@arm.com 222911051Sandreas.hansson@arm.com delete pkt; 223011051Sandreas.hansson@arm.com } 223111051Sandreas.hansson@arm.com 223211051Sandreas.hansson@arm.com // Do this last in case it deallocates block data or something 223311051Sandreas.hansson@arm.com // like that 223412349Snikos.nikoleris@arm.com if (blk_valid && invalidate) { 223511197Sandreas.hansson@arm.com invalidateBlock(blk); 223612349Snikos.nikoleris@arm.com DPRINTF(Cache, "new state is %s\n", blk->print()); 223711051Sandreas.hansson@arm.com } 223811051Sandreas.hansson@arm.com 223911127Sandreas.hansson@arm.com return snoop_delay; 224011051Sandreas.hansson@arm.com} 224111051Sandreas.hansson@arm.com 224211051Sandreas.hansson@arm.com 224311051Sandreas.hansson@arm.comvoid 224411051Sandreas.hansson@arm.comCache::recvTimingSnoopReq(PacketPtr pkt) 224511051Sandreas.hansson@arm.com{ 224611744Snikos.nikoleris@arm.com DPRINTF(CacheVerbose, "%s: for %s\n", __func__, pkt->print()); 224711051Sandreas.hansson@arm.com 224811051Sandreas.hansson@arm.com // Snoops shouldn't happen when bypassing caches 224911051Sandreas.hansson@arm.com assert(!system->bypassCaches()); 225011051Sandreas.hansson@arm.com 225111130Sali.jafri@arm.com // no need to snoop requests that are not in range 225211051Sandreas.hansson@arm.com if (!inRange(pkt->getAddr())) { 225311051Sandreas.hansson@arm.com return; 225411051Sandreas.hansson@arm.com } 225511051Sandreas.hansson@arm.com 225611051Sandreas.hansson@arm.com bool is_secure = pkt->isSecure(); 225711051Sandreas.hansson@arm.com CacheBlk *blk = tags->findBlock(pkt->getAddr(), is_secure); 225811051Sandreas.hansson@arm.com 225911892Snikos.nikoleris@arm.com Addr blk_addr = pkt->getBlockAddr(blkSize); 226011051Sandreas.hansson@arm.com MSHR *mshr = mshrQueue.findMatch(blk_addr, is_secure); 226111051Sandreas.hansson@arm.com 226211127Sandreas.hansson@arm.com // Update the latency cost of the snoop so that the crossbar can 226311127Sandreas.hansson@arm.com // account for it. Do not overwrite what other neighbouring caches 226411127Sandreas.hansson@arm.com // have already done, rather take the maximum. The update is 226511127Sandreas.hansson@arm.com // tentative, for cases where we return before an upward snoop 226611127Sandreas.hansson@arm.com // happens below. 226711127Sandreas.hansson@arm.com pkt->snoopDelay = std::max<uint32_t>(pkt->snoopDelay, 226811127Sandreas.hansson@arm.com lookupLatency * clockPeriod()); 226911127Sandreas.hansson@arm.com 227011051Sandreas.hansson@arm.com // Inform request(Prefetch, CleanEvict or Writeback) from below of 227111051Sandreas.hansson@arm.com // MSHR hit, set setBlockCached. 227211051Sandreas.hansson@arm.com if (mshr && pkt->mustCheckAbove()) { 227311744Snikos.nikoleris@arm.com DPRINTF(Cache, "Setting block cached for %s from lower cache on " 227411744Snikos.nikoleris@arm.com "mshr hit\n", pkt->print()); 227511051Sandreas.hansson@arm.com pkt->setBlockCached(); 227611051Sandreas.hansson@arm.com return; 227711051Sandreas.hansson@arm.com } 227811051Sandreas.hansson@arm.com 227912349Snikos.nikoleris@arm.com // Bypass any existing cache maintenance requests if the request 228012349Snikos.nikoleris@arm.com // has been satisfied already (i.e., the dirty block has been 228112349Snikos.nikoleris@arm.com // found). 228212349Snikos.nikoleris@arm.com if (mshr && pkt->req->isCacheMaintenance() && pkt->satisfied()) { 228312349Snikos.nikoleris@arm.com return; 228412349Snikos.nikoleris@arm.com } 228512349Snikos.nikoleris@arm.com 228611051Sandreas.hansson@arm.com // Let the MSHR itself track the snoop and decide whether we want 228711051Sandreas.hansson@arm.com // to go ahead and do the regular cache snoop 228811051Sandreas.hansson@arm.com if (mshr && mshr->handleSnoop(pkt, order++)) { 228911051Sandreas.hansson@arm.com DPRINTF(Cache, "Deferring snoop on in-service MSHR to blk %#llx (%s)." 229011051Sandreas.hansson@arm.com "mshrs: %s\n", blk_addr, is_secure ? "s" : "ns", 229111051Sandreas.hansson@arm.com mshr->print()); 229211051Sandreas.hansson@arm.com 229311051Sandreas.hansson@arm.com if (mshr->getNumTargets() > numTarget) 229411051Sandreas.hansson@arm.com warn("allocating bonus target for snoop"); //handle later 229511051Sandreas.hansson@arm.com return; 229611051Sandreas.hansson@arm.com } 229711051Sandreas.hansson@arm.com 229811051Sandreas.hansson@arm.com //We also need to check the writeback buffers and handle those 229911375Sandreas.hansson@arm.com WriteQueueEntry *wb_entry = writeBuffer.findMatch(blk_addr, is_secure); 230011375Sandreas.hansson@arm.com if (wb_entry) { 230111051Sandreas.hansson@arm.com DPRINTF(Cache, "Snoop hit in writeback to addr %#llx (%s)\n", 230211051Sandreas.hansson@arm.com pkt->getAddr(), is_secure ? "s" : "ns"); 230311051Sandreas.hansson@arm.com // Expect to see only Writebacks and/or CleanEvicts here, both of 230411051Sandreas.hansson@arm.com // which should not be generated for uncacheable data. 230511051Sandreas.hansson@arm.com assert(!wb_entry->isUncacheable()); 230611051Sandreas.hansson@arm.com // There should only be a single request responsible for generating 230711051Sandreas.hansson@arm.com // Writebacks/CleanEvicts. 230811051Sandreas.hansson@arm.com assert(wb_entry->getNumTargets() == 1); 230911051Sandreas.hansson@arm.com PacketPtr wb_pkt = wb_entry->getTarget()->pkt; 231012345Snikos.nikoleris@arm.com assert(wb_pkt->isEviction() || wb_pkt->cmd == MemCmd::WriteClean); 231111051Sandreas.hansson@arm.com 231211199Sandreas.hansson@arm.com if (pkt->isEviction()) { 231311051Sandreas.hansson@arm.com // if the block is found in the write queue, set the BLOCK_CACHED 231411051Sandreas.hansson@arm.com // flag for Writeback/CleanEvict snoop. On return the snoop will 231511051Sandreas.hansson@arm.com // propagate the BLOCK_CACHED flag in Writeback packets and prevent 231611051Sandreas.hansson@arm.com // any CleanEvicts from travelling down the memory hierarchy. 231711051Sandreas.hansson@arm.com pkt->setBlockCached(); 231811744Snikos.nikoleris@arm.com DPRINTF(Cache, "%s: Squashing %s from lower cache on writequeue " 231911744Snikos.nikoleris@arm.com "hit\n", __func__, pkt->print()); 232011051Sandreas.hansson@arm.com return; 232111051Sandreas.hansson@arm.com } 232211051Sandreas.hansson@arm.com 232311332Sandreas.hansson@arm.com // conceptually writebacks are no different to other blocks in 232411332Sandreas.hansson@arm.com // this cache, so the behaviour is modelled after handleSnoop, 232511332Sandreas.hansson@arm.com // the difference being that instead of querying the block 232611332Sandreas.hansson@arm.com // state to determine if it is dirty and writable, we use the 232711332Sandreas.hansson@arm.com // command and fields of the writeback packet 232811332Sandreas.hansson@arm.com bool respond = wb_pkt->cmd == MemCmd::WritebackDirty && 232911751Snikos.nikoleris@arm.com pkt->needsResponse(); 233011332Sandreas.hansson@arm.com bool have_writable = !wb_pkt->hasSharers(); 233111332Sandreas.hansson@arm.com bool invalidate = pkt->isInvalidate(); 233211332Sandreas.hansson@arm.com 233311332Sandreas.hansson@arm.com if (!pkt->req->isUncacheable() && pkt->isRead() && !invalidate) { 233411332Sandreas.hansson@arm.com assert(!pkt->needsWritable()); 233511332Sandreas.hansson@arm.com pkt->setHasSharers(); 233611332Sandreas.hansson@arm.com wb_pkt->setHasSharers(); 233711332Sandreas.hansson@arm.com } 233811332Sandreas.hansson@arm.com 233911332Sandreas.hansson@arm.com if (respond) { 234011284Sandreas.hansson@arm.com pkt->setCacheResponding(); 234111332Sandreas.hansson@arm.com 234211332Sandreas.hansson@arm.com if (have_writable) { 234311332Sandreas.hansson@arm.com pkt->setResponderHadWritable(); 234411051Sandreas.hansson@arm.com } 234511332Sandreas.hansson@arm.com 234611051Sandreas.hansson@arm.com doTimingSupplyResponse(pkt, wb_pkt->getConstPtr<uint8_t>(), 234711051Sandreas.hansson@arm.com false, false); 234811051Sandreas.hansson@arm.com } 234911051Sandreas.hansson@arm.com 235012349Snikos.nikoleris@arm.com if (invalidate && wb_pkt->cmd != MemCmd::WriteClean) { 235111051Sandreas.hansson@arm.com // Invalidation trumps our writeback... discard here 235211051Sandreas.hansson@arm.com // Note: markInService will remove entry from writeback buffer. 235311375Sandreas.hansson@arm.com markInService(wb_entry); 235411051Sandreas.hansson@arm.com delete wb_pkt; 235511051Sandreas.hansson@arm.com } 235611051Sandreas.hansson@arm.com } 235711051Sandreas.hansson@arm.com 235811051Sandreas.hansson@arm.com // If this was a shared writeback, there may still be 235911051Sandreas.hansson@arm.com // other shared copies above that require invalidation. 236011051Sandreas.hansson@arm.com // We could be more selective and return here if the 236111051Sandreas.hansson@arm.com // request is non-exclusive or if the writeback is 236211051Sandreas.hansson@arm.com // exclusive. 236311127Sandreas.hansson@arm.com uint32_t snoop_delay = handleSnoop(pkt, blk, true, false, false); 236411127Sandreas.hansson@arm.com 236511127Sandreas.hansson@arm.com // Override what we did when we first saw the snoop, as we now 236611127Sandreas.hansson@arm.com // also have the cost of the upwards snoops to account for 236711127Sandreas.hansson@arm.com pkt->snoopDelay = std::max<uint32_t>(pkt->snoopDelay, snoop_delay + 236811127Sandreas.hansson@arm.com lookupLatency * clockPeriod()); 236911051Sandreas.hansson@arm.com} 237011051Sandreas.hansson@arm.com 237111051Sandreas.hansson@arm.combool 237211051Sandreas.hansson@arm.comCache::CpuSidePort::recvTimingSnoopResp(PacketPtr pkt) 237311051Sandreas.hansson@arm.com{ 237411051Sandreas.hansson@arm.com // Express snoop responses from master to slave, e.g., from L1 to L2 237511051Sandreas.hansson@arm.com cache->recvTimingSnoopResp(pkt); 237611051Sandreas.hansson@arm.com return true; 237711051Sandreas.hansson@arm.com} 237811051Sandreas.hansson@arm.com 237911051Sandreas.hansson@arm.comTick 238011051Sandreas.hansson@arm.comCache::recvAtomicSnoop(PacketPtr pkt) 238111051Sandreas.hansson@arm.com{ 238211051Sandreas.hansson@arm.com // Snoops shouldn't happen when bypassing caches 238311051Sandreas.hansson@arm.com assert(!system->bypassCaches()); 238411051Sandreas.hansson@arm.com 238511130Sali.jafri@arm.com // no need to snoop requests that are not in range. 238611130Sali.jafri@arm.com if (!inRange(pkt->getAddr())) { 238711051Sandreas.hansson@arm.com return 0; 238811051Sandreas.hansson@arm.com } 238911051Sandreas.hansson@arm.com 239011051Sandreas.hansson@arm.com CacheBlk *blk = tags->findBlock(pkt->getAddr(), pkt->isSecure()); 239111127Sandreas.hansson@arm.com uint32_t snoop_delay = handleSnoop(pkt, blk, false, false, false); 239211127Sandreas.hansson@arm.com return snoop_delay + lookupLatency * clockPeriod(); 239311051Sandreas.hansson@arm.com} 239411051Sandreas.hansson@arm.com 239511051Sandreas.hansson@arm.com 239611375Sandreas.hansson@arm.comQueueEntry* 239711375Sandreas.hansson@arm.comCache::getNextQueueEntry() 239811051Sandreas.hansson@arm.com{ 239911051Sandreas.hansson@arm.com // Check both MSHR queue and write buffer for potential requests, 240011051Sandreas.hansson@arm.com // note that null does not mean there is no request, it could 240111051Sandreas.hansson@arm.com // simply be that it is not ready 240211375Sandreas.hansson@arm.com MSHR *miss_mshr = mshrQueue.getNext(); 240311375Sandreas.hansson@arm.com WriteQueueEntry *wq_entry = writeBuffer.getNext(); 240411051Sandreas.hansson@arm.com 240511051Sandreas.hansson@arm.com // If we got a write buffer request ready, first priority is a 240611453Sandreas.hansson@arm.com // full write buffer, otherwise we favour the miss requests 240711453Sandreas.hansson@arm.com if (wq_entry && (writeBuffer.isFull() || !miss_mshr)) { 240811051Sandreas.hansson@arm.com // need to search MSHR queue for conflicting earlier miss. 240911051Sandreas.hansson@arm.com MSHR *conflict_mshr = 241011375Sandreas.hansson@arm.com mshrQueue.findPending(wq_entry->blkAddr, 241111375Sandreas.hansson@arm.com wq_entry->isSecure); 241211375Sandreas.hansson@arm.com 241311375Sandreas.hansson@arm.com if (conflict_mshr && conflict_mshr->order < wq_entry->order) { 241411051Sandreas.hansson@arm.com // Service misses in order until conflict is cleared. 241511051Sandreas.hansson@arm.com return conflict_mshr; 241611051Sandreas.hansson@arm.com 241711051Sandreas.hansson@arm.com // @todo Note that we ignore the ready time of the conflict here 241811051Sandreas.hansson@arm.com } 241911051Sandreas.hansson@arm.com 242011051Sandreas.hansson@arm.com // No conflicts; issue write 242111375Sandreas.hansson@arm.com return wq_entry; 242211051Sandreas.hansson@arm.com } else if (miss_mshr) { 242311051Sandreas.hansson@arm.com // need to check for conflicting earlier writeback 242411375Sandreas.hansson@arm.com WriteQueueEntry *conflict_mshr = 242511051Sandreas.hansson@arm.com writeBuffer.findPending(miss_mshr->blkAddr, 242611051Sandreas.hansson@arm.com miss_mshr->isSecure); 242711051Sandreas.hansson@arm.com if (conflict_mshr) { 242811051Sandreas.hansson@arm.com // not sure why we don't check order here... it was in the 242911051Sandreas.hansson@arm.com // original code but commented out. 243011051Sandreas.hansson@arm.com 243111051Sandreas.hansson@arm.com // The only way this happens is if we are 243211051Sandreas.hansson@arm.com // doing a write and we didn't have permissions 243311051Sandreas.hansson@arm.com // then subsequently saw a writeback (owned got evicted) 243411051Sandreas.hansson@arm.com // We need to make sure to perform the writeback first 243511051Sandreas.hansson@arm.com // To preserve the dirty data, then we can issue the write 243611051Sandreas.hansson@arm.com 243711375Sandreas.hansson@arm.com // should we return wq_entry here instead? I.e. do we 243811051Sandreas.hansson@arm.com // have to flush writes in order? I don't think so... not 243911051Sandreas.hansson@arm.com // for Alpha anyway. Maybe for x86? 244011051Sandreas.hansson@arm.com return conflict_mshr; 244111051Sandreas.hansson@arm.com 244211051Sandreas.hansson@arm.com // @todo Note that we ignore the ready time of the conflict here 244311051Sandreas.hansson@arm.com } 244411051Sandreas.hansson@arm.com 244511051Sandreas.hansson@arm.com // No conflicts; issue read 244611051Sandreas.hansson@arm.com return miss_mshr; 244711051Sandreas.hansson@arm.com } 244811051Sandreas.hansson@arm.com 244911051Sandreas.hansson@arm.com // fall through... no pending requests. Try a prefetch. 245011375Sandreas.hansson@arm.com assert(!miss_mshr && !wq_entry); 245111051Sandreas.hansson@arm.com if (prefetcher && mshrQueue.canPrefetch()) { 245211051Sandreas.hansson@arm.com // If we have a miss queue slot, we can try a prefetch 245311051Sandreas.hansson@arm.com PacketPtr pkt = prefetcher->getPacket(); 245411051Sandreas.hansson@arm.com if (pkt) { 245511892Snikos.nikoleris@arm.com Addr pf_addr = pkt->getBlockAddr(blkSize); 245611051Sandreas.hansson@arm.com if (!tags->findBlock(pf_addr, pkt->isSecure()) && 245711051Sandreas.hansson@arm.com !mshrQueue.findMatch(pf_addr, pkt->isSecure()) && 245811051Sandreas.hansson@arm.com !writeBuffer.findMatch(pf_addr, pkt->isSecure())) { 245911051Sandreas.hansson@arm.com // Update statistic on number of prefetches issued 246011051Sandreas.hansson@arm.com // (hwpf_mshr_misses) 246111051Sandreas.hansson@arm.com assert(pkt->req->masterId() < system->maxMasters()); 246211051Sandreas.hansson@arm.com mshr_misses[pkt->cmdToIndex()][pkt->req->masterId()]++; 246311051Sandreas.hansson@arm.com 246411051Sandreas.hansson@arm.com // allocate an MSHR and return it, note 246511051Sandreas.hansson@arm.com // that we send the packet straight away, so do not 246611051Sandreas.hansson@arm.com // schedule the send 246711051Sandreas.hansson@arm.com return allocateMissBuffer(pkt, curTick(), false); 246811051Sandreas.hansson@arm.com } else { 246911051Sandreas.hansson@arm.com // free the request and packet 247011051Sandreas.hansson@arm.com delete pkt->req; 247111051Sandreas.hansson@arm.com delete pkt; 247211051Sandreas.hansson@arm.com } 247311051Sandreas.hansson@arm.com } 247411051Sandreas.hansson@arm.com } 247511051Sandreas.hansson@arm.com 247611375Sandreas.hansson@arm.com return nullptr; 247711051Sandreas.hansson@arm.com} 247811051Sandreas.hansson@arm.com 247911051Sandreas.hansson@arm.combool 248011130Sali.jafri@arm.comCache::isCachedAbove(PacketPtr pkt, bool is_timing) const 248111051Sandreas.hansson@arm.com{ 248211051Sandreas.hansson@arm.com if (!forwardSnoops) 248311051Sandreas.hansson@arm.com return false; 248411051Sandreas.hansson@arm.com // Mirroring the flow of HardPFReqs, the cache sends CleanEvict and 248511051Sandreas.hansson@arm.com // Writeback snoops into upper level caches to check for copies of the 248611051Sandreas.hansson@arm.com // same block. Using the BLOCK_CACHED flag with the Writeback/CleanEvict 248711051Sandreas.hansson@arm.com // packet, the cache can inform the crossbar below of presence or absence 248811051Sandreas.hansson@arm.com // of the block. 248911130Sali.jafri@arm.com if (is_timing) { 249011130Sali.jafri@arm.com Packet snoop_pkt(pkt, true, false); 249111130Sali.jafri@arm.com snoop_pkt.setExpressSnoop(); 249211130Sali.jafri@arm.com // Assert that packet is either Writeback or CleanEvict and not a 249311130Sali.jafri@arm.com // prefetch request because prefetch requests need an MSHR and may 249411130Sali.jafri@arm.com // generate a snoop response. 249512345Snikos.nikoleris@arm.com assert(pkt->isEviction() || pkt->cmd == MemCmd::WriteClean); 249611484Snikos.nikoleris@arm.com snoop_pkt.senderState = nullptr; 249711130Sali.jafri@arm.com cpuSidePort->sendTimingSnoopReq(&snoop_pkt); 249811130Sali.jafri@arm.com // Writeback/CleanEvict snoops do not generate a snoop response. 249911284Sandreas.hansson@arm.com assert(!(snoop_pkt.cacheResponding())); 250011130Sali.jafri@arm.com return snoop_pkt.isBlockCached(); 250111130Sali.jafri@arm.com } else { 250211130Sali.jafri@arm.com cpuSidePort->sendAtomicSnoop(pkt); 250311130Sali.jafri@arm.com return pkt->isBlockCached(); 250411130Sali.jafri@arm.com } 250511051Sandreas.hansson@arm.com} 250611051Sandreas.hansson@arm.com 250711375Sandreas.hansson@arm.comTick 250811375Sandreas.hansson@arm.comCache::nextQueueReadyTime() const 250911051Sandreas.hansson@arm.com{ 251011375Sandreas.hansson@arm.com Tick nextReady = std::min(mshrQueue.nextReadyTime(), 251111375Sandreas.hansson@arm.com writeBuffer.nextReadyTime()); 251211375Sandreas.hansson@arm.com 251311375Sandreas.hansson@arm.com // Don't signal prefetch ready time if no MSHRs available 251411375Sandreas.hansson@arm.com // Will signal once enoguh MSHRs are deallocated 251511375Sandreas.hansson@arm.com if (prefetcher && mshrQueue.canPrefetch()) { 251611375Sandreas.hansson@arm.com nextReady = std::min(nextReady, 251711375Sandreas.hansson@arm.com prefetcher->nextPrefetchReadyTime()); 251811051Sandreas.hansson@arm.com } 251911051Sandreas.hansson@arm.com 252011375Sandreas.hansson@arm.com return nextReady; 252111375Sandreas.hansson@arm.com} 252211375Sandreas.hansson@arm.com 252311375Sandreas.hansson@arm.combool 252411375Sandreas.hansson@arm.comCache::sendMSHRQueuePacket(MSHR* mshr) 252511375Sandreas.hansson@arm.com{ 252611375Sandreas.hansson@arm.com assert(mshr); 252711375Sandreas.hansson@arm.com 252811051Sandreas.hansson@arm.com // use request from 1st target 252911051Sandreas.hansson@arm.com PacketPtr tgt_pkt = mshr->getTarget()->pkt; 253011375Sandreas.hansson@arm.com 253111744Snikos.nikoleris@arm.com DPRINTF(Cache, "%s: MSHR %s\n", __func__, tgt_pkt->print()); 253211051Sandreas.hansson@arm.com 253311051Sandreas.hansson@arm.com CacheBlk *blk = tags->findBlock(mshr->blkAddr, mshr->isSecure); 253411051Sandreas.hansson@arm.com 253511051Sandreas.hansson@arm.com if (tgt_pkt->cmd == MemCmd::HardPFReq && forwardSnoops) { 253611375Sandreas.hansson@arm.com // we should never have hardware prefetches to allocated 253711375Sandreas.hansson@arm.com // blocks 253811484Snikos.nikoleris@arm.com assert(blk == nullptr); 253911375Sandreas.hansson@arm.com 254011051Sandreas.hansson@arm.com // We need to check the caches above us to verify that 254111051Sandreas.hansson@arm.com // they don't have a copy of this block in the dirty state 254211051Sandreas.hansson@arm.com // at the moment. Without this check we could get a stale 254311051Sandreas.hansson@arm.com // copy from memory that might get used in place of the 254411051Sandreas.hansson@arm.com // dirty one. 254511051Sandreas.hansson@arm.com Packet snoop_pkt(tgt_pkt, true, false); 254611051Sandreas.hansson@arm.com snoop_pkt.setExpressSnoop(); 254711275Sandreas.hansson@arm.com // We are sending this packet upwards, but if it hits we will 254811275Sandreas.hansson@arm.com // get a snoop response that we end up treating just like a 254911275Sandreas.hansson@arm.com // normal response, hence it needs the MSHR as its sender 255011275Sandreas.hansson@arm.com // state 255111051Sandreas.hansson@arm.com snoop_pkt.senderState = mshr; 255211051Sandreas.hansson@arm.com cpuSidePort->sendTimingSnoopReq(&snoop_pkt); 255311051Sandreas.hansson@arm.com 255411051Sandreas.hansson@arm.com // Check to see if the prefetch was squashed by an upper cache (to 255511051Sandreas.hansson@arm.com // prevent us from grabbing the line) or if a Check to see if a 255611051Sandreas.hansson@arm.com // writeback arrived between the time the prefetch was placed in 255711051Sandreas.hansson@arm.com // the MSHRs and when it was selected to be sent or if the 255811051Sandreas.hansson@arm.com // prefetch was squashed by an upper cache. 255911051Sandreas.hansson@arm.com 256011284Sandreas.hansson@arm.com // It is important to check cacheResponding before 256111284Sandreas.hansson@arm.com // prefetchSquashed. If another cache has committed to 256211284Sandreas.hansson@arm.com // responding, it will be sending a dirty response which will 256311284Sandreas.hansson@arm.com // arrive at the MSHR allocated for this request. Checking the 256411284Sandreas.hansson@arm.com // prefetchSquash first may result in the MSHR being 256511284Sandreas.hansson@arm.com // prematurely deallocated. 256611284Sandreas.hansson@arm.com if (snoop_pkt.cacheResponding()) { 256711276Sandreas.hansson@arm.com auto M5_VAR_USED r = outstandingSnoop.insert(snoop_pkt.req); 256811276Sandreas.hansson@arm.com assert(r.second); 256911284Sandreas.hansson@arm.com 257011284Sandreas.hansson@arm.com // if we are getting a snoop response with no sharers it 257111284Sandreas.hansson@arm.com // will be allocated as Modified 257211284Sandreas.hansson@arm.com bool pending_modified_resp = !snoop_pkt.hasSharers(); 257311284Sandreas.hansson@arm.com markInService(mshr, pending_modified_resp); 257411284Sandreas.hansson@arm.com 257511051Sandreas.hansson@arm.com DPRINTF(Cache, "Upward snoop of prefetch for addr" 257611051Sandreas.hansson@arm.com " %#x (%s) hit\n", 257711051Sandreas.hansson@arm.com tgt_pkt->getAddr(), tgt_pkt->isSecure()? "s": "ns"); 257811375Sandreas.hansson@arm.com return false; 257911051Sandreas.hansson@arm.com } 258011051Sandreas.hansson@arm.com 258111375Sandreas.hansson@arm.com if (snoop_pkt.isBlockCached()) { 258211051Sandreas.hansson@arm.com DPRINTF(Cache, "Block present, prefetch squashed by cache. " 258311051Sandreas.hansson@arm.com "Deallocating mshr target %#x.\n", 258411051Sandreas.hansson@arm.com mshr->blkAddr); 258511375Sandreas.hansson@arm.com 258611051Sandreas.hansson@arm.com // Deallocate the mshr target 258711375Sandreas.hansson@arm.com if (mshrQueue.forceDeallocateTarget(mshr)) { 258811277Sandreas.hansson@arm.com // Clear block if this deallocation resulted freed an 258911277Sandreas.hansson@arm.com // mshr when all had previously been utilized 259011375Sandreas.hansson@arm.com clearBlocked(Blocked_NoMSHRs); 259111051Sandreas.hansson@arm.com } 259212167Spau.cabre@metempsy.com 259312167Spau.cabre@metempsy.com // given that no response is expected, delete Request and Packet 259412167Spau.cabre@metempsy.com delete tgt_pkt->req; 259512167Spau.cabre@metempsy.com delete tgt_pkt; 259612167Spau.cabre@metempsy.com 259711375Sandreas.hansson@arm.com return false; 259811051Sandreas.hansson@arm.com } 259911051Sandreas.hansson@arm.com } 260011051Sandreas.hansson@arm.com 260111375Sandreas.hansson@arm.com // either a prefetch that is not present upstream, or a normal 260211375Sandreas.hansson@arm.com // MSHR request, proceed to get the packet to send downstream 260311452Sandreas.hansson@arm.com PacketPtr pkt = createMissPacket(tgt_pkt, blk, mshr->needsWritable()); 260411375Sandreas.hansson@arm.com 260511484Snikos.nikoleris@arm.com mshr->isForward = (pkt == nullptr); 260611375Sandreas.hansson@arm.com 260711375Sandreas.hansson@arm.com if (mshr->isForward) { 260811375Sandreas.hansson@arm.com // not a cache block request, but a response is expected 260911375Sandreas.hansson@arm.com // make copy of current packet to forward, keep current 261011375Sandreas.hansson@arm.com // copy for response handling 261111375Sandreas.hansson@arm.com pkt = new Packet(tgt_pkt, false, true); 261211375Sandreas.hansson@arm.com assert(!pkt->isWrite()); 261311375Sandreas.hansson@arm.com } 261411375Sandreas.hansson@arm.com 261511375Sandreas.hansson@arm.com // play it safe and append (rather than set) the sender state, 261611375Sandreas.hansson@arm.com // as forwarded packets may already have existing state 261711375Sandreas.hansson@arm.com pkt->pushSenderState(mshr); 261811375Sandreas.hansson@arm.com 261912349Snikos.nikoleris@arm.com if (pkt->isClean() && blk && blk->isDirty()) { 262012349Snikos.nikoleris@arm.com // A cache clean opearation is looking for a dirty block. Mark 262112349Snikos.nikoleris@arm.com // the packet so that the destination xbar can determine that 262212349Snikos.nikoleris@arm.com // there will be a follow-up write packet as well. 262312349Snikos.nikoleris@arm.com pkt->setSatisfied(); 262412349Snikos.nikoleris@arm.com } 262512349Snikos.nikoleris@arm.com 262611375Sandreas.hansson@arm.com if (!memSidePort->sendTimingReq(pkt)) { 262711375Sandreas.hansson@arm.com // we are awaiting a retry, but we 262811375Sandreas.hansson@arm.com // delete the packet and will be creating a new packet 262911375Sandreas.hansson@arm.com // when we get the opportunity 263011375Sandreas.hansson@arm.com delete pkt; 263111375Sandreas.hansson@arm.com 263211375Sandreas.hansson@arm.com // note that we have now masked any requestBus and 263311375Sandreas.hansson@arm.com // schedSendEvent (we will wait for a retry before 263411375Sandreas.hansson@arm.com // doing anything), and this is so even if we do not 263511375Sandreas.hansson@arm.com // care about this packet and might override it before 263611375Sandreas.hansson@arm.com // it gets retried 263711375Sandreas.hansson@arm.com return true; 263811375Sandreas.hansson@arm.com } else { 263911375Sandreas.hansson@arm.com // As part of the call to sendTimingReq the packet is 264011375Sandreas.hansson@arm.com // forwarded to all neighbouring caches (and any caches 264111375Sandreas.hansson@arm.com // above them) as a snoop. Thus at this point we know if 264211375Sandreas.hansson@arm.com // any of the neighbouring caches are responding, and if 264311375Sandreas.hansson@arm.com // so, we know it is dirty, and we can determine if it is 264411375Sandreas.hansson@arm.com // being passed as Modified, making our MSHR the ordering 264511375Sandreas.hansson@arm.com // point 264611375Sandreas.hansson@arm.com bool pending_modified_resp = !pkt->hasSharers() && 264711375Sandreas.hansson@arm.com pkt->cacheResponding(); 264811375Sandreas.hansson@arm.com markInService(mshr, pending_modified_resp); 264912349Snikos.nikoleris@arm.com if (pkt->isClean() && blk && blk->isDirty()) { 265012349Snikos.nikoleris@arm.com // A cache clean opearation is looking for a dirty 265112349Snikos.nikoleris@arm.com // block. If a dirty block is encountered a WriteClean 265212349Snikos.nikoleris@arm.com // will update any copies to the path to the memory 265312349Snikos.nikoleris@arm.com // until the point of reference. 265412349Snikos.nikoleris@arm.com DPRINTF(CacheVerbose, "%s: packet %s found block: %s\n", 265512349Snikos.nikoleris@arm.com __func__, pkt->print(), blk->print()); 265612351Snikos.nikoleris@arm.com PacketPtr wb_pkt = writecleanBlk(blk, pkt->req->getDest(), 265712351Snikos.nikoleris@arm.com pkt->id); 265812349Snikos.nikoleris@arm.com PacketList writebacks; 265912349Snikos.nikoleris@arm.com writebacks.push_back(wb_pkt); 266012349Snikos.nikoleris@arm.com doWritebacks(writebacks, 0); 266112349Snikos.nikoleris@arm.com } 266212349Snikos.nikoleris@arm.com 266311375Sandreas.hansson@arm.com return false; 266411375Sandreas.hansson@arm.com } 266511375Sandreas.hansson@arm.com} 266611375Sandreas.hansson@arm.com 266711375Sandreas.hansson@arm.combool 266811375Sandreas.hansson@arm.comCache::sendWriteQueuePacket(WriteQueueEntry* wq_entry) 266911375Sandreas.hansson@arm.com{ 267011375Sandreas.hansson@arm.com assert(wq_entry); 267111375Sandreas.hansson@arm.com 267211375Sandreas.hansson@arm.com // always a single target for write queue entries 267311375Sandreas.hansson@arm.com PacketPtr tgt_pkt = wq_entry->getTarget()->pkt; 267411375Sandreas.hansson@arm.com 267511744Snikos.nikoleris@arm.com DPRINTF(Cache, "%s: write %s\n", __func__, tgt_pkt->print()); 267611375Sandreas.hansson@arm.com 267711453Sandreas.hansson@arm.com // forward as is, both for evictions and uncacheable writes 267811453Sandreas.hansson@arm.com if (!memSidePort->sendTimingReq(tgt_pkt)) { 267911375Sandreas.hansson@arm.com // note that we have now masked any requestBus and 268011375Sandreas.hansson@arm.com // schedSendEvent (we will wait for a retry before 268111375Sandreas.hansson@arm.com // doing anything), and this is so even if we do not 268211375Sandreas.hansson@arm.com // care about this packet and might override it before 268311375Sandreas.hansson@arm.com // it gets retried 268411375Sandreas.hansson@arm.com return true; 268511375Sandreas.hansson@arm.com } else { 268611375Sandreas.hansson@arm.com markInService(wq_entry); 268711375Sandreas.hansson@arm.com return false; 268811051Sandreas.hansson@arm.com } 268911051Sandreas.hansson@arm.com} 269011051Sandreas.hansson@arm.com 269111051Sandreas.hansson@arm.comvoid 269211051Sandreas.hansson@arm.comCache::serialize(CheckpointOut &cp) const 269311051Sandreas.hansson@arm.com{ 269411051Sandreas.hansson@arm.com bool dirty(isDirty()); 269511051Sandreas.hansson@arm.com 269611051Sandreas.hansson@arm.com if (dirty) { 269711051Sandreas.hansson@arm.com warn("*** The cache still contains dirty data. ***\n"); 269811051Sandreas.hansson@arm.com warn(" Make sure to drain the system using the correct flags.\n"); 269911483Snikos.nikoleris@arm.com warn(" This checkpoint will not restore correctly and dirty data " 270011483Snikos.nikoleris@arm.com " in the cache will be lost!\n"); 270111051Sandreas.hansson@arm.com } 270211051Sandreas.hansson@arm.com 270311051Sandreas.hansson@arm.com // Since we don't checkpoint the data in the cache, any dirty data 270411051Sandreas.hansson@arm.com // will be lost when restoring from a checkpoint of a system that 270511051Sandreas.hansson@arm.com // wasn't drained properly. Flag the checkpoint as invalid if the 270611051Sandreas.hansson@arm.com // cache contains dirty data. 270711051Sandreas.hansson@arm.com bool bad_checkpoint(dirty); 270811051Sandreas.hansson@arm.com SERIALIZE_SCALAR(bad_checkpoint); 270911051Sandreas.hansson@arm.com} 271011051Sandreas.hansson@arm.com 271111051Sandreas.hansson@arm.comvoid 271211051Sandreas.hansson@arm.comCache::unserialize(CheckpointIn &cp) 271311051Sandreas.hansson@arm.com{ 271411051Sandreas.hansson@arm.com bool bad_checkpoint; 271511051Sandreas.hansson@arm.com UNSERIALIZE_SCALAR(bad_checkpoint); 271611051Sandreas.hansson@arm.com if (bad_checkpoint) { 271711051Sandreas.hansson@arm.com fatal("Restoring from checkpoints with dirty caches is not supported " 271811051Sandreas.hansson@arm.com "in the classic memory system. Please remove any caches or " 271911051Sandreas.hansson@arm.com " drain them properly before taking checkpoints.\n"); 272011051Sandreas.hansson@arm.com } 272111051Sandreas.hansson@arm.com} 272211051Sandreas.hansson@arm.com 272311051Sandreas.hansson@arm.com/////////////// 272411051Sandreas.hansson@arm.com// 272511051Sandreas.hansson@arm.com// CpuSidePort 272611051Sandreas.hansson@arm.com// 272711051Sandreas.hansson@arm.com/////////////// 272811051Sandreas.hansson@arm.com 272911051Sandreas.hansson@arm.comAddrRangeList 273011051Sandreas.hansson@arm.comCache::CpuSidePort::getAddrRanges() const 273111051Sandreas.hansson@arm.com{ 273211051Sandreas.hansson@arm.com return cache->getAddrRanges(); 273311051Sandreas.hansson@arm.com} 273411051Sandreas.hansson@arm.com 273511051Sandreas.hansson@arm.combool 273612343Snikos.nikoleris@arm.comCache::CpuSidePort::tryTiming(PacketPtr pkt) 273712343Snikos.nikoleris@arm.com{ 273812343Snikos.nikoleris@arm.com assert(!cache->system->bypassCaches()); 273912343Snikos.nikoleris@arm.com 274012343Snikos.nikoleris@arm.com // always let express snoop packets through if even if blocked 274112343Snikos.nikoleris@arm.com if (pkt->isExpressSnoop()) { 274212343Snikos.nikoleris@arm.com return true; 274312343Snikos.nikoleris@arm.com } else if (isBlocked() || mustSendRetry) { 274412343Snikos.nikoleris@arm.com // either already committed to send a retry, or blocked 274512343Snikos.nikoleris@arm.com mustSendRetry = true; 274612343Snikos.nikoleris@arm.com return false; 274712343Snikos.nikoleris@arm.com } 274812343Snikos.nikoleris@arm.com mustSendRetry = false; 274912343Snikos.nikoleris@arm.com return true; 275012343Snikos.nikoleris@arm.com} 275112343Snikos.nikoleris@arm.com 275212343Snikos.nikoleris@arm.combool 275311051Sandreas.hansson@arm.comCache::CpuSidePort::recvTimingReq(PacketPtr pkt) 275411051Sandreas.hansson@arm.com{ 275511051Sandreas.hansson@arm.com assert(!cache->system->bypassCaches()); 275611051Sandreas.hansson@arm.com 275711334Sandreas.hansson@arm.com // always let express snoop packets through if even if blocked 275811334Sandreas.hansson@arm.com if (pkt->isExpressSnoop()) { 275911051Sandreas.hansson@arm.com bool M5_VAR_USED bypass_success = cache->recvTimingReq(pkt); 276011051Sandreas.hansson@arm.com assert(bypass_success); 276111051Sandreas.hansson@arm.com return true; 276211051Sandreas.hansson@arm.com } 276311051Sandreas.hansson@arm.com 276412343Snikos.nikoleris@arm.com return tryTiming(pkt) && cache->recvTimingReq(pkt); 276511051Sandreas.hansson@arm.com} 276611051Sandreas.hansson@arm.com 276711051Sandreas.hansson@arm.comTick 276811051Sandreas.hansson@arm.comCache::CpuSidePort::recvAtomic(PacketPtr pkt) 276911051Sandreas.hansson@arm.com{ 277011051Sandreas.hansson@arm.com return cache->recvAtomic(pkt); 277111051Sandreas.hansson@arm.com} 277211051Sandreas.hansson@arm.com 277311051Sandreas.hansson@arm.comvoid 277411051Sandreas.hansson@arm.comCache::CpuSidePort::recvFunctional(PacketPtr pkt) 277511051Sandreas.hansson@arm.com{ 277611051Sandreas.hansson@arm.com // functional request 277711051Sandreas.hansson@arm.com cache->functionalAccess(pkt, true); 277811051Sandreas.hansson@arm.com} 277911051Sandreas.hansson@arm.com 278011051Sandreas.hansson@arm.comCache:: 278111051Sandreas.hansson@arm.comCpuSidePort::CpuSidePort(const std::string &_name, Cache *_cache, 278211051Sandreas.hansson@arm.com const std::string &_label) 278311051Sandreas.hansson@arm.com : BaseCache::CacheSlavePort(_name, _cache, _label), cache(_cache) 278411051Sandreas.hansson@arm.com{ 278511051Sandreas.hansson@arm.com} 278611051Sandreas.hansson@arm.com 278711053Sandreas.hansson@arm.comCache* 278811053Sandreas.hansson@arm.comCacheParams::create() 278911053Sandreas.hansson@arm.com{ 279011053Sandreas.hansson@arm.com assert(tags); 279111053Sandreas.hansson@arm.com 279211053Sandreas.hansson@arm.com return new Cache(this); 279311053Sandreas.hansson@arm.com} 279411051Sandreas.hansson@arm.com/////////////// 279511051Sandreas.hansson@arm.com// 279611051Sandreas.hansson@arm.com// MemSidePort 279711051Sandreas.hansson@arm.com// 279811051Sandreas.hansson@arm.com/////////////// 279911051Sandreas.hansson@arm.com 280011051Sandreas.hansson@arm.combool 280111051Sandreas.hansson@arm.comCache::MemSidePort::recvTimingResp(PacketPtr pkt) 280211051Sandreas.hansson@arm.com{ 280311051Sandreas.hansson@arm.com cache->recvTimingResp(pkt); 280411051Sandreas.hansson@arm.com return true; 280511051Sandreas.hansson@arm.com} 280611051Sandreas.hansson@arm.com 280711051Sandreas.hansson@arm.com// Express snooping requests to memside port 280811051Sandreas.hansson@arm.comvoid 280911051Sandreas.hansson@arm.comCache::MemSidePort::recvTimingSnoopReq(PacketPtr pkt) 281011051Sandreas.hansson@arm.com{ 281111051Sandreas.hansson@arm.com // handle snooping requests 281211051Sandreas.hansson@arm.com cache->recvTimingSnoopReq(pkt); 281311051Sandreas.hansson@arm.com} 281411051Sandreas.hansson@arm.com 281511051Sandreas.hansson@arm.comTick 281611051Sandreas.hansson@arm.comCache::MemSidePort::recvAtomicSnoop(PacketPtr pkt) 281711051Sandreas.hansson@arm.com{ 281811051Sandreas.hansson@arm.com return cache->recvAtomicSnoop(pkt); 281911051Sandreas.hansson@arm.com} 282011051Sandreas.hansson@arm.com 282111051Sandreas.hansson@arm.comvoid 282211051Sandreas.hansson@arm.comCache::MemSidePort::recvFunctionalSnoop(PacketPtr pkt) 282311051Sandreas.hansson@arm.com{ 282411051Sandreas.hansson@arm.com // functional snoop (note that in contrast to atomic we don't have 282511051Sandreas.hansson@arm.com // a specific functionalSnoop method, as they have the same 282611051Sandreas.hansson@arm.com // behaviour regardless) 282711051Sandreas.hansson@arm.com cache->functionalAccess(pkt, false); 282811051Sandreas.hansson@arm.com} 282911051Sandreas.hansson@arm.com 283011051Sandreas.hansson@arm.comvoid 283111051Sandreas.hansson@arm.comCache::CacheReqPacketQueue::sendDeferredPacket() 283211051Sandreas.hansson@arm.com{ 283311051Sandreas.hansson@arm.com // sanity check 283411051Sandreas.hansson@arm.com assert(!waitingOnRetry); 283511051Sandreas.hansson@arm.com 283611051Sandreas.hansson@arm.com // there should never be any deferred request packets in the 283711051Sandreas.hansson@arm.com // queue, instead we resly on the cache to provide the packets 283811051Sandreas.hansson@arm.com // from the MSHR queue or write queue 283911051Sandreas.hansson@arm.com assert(deferredPacketReadyTime() == MaxTick); 284011051Sandreas.hansson@arm.com 284111051Sandreas.hansson@arm.com // check for request packets (requests & writebacks) 284211375Sandreas.hansson@arm.com QueueEntry* entry = cache.getNextQueueEntry(); 284311375Sandreas.hansson@arm.com 284411375Sandreas.hansson@arm.com if (!entry) { 284511051Sandreas.hansson@arm.com // can happen if e.g. we attempt a writeback and fail, but 284611051Sandreas.hansson@arm.com // before the retry, the writeback is eliminated because 284711051Sandreas.hansson@arm.com // we snoop another cache's ReadEx. 284811051Sandreas.hansson@arm.com } else { 284911051Sandreas.hansson@arm.com // let our snoop responses go first if there are responses to 285011375Sandreas.hansson@arm.com // the same addresses 285111375Sandreas.hansson@arm.com if (checkConflictingSnoop(entry->blkAddr)) { 285211051Sandreas.hansson@arm.com return; 285311051Sandreas.hansson@arm.com } 285411375Sandreas.hansson@arm.com waitingOnRetry = entry->sendPacket(cache); 285511051Sandreas.hansson@arm.com } 285611051Sandreas.hansson@arm.com 285711051Sandreas.hansson@arm.com // if we succeeded and are not waiting for a retry, schedule the 285811375Sandreas.hansson@arm.com // next send considering when the next queue is ready, note that 285911051Sandreas.hansson@arm.com // snoop responses have their own packet queue and thus schedule 286011051Sandreas.hansson@arm.com // their own events 286111051Sandreas.hansson@arm.com if (!waitingOnRetry) { 286211375Sandreas.hansson@arm.com schedSendEvent(cache.nextQueueReadyTime()); 286311051Sandreas.hansson@arm.com } 286411051Sandreas.hansson@arm.com} 286511051Sandreas.hansson@arm.com 286611051Sandreas.hansson@arm.comCache:: 286711051Sandreas.hansson@arm.comMemSidePort::MemSidePort(const std::string &_name, Cache *_cache, 286811051Sandreas.hansson@arm.com const std::string &_label) 286911051Sandreas.hansson@arm.com : BaseCache::CacheMasterPort(_name, _cache, _reqQueue, _snoopRespQueue), 287011051Sandreas.hansson@arm.com _reqQueue(*_cache, *this, _snoopRespQueue, _label), 287111051Sandreas.hansson@arm.com _snoopRespQueue(*_cache, *this, _label), cache(_cache) 287211051Sandreas.hansson@arm.com{ 287311051Sandreas.hansson@arm.com} 2874