cache.cc revision 11892
12810Srdreslin@umich.edu/* 211051Sandreas.hansson@arm.com * Copyright (c) 2010-2016 ARM Limited 311051Sandreas.hansson@arm.com * All rights reserved. 411051Sandreas.hansson@arm.com * 511051Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall 611051Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual 711051Sandreas.hansson@arm.com * property including but not limited to intellectual property relating 811051Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software 911051Sandreas.hansson@arm.com * licensed hereunder. You may use the software subject to the license 1011051Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated 1111051Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software, 1211051Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form. 1311051Sandreas.hansson@arm.com * 1411051Sandreas.hansson@arm.com * Copyright (c) 2002-2005 The Regents of The University of Michigan 1511051Sandreas.hansson@arm.com * Copyright (c) 2010,2015 Advanced Micro Devices, Inc. 162810Srdreslin@umich.edu * All rights reserved. 172810Srdreslin@umich.edu * 182810Srdreslin@umich.edu * Redistribution and use in source and binary forms, with or without 192810Srdreslin@umich.edu * modification, are permitted provided that the following conditions are 202810Srdreslin@umich.edu * met: redistributions of source code must retain the above copyright 212810Srdreslin@umich.edu * notice, this list of conditions and the following disclaimer; 222810Srdreslin@umich.edu * redistributions in binary form must reproduce the above copyright 232810Srdreslin@umich.edu * notice, this list of conditions and the following disclaimer in the 242810Srdreslin@umich.edu * documentation and/or other materials provided with the distribution; 252810Srdreslin@umich.edu * neither the name of the copyright holders nor the names of its 262810Srdreslin@umich.edu * contributors may be used to endorse or promote products derived from 272810Srdreslin@umich.edu * this software without specific prior written permission. 282810Srdreslin@umich.edu * 292810Srdreslin@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 302810Srdreslin@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 312810Srdreslin@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 322810Srdreslin@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 332810Srdreslin@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 342810Srdreslin@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 352810Srdreslin@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 362810Srdreslin@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 372810Srdreslin@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 382810Srdreslin@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 392810Srdreslin@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402810Srdreslin@umich.edu * 412810Srdreslin@umich.edu * Authors: Erik Hallnor 4211051Sandreas.hansson@arm.com * Dave Greene 4311051Sandreas.hansson@arm.com * Nathan Binkert 442810Srdreslin@umich.edu * Steve Reinhardt 4511051Sandreas.hansson@arm.com * Ron Dreslinski 4611051Sandreas.hansson@arm.com * Andreas Sandberg 472810Srdreslin@umich.edu */ 482810Srdreslin@umich.edu 492810Srdreslin@umich.edu/** 502810Srdreslin@umich.edu * @file 5111051Sandreas.hansson@arm.com * Cache definitions. 522810Srdreslin@umich.edu */ 532810Srdreslin@umich.edu 5411051Sandreas.hansson@arm.com#include "mem/cache/cache.hh" 552810Srdreslin@umich.edu 5611051Sandreas.hansson@arm.com#include "base/misc.hh" 5711051Sandreas.hansson@arm.com#include "base/types.hh" 5811051Sandreas.hansson@arm.com#include "debug/Cache.hh" 5911051Sandreas.hansson@arm.com#include "debug/CachePort.hh" 6011051Sandreas.hansson@arm.com#include "debug/CacheTags.hh" 6111051Sandreas.hansson@arm.com#include "debug/CacheVerbose.hh" 6211051Sandreas.hansson@arm.com#include "mem/cache/blk.hh" 6311051Sandreas.hansson@arm.com#include "mem/cache/mshr.hh" 6411051Sandreas.hansson@arm.com#include "mem/cache/prefetch/base.hh" 6511051Sandreas.hansson@arm.com#include "sim/sim_exit.hh" 6611053Sandreas.hansson@arm.com 6711053Sandreas.hansson@arm.comCache::Cache(const CacheParams *p) 6811051Sandreas.hansson@arm.com : BaseCache(p, p->system->cacheLineSize()), 6911051Sandreas.hansson@arm.com tags(p->tags), 7011051Sandreas.hansson@arm.com prefetcher(p->prefetcher), 7111051Sandreas.hansson@arm.com doFastWrites(true), 7211051Sandreas.hansson@arm.com prefetchOnAccess(p->prefetch_on_access), 7311051Sandreas.hansson@arm.com clusivity(p->clusivity), 7411051Sandreas.hansson@arm.com writebackClean(p->writeback_clean), 7511051Sandreas.hansson@arm.com tempBlockWriteback(nullptr), 7611051Sandreas.hansson@arm.com writebackTempBlockAtomicEvent(this, false, 7711051Sandreas.hansson@arm.com EventBase::Delayed_Writeback_Pri) 7811051Sandreas.hansson@arm.com{ 7911051Sandreas.hansson@arm.com tempBlock = new CacheBlk(); 8011051Sandreas.hansson@arm.com tempBlock->data = new uint8_t[blkSize]; 8111051Sandreas.hansson@arm.com 8211051Sandreas.hansson@arm.com cpuSidePort = new CpuSidePort(p->name + ".cpu_side", this, 8311051Sandreas.hansson@arm.com "CpuSidePort"); 8411051Sandreas.hansson@arm.com memSidePort = new MemSidePort(p->name + ".mem_side", this, 8511051Sandreas.hansson@arm.com "MemSidePort"); 8611051Sandreas.hansson@arm.com 8711051Sandreas.hansson@arm.com tags->setCache(this); 8811051Sandreas.hansson@arm.com if (prefetcher) 8911051Sandreas.hansson@arm.com prefetcher->setCache(this); 9011051Sandreas.hansson@arm.com} 9111051Sandreas.hansson@arm.com 9211051Sandreas.hansson@arm.comCache::~Cache() 9311051Sandreas.hansson@arm.com{ 9411051Sandreas.hansson@arm.com delete [] tempBlock->data; 9511051Sandreas.hansson@arm.com delete tempBlock; 9611051Sandreas.hansson@arm.com 9711051Sandreas.hansson@arm.com delete cpuSidePort; 9811051Sandreas.hansson@arm.com delete memSidePort; 9911051Sandreas.hansson@arm.com} 10011051Sandreas.hansson@arm.com 10111051Sandreas.hansson@arm.comvoid 10211051Sandreas.hansson@arm.comCache::regStats() 10311051Sandreas.hansson@arm.com{ 10411051Sandreas.hansson@arm.com BaseCache::regStats(); 10511051Sandreas.hansson@arm.com} 10611051Sandreas.hansson@arm.com 10711051Sandreas.hansson@arm.comvoid 10811051Sandreas.hansson@arm.comCache::cmpAndSwap(CacheBlk *blk, PacketPtr pkt) 10911051Sandreas.hansson@arm.com{ 11011051Sandreas.hansson@arm.com assert(pkt->isRequest()); 11111051Sandreas.hansson@arm.com 11211051Sandreas.hansson@arm.com uint64_t overwrite_val; 11311051Sandreas.hansson@arm.com bool overwrite_mem; 11411051Sandreas.hansson@arm.com uint64_t condition_val64; 11511051Sandreas.hansson@arm.com uint32_t condition_val32; 11611051Sandreas.hansson@arm.com 11711051Sandreas.hansson@arm.com int offset = tags->extractBlkOffset(pkt->getAddr()); 11811051Sandreas.hansson@arm.com uint8_t *blk_data = blk->data + offset; 11911051Sandreas.hansson@arm.com 12011051Sandreas.hansson@arm.com assert(sizeof(uint64_t) >= pkt->getSize()); 12111051Sandreas.hansson@arm.com 12211051Sandreas.hansson@arm.com overwrite_mem = true; 12311051Sandreas.hansson@arm.com // keep a copy of our possible write value, and copy what is at the 12411051Sandreas.hansson@arm.com // memory address into the packet 12511051Sandreas.hansson@arm.com pkt->writeData((uint8_t *)&overwrite_val); 12611051Sandreas.hansson@arm.com pkt->setData(blk_data); 12711051Sandreas.hansson@arm.com 12811051Sandreas.hansson@arm.com if (pkt->req->isCondSwap()) { 12911051Sandreas.hansson@arm.com if (pkt->getSize() == sizeof(uint64_t)) { 13011051Sandreas.hansson@arm.com condition_val64 = pkt->req->getExtraData(); 13111051Sandreas.hansson@arm.com overwrite_mem = !std::memcmp(&condition_val64, blk_data, 13211051Sandreas.hansson@arm.com sizeof(uint64_t)); 13311051Sandreas.hansson@arm.com } else if (pkt->getSize() == sizeof(uint32_t)) { 13411051Sandreas.hansson@arm.com condition_val32 = (uint32_t)pkt->req->getExtraData(); 13511051Sandreas.hansson@arm.com overwrite_mem = !std::memcmp(&condition_val32, blk_data, 13611051Sandreas.hansson@arm.com sizeof(uint32_t)); 13711051Sandreas.hansson@arm.com } else 13811051Sandreas.hansson@arm.com panic("Invalid size for conditional read/write\n"); 13911051Sandreas.hansson@arm.com } 14011051Sandreas.hansson@arm.com 14111051Sandreas.hansson@arm.com if (overwrite_mem) { 14211051Sandreas.hansson@arm.com std::memcpy(blk_data, &overwrite_val, pkt->getSize()); 14311051Sandreas.hansson@arm.com blk->status |= BlkDirty; 14411051Sandreas.hansson@arm.com } 14511051Sandreas.hansson@arm.com} 14611051Sandreas.hansson@arm.com 14711051Sandreas.hansson@arm.com 14811051Sandreas.hansson@arm.comvoid 14911051Sandreas.hansson@arm.comCache::satisfyRequest(PacketPtr pkt, CacheBlk *blk, 15011051Sandreas.hansson@arm.com bool deferred_response, bool pending_downgrade) 15111051Sandreas.hansson@arm.com{ 15211051Sandreas.hansson@arm.com assert(pkt->isRequest()); 15311051Sandreas.hansson@arm.com 15411051Sandreas.hansson@arm.com assert(blk && blk->isValid()); 15511051Sandreas.hansson@arm.com // Occasionally this is not true... if we are a lower-level cache 15611051Sandreas.hansson@arm.com // satisfying a string of Read and ReadEx requests from 15711051Sandreas.hansson@arm.com // upper-level caches, a Read will mark the block as shared but we 15811051Sandreas.hansson@arm.com // can satisfy a following ReadEx anyway since we can rely on the 15911051Sandreas.hansson@arm.com // Read requester(s) to have buffered the ReadEx snoop and to 16011051Sandreas.hansson@arm.com // invalidate their blocks after receiving them. 16111051Sandreas.hansson@arm.com // assert(!pkt->needsWritable() || blk->isWritable()); 16211051Sandreas.hansson@arm.com assert(pkt->getOffset(blkSize) + pkt->getSize() <= blkSize); 16311051Sandreas.hansson@arm.com 16411051Sandreas.hansson@arm.com // Check RMW operations first since both isRead() and 16511051Sandreas.hansson@arm.com // isWrite() will be true for them 16611051Sandreas.hansson@arm.com if (pkt->cmd == MemCmd::SwapReq) { 16711051Sandreas.hansson@arm.com cmpAndSwap(blk, pkt); 16811051Sandreas.hansson@arm.com } else if (pkt->isWrite()) { 16911051Sandreas.hansson@arm.com // we have the block in a writable state and can go ahead, 17011051Sandreas.hansson@arm.com // note that the line may be also be considered writable in 17111051Sandreas.hansson@arm.com // downstream caches along the path to memory, but always 17211051Sandreas.hansson@arm.com // Exclusive, and never Modified 17311051Sandreas.hansson@arm.com assert(blk->isWritable()); 17411051Sandreas.hansson@arm.com // Write or WriteLine at the first cache with block in writable state 17511051Sandreas.hansson@arm.com if (blk->checkWrite(pkt)) { 17611051Sandreas.hansson@arm.com pkt->writeDataToBlock(blk->data, blkSize); 17711051Sandreas.hansson@arm.com } 17811051Sandreas.hansson@arm.com // Always mark the line as dirty (and thus transition to the 17911051Sandreas.hansson@arm.com // Modified state) even if we are a failed StoreCond so we 18011051Sandreas.hansson@arm.com // supply data to any snoops that have appended themselves to 18111051Sandreas.hansson@arm.com // this cache before knowing the store will fail. 18211051Sandreas.hansson@arm.com blk->status |= BlkDirty; 18311051Sandreas.hansson@arm.com DPRINTF(CacheVerbose, "%s for %s (write)\n", __func__, pkt->print()); 18411051Sandreas.hansson@arm.com } else if (pkt->isRead()) { 18511051Sandreas.hansson@arm.com if (pkt->isLLSC()) { 18611051Sandreas.hansson@arm.com blk->trackLoadLocked(pkt); 18711051Sandreas.hansson@arm.com } 18811051Sandreas.hansson@arm.com 18911051Sandreas.hansson@arm.com // all read responses have a data payload 19011051Sandreas.hansson@arm.com assert(pkt->hasRespData()); 19111051Sandreas.hansson@arm.com pkt->setDataFromBlock(blk->data, blkSize); 19211051Sandreas.hansson@arm.com 19311051Sandreas.hansson@arm.com // determine if this read is from a (coherent) cache or not 19411051Sandreas.hansson@arm.com if (pkt->fromCache()) { 19511051Sandreas.hansson@arm.com assert(pkt->getSize() == blkSize); 19611051Sandreas.hansson@arm.com // special handling for coherent block requests from 19711051Sandreas.hansson@arm.com // upper-level caches 19811051Sandreas.hansson@arm.com if (pkt->needsWritable()) { 19911051Sandreas.hansson@arm.com // sanity check 20011051Sandreas.hansson@arm.com assert(pkt->cmd == MemCmd::ReadExReq || 20111051Sandreas.hansson@arm.com pkt->cmd == MemCmd::SCUpgradeFailReq); 20211051Sandreas.hansson@arm.com assert(!pkt->hasSharers()); 20311051Sandreas.hansson@arm.com 20411051Sandreas.hansson@arm.com // if we have a dirty copy, make sure the recipient 20511051Sandreas.hansson@arm.com // keeps it marked dirty (in the modified state) 20611051Sandreas.hansson@arm.com if (blk->isDirty()) { 20711051Sandreas.hansson@arm.com pkt->setCacheResponding(); 20811051Sandreas.hansson@arm.com blk->status &= ~BlkDirty; 20911051Sandreas.hansson@arm.com } 21011051Sandreas.hansson@arm.com } else if (blk->isWritable() && !pending_downgrade && 21111051Sandreas.hansson@arm.com !pkt->hasSharers() && 21211051Sandreas.hansson@arm.com pkt->cmd != MemCmd::ReadCleanReq) { 21311051Sandreas.hansson@arm.com // we can give the requester a writable copy on a read 21411051Sandreas.hansson@arm.com // request if: 21511051Sandreas.hansson@arm.com // - we have a writable copy at this level (& below) 21611051Sandreas.hansson@arm.com // - we don't have a pending snoop from below 21711051Sandreas.hansson@arm.com // signaling another read request 21811051Sandreas.hansson@arm.com // - no other cache above has a copy (otherwise it 21911051Sandreas.hansson@arm.com // would have set hasSharers flag when 22011051Sandreas.hansson@arm.com // snooping the packet) 22111051Sandreas.hansson@arm.com // - the read has explicitly asked for a clean 22211051Sandreas.hansson@arm.com // copy of the line 22311051Sandreas.hansson@arm.com if (blk->isDirty()) { 22411051Sandreas.hansson@arm.com // special considerations if we're owner: 22511051Sandreas.hansson@arm.com if (!deferred_response) { 22611051Sandreas.hansson@arm.com // respond with the line in Modified state 22711051Sandreas.hansson@arm.com // (cacheResponding set, hasSharers not set) 22811051Sandreas.hansson@arm.com pkt->setCacheResponding(); 22911051Sandreas.hansson@arm.com 23011051Sandreas.hansson@arm.com // if this cache is mostly inclusive, we 23111051Sandreas.hansson@arm.com // keep the block in the Exclusive state, 23211051Sandreas.hansson@arm.com // and pass it upwards as Modified 23311051Sandreas.hansson@arm.com // (writable and dirty), hence we have 23411051Sandreas.hansson@arm.com // multiple caches, all on the same path 23511051Sandreas.hansson@arm.com // towards memory, all considering the 23611051Sandreas.hansson@arm.com // same block writable, but only one 23711051Sandreas.hansson@arm.com // considering it Modified 23811051Sandreas.hansson@arm.com 23911051Sandreas.hansson@arm.com // we get away with multiple caches (on 24011051Sandreas.hansson@arm.com // the same path to memory) considering 24111051Sandreas.hansson@arm.com // the block writeable as we always enter 24211051Sandreas.hansson@arm.com // the cache hierarchy through a cache, 24311051Sandreas.hansson@arm.com // and first snoop upwards in all other 24411051Sandreas.hansson@arm.com // branches 24511051Sandreas.hansson@arm.com blk->status &= ~BlkDirty; 24611051Sandreas.hansson@arm.com } else { 24711051Sandreas.hansson@arm.com // if we're responding after our own miss, 24811051Sandreas.hansson@arm.com // there's a window where the recipient didn't 24911051Sandreas.hansson@arm.com // know it was getting ownership and may not 25011051Sandreas.hansson@arm.com // have responded to snoops correctly, so we 25111051Sandreas.hansson@arm.com // have to respond with a shared line 25211051Sandreas.hansson@arm.com pkt->setHasSharers(); 25311051Sandreas.hansson@arm.com } 25411051Sandreas.hansson@arm.com } 25511051Sandreas.hansson@arm.com } else { 25611051Sandreas.hansson@arm.com // otherwise only respond with a shared copy 25711051Sandreas.hansson@arm.com pkt->setHasSharers(); 25811051Sandreas.hansson@arm.com } 25911051Sandreas.hansson@arm.com } 26011051Sandreas.hansson@arm.com } else if (pkt->isUpgrade()) { 26111051Sandreas.hansson@arm.com // sanity check 26211051Sandreas.hansson@arm.com assert(!pkt->hasSharers()); 26311051Sandreas.hansson@arm.com 26411051Sandreas.hansson@arm.com if (blk->isDirty()) { 26511051Sandreas.hansson@arm.com // we were in the Owned state, and a cache above us that 26611051Sandreas.hansson@arm.com // has the line in Shared state needs to be made aware 26711051Sandreas.hansson@arm.com // that the data it already has is in fact dirty 26811051Sandreas.hansson@arm.com pkt->setCacheResponding(); 26911051Sandreas.hansson@arm.com blk->status &= ~BlkDirty; 27011051Sandreas.hansson@arm.com } 27111051Sandreas.hansson@arm.com } else { 27211051Sandreas.hansson@arm.com assert(pkt->isInvalidate()); 27311051Sandreas.hansson@arm.com invalidateBlock(blk); 27411051Sandreas.hansson@arm.com DPRINTF(CacheVerbose, "%s for %s (invalidation)\n", __func__, 27511051Sandreas.hansson@arm.com pkt->print()); 27611051Sandreas.hansson@arm.com } 27711051Sandreas.hansson@arm.com} 27811051Sandreas.hansson@arm.com 27911051Sandreas.hansson@arm.com///////////////////////////////////////////////////// 28011051Sandreas.hansson@arm.com// 28111051Sandreas.hansson@arm.com// Access path: requests coming in from the CPU side 28211051Sandreas.hansson@arm.com// 28311051Sandreas.hansson@arm.com///////////////////////////////////////////////////// 28411051Sandreas.hansson@arm.com 28511051Sandreas.hansson@arm.combool 28611051Sandreas.hansson@arm.comCache::access(PacketPtr pkt, CacheBlk *&blk, Cycles &lat, 28711051Sandreas.hansson@arm.com PacketList &writebacks) 28811051Sandreas.hansson@arm.com{ 28911051Sandreas.hansson@arm.com // sanity check 29011051Sandreas.hansson@arm.com assert(pkt->isRequest()); 29111051Sandreas.hansson@arm.com 29211051Sandreas.hansson@arm.com chatty_assert(!(isReadOnly && pkt->isWrite()), 29311051Sandreas.hansson@arm.com "Should never see a write in a read-only cache %s\n", 29411051Sandreas.hansson@arm.com name()); 29511051Sandreas.hansson@arm.com 29611051Sandreas.hansson@arm.com DPRINTF(CacheVerbose, "%s for %s\n", __func__, pkt->print()); 29711051Sandreas.hansson@arm.com 29811051Sandreas.hansson@arm.com if (pkt->req->isUncacheable()) { 29911051Sandreas.hansson@arm.com DPRINTF(Cache, "uncacheable: %s\n", pkt->print()); 30011051Sandreas.hansson@arm.com 30111051Sandreas.hansson@arm.com // flush and invalidate any existing block 30211051Sandreas.hansson@arm.com CacheBlk *old_blk(tags->findBlock(pkt->getAddr(), pkt->isSecure())); 30311051Sandreas.hansson@arm.com if (old_blk && old_blk->isValid()) { 30411051Sandreas.hansson@arm.com if (old_blk->isDirty() || writebackClean) 30511051Sandreas.hansson@arm.com writebacks.push_back(writebackBlk(old_blk)); 30611051Sandreas.hansson@arm.com else 30711051Sandreas.hansson@arm.com writebacks.push_back(cleanEvictBlk(old_blk)); 30811051Sandreas.hansson@arm.com invalidateBlock(old_blk); 30911051Sandreas.hansson@arm.com } 31011051Sandreas.hansson@arm.com 31111051Sandreas.hansson@arm.com blk = nullptr; 31211051Sandreas.hansson@arm.com // lookupLatency is the latency in case the request is uncacheable. 31311051Sandreas.hansson@arm.com lat = lookupLatency; 31411051Sandreas.hansson@arm.com return false; 31511051Sandreas.hansson@arm.com } 31611051Sandreas.hansson@arm.com 31711051Sandreas.hansson@arm.com // Here lat is the value passed as parameter to accessBlock() function 31811051Sandreas.hansson@arm.com // that can modify its value. 31911051Sandreas.hansson@arm.com blk = tags->accessBlock(pkt->getAddr(), pkt->isSecure(), lat); 32011051Sandreas.hansson@arm.com 32111051Sandreas.hansson@arm.com DPRINTF(Cache, "%s %s\n", pkt->print(), 32211051Sandreas.hansson@arm.com blk ? "hit " + blk->print() : "miss"); 32311051Sandreas.hansson@arm.com 32411051Sandreas.hansson@arm.com 32511051Sandreas.hansson@arm.com if (pkt->isEviction()) { 32611051Sandreas.hansson@arm.com // We check for presence of block in above caches before issuing 32711051Sandreas.hansson@arm.com // Writeback or CleanEvict to write buffer. Therefore the only 32811051Sandreas.hansson@arm.com // possible cases can be of a CleanEvict packet coming from above 32911051Sandreas.hansson@arm.com // encountering a Writeback generated in this cache peer cache and 33011051Sandreas.hansson@arm.com // waiting in the write buffer. Cases of upper level peer caches 33111051Sandreas.hansson@arm.com // generating CleanEvict and Writeback or simply CleanEvict and 33211051Sandreas.hansson@arm.com // CleanEvict almost simultaneously will be caught by snoops sent out 33311051Sandreas.hansson@arm.com // by crossbar. 33411051Sandreas.hansson@arm.com WriteQueueEntry *wb_entry = writeBuffer.findMatch(pkt->getAddr(), 33511051Sandreas.hansson@arm.com pkt->isSecure()); 33611051Sandreas.hansson@arm.com if (wb_entry) { 33711051Sandreas.hansson@arm.com assert(wb_entry->getNumTargets() == 1); 33811051Sandreas.hansson@arm.com PacketPtr wbPkt = wb_entry->getTarget()->pkt; 33911051Sandreas.hansson@arm.com assert(wbPkt->isWriteback()); 34011051Sandreas.hansson@arm.com 34111051Sandreas.hansson@arm.com if (pkt->isCleanEviction()) { 34211051Sandreas.hansson@arm.com // The CleanEvict and WritebackClean snoops into other 34311051Sandreas.hansson@arm.com // peer caches of the same level while traversing the 34411051Sandreas.hansson@arm.com // crossbar. If a copy of the block is found, the 34511051Sandreas.hansson@arm.com // packet is deleted in the crossbar. Hence, none of 34611051Sandreas.hansson@arm.com // the other upper level caches connected to this 34711051Sandreas.hansson@arm.com // cache have the block, so we can clear the 34811051Sandreas.hansson@arm.com // BLOCK_CACHED flag in the Writeback if set and 34911051Sandreas.hansson@arm.com // discard the CleanEvict by returning true. 35011051Sandreas.hansson@arm.com wbPkt->clearBlockCached(); 35111051Sandreas.hansson@arm.com return true; 35211051Sandreas.hansson@arm.com } else { 35311051Sandreas.hansson@arm.com assert(pkt->cmd == MemCmd::WritebackDirty); 35411051Sandreas.hansson@arm.com // Dirty writeback from above trumps our clean 35511051Sandreas.hansson@arm.com // writeback... discard here 35611051Sandreas.hansson@arm.com // Note: markInService will remove entry from writeback buffer. 35711051Sandreas.hansson@arm.com markInService(wb_entry); 35811051Sandreas.hansson@arm.com delete wbPkt; 35911051Sandreas.hansson@arm.com } 36011051Sandreas.hansson@arm.com } 36111051Sandreas.hansson@arm.com } 36211051Sandreas.hansson@arm.com 36311051Sandreas.hansson@arm.com // Writeback handling is special case. We can write the block into 36411051Sandreas.hansson@arm.com // the cache without having a writeable copy (or any copy at all). 36511051Sandreas.hansson@arm.com if (pkt->isWriteback()) { 36611051Sandreas.hansson@arm.com assert(blkSize == pkt->getSize()); 36711051Sandreas.hansson@arm.com 36811051Sandreas.hansson@arm.com // we could get a clean writeback while we are having 36911051Sandreas.hansson@arm.com // outstanding accesses to a block, do the simple thing for 37011051Sandreas.hansson@arm.com // now and drop the clean writeback so that we do not upset 37111051Sandreas.hansson@arm.com // any ordering/decisions about ownership already taken 37211051Sandreas.hansson@arm.com if (pkt->cmd == MemCmd::WritebackClean && 37311051Sandreas.hansson@arm.com mshrQueue.findMatch(pkt->getAddr(), pkt->isSecure())) { 37411051Sandreas.hansson@arm.com DPRINTF(Cache, "Clean writeback %#llx to block with MSHR, " 37511051Sandreas.hansson@arm.com "dropping\n", pkt->getAddr()); 37611051Sandreas.hansson@arm.com return true; 37711051Sandreas.hansson@arm.com } 37811051Sandreas.hansson@arm.com 37911051Sandreas.hansson@arm.com if (blk == nullptr) { 38011051Sandreas.hansson@arm.com // need to do a replacement 38111051Sandreas.hansson@arm.com blk = allocateBlock(pkt->getAddr(), pkt->isSecure(), writebacks); 38211051Sandreas.hansson@arm.com if (blk == nullptr) { 38311051Sandreas.hansson@arm.com // no replaceable block available: give up, fwd to next level. 38411051Sandreas.hansson@arm.com incMissCount(pkt); 38511051Sandreas.hansson@arm.com return false; 38611051Sandreas.hansson@arm.com } 38711051Sandreas.hansson@arm.com tags->insertBlock(pkt, blk); 38811051Sandreas.hansson@arm.com 38911051Sandreas.hansson@arm.com blk->status = (BlkValid | BlkReadable); 39011051Sandreas.hansson@arm.com if (pkt->isSecure()) { 39111051Sandreas.hansson@arm.com blk->status |= BlkSecure; 39211051Sandreas.hansson@arm.com } 39311051Sandreas.hansson@arm.com } 39411051Sandreas.hansson@arm.com // only mark the block dirty if we got a writeback command, 39511051Sandreas.hansson@arm.com // and leave it as is for a clean writeback 39611051Sandreas.hansson@arm.com if (pkt->cmd == MemCmd::WritebackDirty) { 39711051Sandreas.hansson@arm.com blk->status |= BlkDirty; 39811051Sandreas.hansson@arm.com } 39911051Sandreas.hansson@arm.com // if the packet does not have sharers, it is passing 40011051Sandreas.hansson@arm.com // writable, and we got the writeback in Modified or Exclusive 40111051Sandreas.hansson@arm.com // state, if not we are in the Owned or Shared state 40211051Sandreas.hansson@arm.com if (!pkt->hasSharers()) { 40311051Sandreas.hansson@arm.com blk->status |= BlkWritable; 40411051Sandreas.hansson@arm.com } 40511051Sandreas.hansson@arm.com // nothing else to do; writeback doesn't expect response 40611051Sandreas.hansson@arm.com assert(!pkt->needsResponse()); 40711051Sandreas.hansson@arm.com std::memcpy(blk->data, pkt->getConstPtr<uint8_t>(), blkSize); 40811051Sandreas.hansson@arm.com DPRINTF(Cache, "%s new state is %s\n", __func__, blk->print()); 40911051Sandreas.hansson@arm.com incHitCount(pkt); 41011051Sandreas.hansson@arm.com return true; 41111051Sandreas.hansson@arm.com } else if (pkt->cmd == MemCmd::CleanEvict) { 41211051Sandreas.hansson@arm.com if (blk != nullptr) { 41311051Sandreas.hansson@arm.com // Found the block in the tags, need to stop CleanEvict from 41411051Sandreas.hansson@arm.com // propagating further down the hierarchy. Returning true will 41511051Sandreas.hansson@arm.com // treat the CleanEvict like a satisfied write request and delete 41611051Sandreas.hansson@arm.com // it. 41711051Sandreas.hansson@arm.com return true; 41811051Sandreas.hansson@arm.com } 41911051Sandreas.hansson@arm.com // We didn't find the block here, propagate the CleanEvict further 42011051Sandreas.hansson@arm.com // down the memory hierarchy. Returning false will treat the CleanEvict 42111051Sandreas.hansson@arm.com // like a Writeback which could not find a replaceable block so has to 42211051Sandreas.hansson@arm.com // go to next level. 42311051Sandreas.hansson@arm.com return false; 42411051Sandreas.hansson@arm.com } else if (blk && (pkt->needsWritable() ? blk->isWritable() : 42511051Sandreas.hansson@arm.com blk->isReadable())) { 42611051Sandreas.hansson@arm.com // OK to satisfy access 42711051Sandreas.hansson@arm.com incHitCount(pkt); 42811051Sandreas.hansson@arm.com satisfyRequest(pkt, blk); 42911051Sandreas.hansson@arm.com maintainClusivity(pkt->fromCache(), blk); 43011051Sandreas.hansson@arm.com 43111051Sandreas.hansson@arm.com return true; 43211051Sandreas.hansson@arm.com } 43311051Sandreas.hansson@arm.com 43411051Sandreas.hansson@arm.com // Can't satisfy access normally... either no block (blk == nullptr) 43511051Sandreas.hansson@arm.com // or have block but need writable 43611051Sandreas.hansson@arm.com 43711051Sandreas.hansson@arm.com incMissCount(pkt); 43811051Sandreas.hansson@arm.com 43911051Sandreas.hansson@arm.com if (blk == nullptr && pkt->isLLSC() && pkt->isWrite()) { 44011051Sandreas.hansson@arm.com // complete miss on store conditional... just give up now 44111051Sandreas.hansson@arm.com pkt->req->setExtraData(0); 44211051Sandreas.hansson@arm.com return true; 44311051Sandreas.hansson@arm.com } 44411051Sandreas.hansson@arm.com 44511051Sandreas.hansson@arm.com return false; 44611051Sandreas.hansson@arm.com} 44711051Sandreas.hansson@arm.com 44811051Sandreas.hansson@arm.comvoid 44911051Sandreas.hansson@arm.comCache::maintainClusivity(bool from_cache, CacheBlk *blk) 45011051Sandreas.hansson@arm.com{ 45111051Sandreas.hansson@arm.com if (from_cache && blk && blk->isValid() && !blk->isDirty() && 45211051Sandreas.hansson@arm.com clusivity == Enums::mostly_excl) { 45311051Sandreas.hansson@arm.com // if we have responded to a cache, and our block is still 45411051Sandreas.hansson@arm.com // valid, but not dirty, and this cache is mostly exclusive 45511051Sandreas.hansson@arm.com // with respect to the cache above, drop the block 45611051Sandreas.hansson@arm.com invalidateBlock(blk); 45711051Sandreas.hansson@arm.com } 45811051Sandreas.hansson@arm.com} 45911051Sandreas.hansson@arm.com 46011051Sandreas.hansson@arm.comvoid 46111051Sandreas.hansson@arm.comCache::doWritebacks(PacketList& writebacks, Tick forward_time) 46211051Sandreas.hansson@arm.com{ 46311051Sandreas.hansson@arm.com while (!writebacks.empty()) { 46411051Sandreas.hansson@arm.com PacketPtr wbPkt = writebacks.front(); 46511051Sandreas.hansson@arm.com // We use forwardLatency here because we are copying writebacks to 46611051Sandreas.hansson@arm.com // write buffer. Call isCachedAbove for both Writebacks and 46711051Sandreas.hansson@arm.com // CleanEvicts. If isCachedAbove returns true we set BLOCK_CACHED flag 46811051Sandreas.hansson@arm.com // in Writebacks and discard CleanEvicts. 46911051Sandreas.hansson@arm.com if (isCachedAbove(wbPkt)) { 47011051Sandreas.hansson@arm.com if (wbPkt->cmd == MemCmd::CleanEvict) { 47111051Sandreas.hansson@arm.com // Delete CleanEvict because cached copies exist above. The 47211051Sandreas.hansson@arm.com // packet destructor will delete the request object because 47311051Sandreas.hansson@arm.com // this is a non-snoop request packet which does not require a 47411051Sandreas.hansson@arm.com // response. 47511051Sandreas.hansson@arm.com delete wbPkt; 47611051Sandreas.hansson@arm.com } else if (wbPkt->cmd == MemCmd::WritebackClean) { 47711051Sandreas.hansson@arm.com // clean writeback, do not send since the block is 47811051Sandreas.hansson@arm.com // still cached above 47911051Sandreas.hansson@arm.com assert(writebackClean); 48011051Sandreas.hansson@arm.com delete wbPkt; 48111051Sandreas.hansson@arm.com } else { 48211051Sandreas.hansson@arm.com assert(wbPkt->cmd == MemCmd::WritebackDirty); 48311051Sandreas.hansson@arm.com // Set BLOCK_CACHED flag in Writeback and send below, so that 48411051Sandreas.hansson@arm.com // the Writeback does not reset the bit corresponding to this 48511051Sandreas.hansson@arm.com // address in the snoop filter below. 48611051Sandreas.hansson@arm.com wbPkt->setBlockCached(); 48711051Sandreas.hansson@arm.com allocateWriteBuffer(wbPkt, forward_time); 48811051Sandreas.hansson@arm.com } 48911051Sandreas.hansson@arm.com } else { 49011051Sandreas.hansson@arm.com // If the block is not cached above, send packet below. Both 49111051Sandreas.hansson@arm.com // CleanEvict and Writeback with BLOCK_CACHED flag cleared will 49211051Sandreas.hansson@arm.com // reset the bit corresponding to this address in the snoop filter 49311051Sandreas.hansson@arm.com // below. 49411051Sandreas.hansson@arm.com allocateWriteBuffer(wbPkt, forward_time); 49511051Sandreas.hansson@arm.com } 49611051Sandreas.hansson@arm.com writebacks.pop_front(); 49711051Sandreas.hansson@arm.com } 49811051Sandreas.hansson@arm.com} 49911051Sandreas.hansson@arm.com 50011051Sandreas.hansson@arm.comvoid 50111051Sandreas.hansson@arm.comCache::doWritebacksAtomic(PacketList& writebacks) 50211051Sandreas.hansson@arm.com{ 50311051Sandreas.hansson@arm.com while (!writebacks.empty()) { 50411051Sandreas.hansson@arm.com PacketPtr wbPkt = writebacks.front(); 50511051Sandreas.hansson@arm.com // Call isCachedAbove for both Writebacks and CleanEvicts. If 50611051Sandreas.hansson@arm.com // isCachedAbove returns true we set BLOCK_CACHED flag in Writebacks 50711051Sandreas.hansson@arm.com // and discard CleanEvicts. 50811051Sandreas.hansson@arm.com if (isCachedAbove(wbPkt, false)) { 50911051Sandreas.hansson@arm.com if (wbPkt->cmd == MemCmd::WritebackDirty) { 51011051Sandreas.hansson@arm.com // Set BLOCK_CACHED flag in Writeback and send below, 51111051Sandreas.hansson@arm.com // so that the Writeback does not reset the bit 51211051Sandreas.hansson@arm.com // corresponding to this address in the snoop filter 51311051Sandreas.hansson@arm.com // below. We can discard CleanEvicts because cached 51411051Sandreas.hansson@arm.com // copies exist above. Atomic mode isCachedAbove 51511051Sandreas.hansson@arm.com // modifies packet to set BLOCK_CACHED flag 51611051Sandreas.hansson@arm.com memSidePort->sendAtomic(wbPkt); 51711051Sandreas.hansson@arm.com } 51811051Sandreas.hansson@arm.com } else { 51911051Sandreas.hansson@arm.com // If the block is not cached above, send packet below. Both 52011051Sandreas.hansson@arm.com // CleanEvict and Writeback with BLOCK_CACHED flag cleared will 52111051Sandreas.hansson@arm.com // reset the bit corresponding to this address in the snoop filter 52211051Sandreas.hansson@arm.com // below. 52311051Sandreas.hansson@arm.com memSidePort->sendAtomic(wbPkt); 52411051Sandreas.hansson@arm.com } 52511051Sandreas.hansson@arm.com writebacks.pop_front(); 52611051Sandreas.hansson@arm.com // In case of CleanEvicts, the packet destructor will delete the 52711051Sandreas.hansson@arm.com // request object because this is a non-snoop request packet which 52811051Sandreas.hansson@arm.com // does not require a response. 52911051Sandreas.hansson@arm.com delete wbPkt; 53011051Sandreas.hansson@arm.com } 53111051Sandreas.hansson@arm.com} 53211051Sandreas.hansson@arm.com 53311051Sandreas.hansson@arm.com 53411051Sandreas.hansson@arm.comvoid 53511051Sandreas.hansson@arm.comCache::recvTimingSnoopResp(PacketPtr pkt) 53611051Sandreas.hansson@arm.com{ 53711051Sandreas.hansson@arm.com DPRINTF(Cache, "%s for %s\n", __func__, pkt->print()); 53811051Sandreas.hansson@arm.com 53911051Sandreas.hansson@arm.com assert(pkt->isResponse()); 54011051Sandreas.hansson@arm.com assert(!system->bypassCaches()); 54111051Sandreas.hansson@arm.com 54211051Sandreas.hansson@arm.com // determine if the response is from a snoop request we created 54311051Sandreas.hansson@arm.com // (in which case it should be in the outstandingSnoop), or if we 54411051Sandreas.hansson@arm.com // merely forwarded someone else's snoop request 54511051Sandreas.hansson@arm.com const bool forwardAsSnoop = outstandingSnoop.find(pkt->req) == 54611051Sandreas.hansson@arm.com outstandingSnoop.end(); 54711051Sandreas.hansson@arm.com 54811051Sandreas.hansson@arm.com if (!forwardAsSnoop) { 54911051Sandreas.hansson@arm.com // the packet came from this cache, so sink it here and do not 55011051Sandreas.hansson@arm.com // forward it 55111051Sandreas.hansson@arm.com assert(pkt->cmd == MemCmd::HardPFResp); 55211051Sandreas.hansson@arm.com 55311051Sandreas.hansson@arm.com outstandingSnoop.erase(pkt->req); 55411051Sandreas.hansson@arm.com 55511051Sandreas.hansson@arm.com DPRINTF(Cache, "Got prefetch response from above for addr " 55611051Sandreas.hansson@arm.com "%#llx (%s)\n", pkt->getAddr(), pkt->isSecure() ? "s" : "ns"); 55711051Sandreas.hansson@arm.com recvTimingResp(pkt); 55811051Sandreas.hansson@arm.com return; 55911051Sandreas.hansson@arm.com } 56011051Sandreas.hansson@arm.com 56111051Sandreas.hansson@arm.com // forwardLatency is set here because there is a response from an 56211051Sandreas.hansson@arm.com // upper level cache. 56311051Sandreas.hansson@arm.com // To pay the delay that occurs if the packet comes from the bus, 56411051Sandreas.hansson@arm.com // we charge also headerDelay. 56511051Sandreas.hansson@arm.com Tick snoop_resp_time = clockEdge(forwardLatency) + pkt->headerDelay; 56611051Sandreas.hansson@arm.com // Reset the timing of the packet. 56711051Sandreas.hansson@arm.com pkt->headerDelay = pkt->payloadDelay = 0; 56811051Sandreas.hansson@arm.com memSidePort->schedTimingSnoopResp(pkt, snoop_resp_time); 56911051Sandreas.hansson@arm.com} 57011051Sandreas.hansson@arm.com 57111051Sandreas.hansson@arm.comvoid 57211051Sandreas.hansson@arm.comCache::promoteWholeLineWrites(PacketPtr pkt) 57311051Sandreas.hansson@arm.com{ 57411051Sandreas.hansson@arm.com // Cache line clearing instructions 57511051Sandreas.hansson@arm.com if (doFastWrites && (pkt->cmd == MemCmd::WriteReq) && 57611051Sandreas.hansson@arm.com (pkt->getSize() == blkSize) && (pkt->getOffset(blkSize) == 0)) { 57711051Sandreas.hansson@arm.com pkt->cmd = MemCmd::WriteLineReq; 57811051Sandreas.hansson@arm.com DPRINTF(Cache, "packet promoted from Write to WriteLineReq\n"); 57911051Sandreas.hansson@arm.com } 58011051Sandreas.hansson@arm.com} 58111051Sandreas.hansson@arm.com 58211051Sandreas.hansson@arm.combool 58311051Sandreas.hansson@arm.comCache::recvTimingReq(PacketPtr pkt) 58411051Sandreas.hansson@arm.com{ 58511051Sandreas.hansson@arm.com DPRINTF(CacheTags, "%s tags:\n%s\n", __func__, tags->print()); 58611051Sandreas.hansson@arm.com 58711051Sandreas.hansson@arm.com assert(pkt->isRequest()); 58811051Sandreas.hansson@arm.com 58911051Sandreas.hansson@arm.com // Just forward the packet if caches are disabled. 59011051Sandreas.hansson@arm.com if (system->bypassCaches()) { 59111051Sandreas.hansson@arm.com // @todo This should really enqueue the packet rather 59211051Sandreas.hansson@arm.com bool M5_VAR_USED success = memSidePort->sendTimingReq(pkt); 59311051Sandreas.hansson@arm.com assert(success); 59411051Sandreas.hansson@arm.com return true; 59511051Sandreas.hansson@arm.com } 59611051Sandreas.hansson@arm.com 59711051Sandreas.hansson@arm.com promoteWholeLineWrites(pkt); 59811051Sandreas.hansson@arm.com 59911051Sandreas.hansson@arm.com if (pkt->cacheResponding()) { 60011051Sandreas.hansson@arm.com // a cache above us (but not where the packet came from) is 60111051Sandreas.hansson@arm.com // responding to the request, in other words it has the line 60211051Sandreas.hansson@arm.com // in Modified or Owned state 60311051Sandreas.hansson@arm.com DPRINTF(Cache, "Cache above responding to %s: not responding\n", 60411051Sandreas.hansson@arm.com pkt->print()); 60511051Sandreas.hansson@arm.com 60611051Sandreas.hansson@arm.com // if the packet needs the block to be writable, and the cache 60711051Sandreas.hansson@arm.com // that has promised to respond (setting the cache responding 60811051Sandreas.hansson@arm.com // flag) is not providing writable (it is in Owned rather than 60911051Sandreas.hansson@arm.com // the Modified state), we know that there may be other Shared 61011051Sandreas.hansson@arm.com // copies in the system; go out and invalidate them all 61111051Sandreas.hansson@arm.com assert(pkt->needsWritable() && !pkt->responderHadWritable()); 61211051Sandreas.hansson@arm.com 61311051Sandreas.hansson@arm.com // an upstream cache that had the line in Owned state 61411051Sandreas.hansson@arm.com // (dirty, but not writable), is responding and thus 61511051Sandreas.hansson@arm.com // transferring the dirty line from one branch of the 61611051Sandreas.hansson@arm.com // cache hierarchy to another 61711051Sandreas.hansson@arm.com 61811051Sandreas.hansson@arm.com // send out an express snoop and invalidate all other 61911051Sandreas.hansson@arm.com // copies (snooping a packet that needs writable is the 62011051Sandreas.hansson@arm.com // same as an invalidation), thus turning the Owned line 62111051Sandreas.hansson@arm.com // into a Modified line, note that we don't invalidate the 62211051Sandreas.hansson@arm.com // block in the current cache or any other cache on the 62311051Sandreas.hansson@arm.com // path to memory 62411051Sandreas.hansson@arm.com 62511051Sandreas.hansson@arm.com // create a downstream express snoop with cleared packet 62611051Sandreas.hansson@arm.com // flags, there is no need to allocate any data as the 62711051Sandreas.hansson@arm.com // packet is merely used to co-ordinate state transitions 62811051Sandreas.hansson@arm.com Packet *snoop_pkt = new Packet(pkt, true, false); 62911051Sandreas.hansson@arm.com 63011051Sandreas.hansson@arm.com // also reset the bus time that the original packet has 63111051Sandreas.hansson@arm.com // not yet paid for 63211051Sandreas.hansson@arm.com snoop_pkt->headerDelay = snoop_pkt->payloadDelay = 0; 63311051Sandreas.hansson@arm.com 63411051Sandreas.hansson@arm.com // make this an instantaneous express snoop, and let the 63511051Sandreas.hansson@arm.com // other caches in the system know that the another cache 63611051Sandreas.hansson@arm.com // is responding, because we have found the authorative 63711051Sandreas.hansson@arm.com // copy (Modified or Owned) that will supply the right 63811051Sandreas.hansson@arm.com // data 63911051Sandreas.hansson@arm.com snoop_pkt->setExpressSnoop(); 64011051Sandreas.hansson@arm.com snoop_pkt->setCacheResponding(); 64111051Sandreas.hansson@arm.com 64211051Sandreas.hansson@arm.com // this express snoop travels towards the memory, and at 64311051Sandreas.hansson@arm.com // every crossbar it is snooped upwards thus reaching 64411051Sandreas.hansson@arm.com // every cache in the system 64511051Sandreas.hansson@arm.com bool M5_VAR_USED success = memSidePort->sendTimingReq(snoop_pkt); 64611051Sandreas.hansson@arm.com // express snoops always succeed 64711051Sandreas.hansson@arm.com assert(success); 64811051Sandreas.hansson@arm.com 64911051Sandreas.hansson@arm.com // main memory will delete the snoop packet 65011051Sandreas.hansson@arm.com 65111051Sandreas.hansson@arm.com // queue for deletion, as opposed to immediate deletion, as 65211051Sandreas.hansson@arm.com // the sending cache is still relying on the packet 65311051Sandreas.hansson@arm.com pendingDelete.reset(pkt); 65411051Sandreas.hansson@arm.com 65511051Sandreas.hansson@arm.com // no need to take any further action in this particular cache 65611051Sandreas.hansson@arm.com // as an upstram cache has already committed to responding, 65711051Sandreas.hansson@arm.com // and we have already sent out any express snoops in the 65811051Sandreas.hansson@arm.com // section above to ensure all other copies in the system are 65911051Sandreas.hansson@arm.com // invalidated 66011051Sandreas.hansson@arm.com return true; 66111051Sandreas.hansson@arm.com } 66211051Sandreas.hansson@arm.com 66311051Sandreas.hansson@arm.com // anything that is merely forwarded pays for the forward latency and 66411051Sandreas.hansson@arm.com // the delay provided by the crossbar 66511051Sandreas.hansson@arm.com Tick forward_time = clockEdge(forwardLatency) + pkt->headerDelay; 66611051Sandreas.hansson@arm.com 66711051Sandreas.hansson@arm.com // We use lookupLatency here because it is used to specify the latency 66811051Sandreas.hansson@arm.com // to access. 66911051Sandreas.hansson@arm.com Cycles lat = lookupLatency; 67011051Sandreas.hansson@arm.com CacheBlk *blk = nullptr; 67111051Sandreas.hansson@arm.com bool satisfied = false; 67211051Sandreas.hansson@arm.com { 67311051Sandreas.hansson@arm.com PacketList writebacks; 67411051Sandreas.hansson@arm.com // Note that lat is passed by reference here. The function 67511051Sandreas.hansson@arm.com // access() calls accessBlock() which can modify lat value. 67611051Sandreas.hansson@arm.com satisfied = access(pkt, blk, lat, writebacks); 67711051Sandreas.hansson@arm.com 67811051Sandreas.hansson@arm.com // copy writebacks to write buffer here to ensure they logically 67911051Sandreas.hansson@arm.com // proceed anything happening below 68011051Sandreas.hansson@arm.com doWritebacks(writebacks, forward_time); 68111051Sandreas.hansson@arm.com } 68211051Sandreas.hansson@arm.com 68311051Sandreas.hansson@arm.com // Here we charge the headerDelay that takes into account the latencies 68411051Sandreas.hansson@arm.com // of the bus, if the packet comes from it. 68511051Sandreas.hansson@arm.com // The latency charged it is just lat that is the value of lookupLatency 68611051Sandreas.hansson@arm.com // modified by access() function, or if not just lookupLatency. 68711051Sandreas.hansson@arm.com // In case of a hit we are neglecting response latency. 68811051Sandreas.hansson@arm.com // In case of a miss we are neglecting forward latency. 68911051Sandreas.hansson@arm.com Tick request_time = clockEdge(lat) + pkt->headerDelay; 69011051Sandreas.hansson@arm.com // Here we reset the timing of the packet. 69111051Sandreas.hansson@arm.com pkt->headerDelay = pkt->payloadDelay = 0; 69211051Sandreas.hansson@arm.com 69311051Sandreas.hansson@arm.com // track time of availability of next prefetch, if any 69411051Sandreas.hansson@arm.com Tick next_pf_time = MaxTick; 69511051Sandreas.hansson@arm.com 69611051Sandreas.hansson@arm.com bool needsResponse = pkt->needsResponse(); 69711051Sandreas.hansson@arm.com 69811051Sandreas.hansson@arm.com if (satisfied) { 69911051Sandreas.hansson@arm.com // should never be satisfying an uncacheable access as we 70011051Sandreas.hansson@arm.com // flush and invalidate any existing block as part of the 70111051Sandreas.hansson@arm.com // lookup 70211051Sandreas.hansson@arm.com assert(!pkt->req->isUncacheable()); 70311051Sandreas.hansson@arm.com 70411051Sandreas.hansson@arm.com // hit (for all other request types) 70511051Sandreas.hansson@arm.com 70611051Sandreas.hansson@arm.com if (prefetcher && (prefetchOnAccess || 70711051Sandreas.hansson@arm.com (blk && blk->wasPrefetched()))) { 70811051Sandreas.hansson@arm.com if (blk) 70911051Sandreas.hansson@arm.com blk->status &= ~BlkHWPrefetched; 71011051Sandreas.hansson@arm.com 71111051Sandreas.hansson@arm.com // Don't notify on SWPrefetch 71211051Sandreas.hansson@arm.com if (!pkt->cmd.isSWPrefetch()) 71311051Sandreas.hansson@arm.com next_pf_time = prefetcher->notify(pkt); 71411051Sandreas.hansson@arm.com } 71511051Sandreas.hansson@arm.com 71611051Sandreas.hansson@arm.com if (needsResponse) { 71711051Sandreas.hansson@arm.com pkt->makeTimingResponse(); 71811051Sandreas.hansson@arm.com // @todo: Make someone pay for this 71911051Sandreas.hansson@arm.com pkt->headerDelay = pkt->payloadDelay = 0; 72011051Sandreas.hansson@arm.com 72111051Sandreas.hansson@arm.com // In this case we are considering request_time that takes 72211051Sandreas.hansson@arm.com // into account the delay of the xbar, if any, and just 72311051Sandreas.hansson@arm.com // lat, neglecting responseLatency, modelling hit latency 72411051Sandreas.hansson@arm.com // just as lookupLatency or or the value of lat overriden 72511051Sandreas.hansson@arm.com // by access(), that calls accessBlock() function. 72611051Sandreas.hansson@arm.com cpuSidePort->schedTimingResp(pkt, request_time, true); 72711051Sandreas.hansson@arm.com } else { 72811051Sandreas.hansson@arm.com DPRINTF(Cache, "%s satisfied %s, no response needed\n", __func__, 72911051Sandreas.hansson@arm.com pkt->print()); 73011051Sandreas.hansson@arm.com 73111051Sandreas.hansson@arm.com // queue the packet for deletion, as the sending cache is 73211051Sandreas.hansson@arm.com // still relying on it; if the block is found in access(), 73311051Sandreas.hansson@arm.com // CleanEvict and Writeback messages will be deleted 73411051Sandreas.hansson@arm.com // here as well 73511051Sandreas.hansson@arm.com pendingDelete.reset(pkt); 73611051Sandreas.hansson@arm.com } 73711051Sandreas.hansson@arm.com } else { 73811051Sandreas.hansson@arm.com // miss 73911051Sandreas.hansson@arm.com 74011051Sandreas.hansson@arm.com Addr blk_addr = pkt->getBlockAddr(blkSize); 74111051Sandreas.hansson@arm.com 74211051Sandreas.hansson@arm.com // ignore any existing MSHR if we are dealing with an 74311051Sandreas.hansson@arm.com // uncacheable request 74411051Sandreas.hansson@arm.com MSHR *mshr = pkt->req->isUncacheable() ? nullptr : 74511051Sandreas.hansson@arm.com mshrQueue.findMatch(blk_addr, pkt->isSecure()); 74611051Sandreas.hansson@arm.com 74711051Sandreas.hansson@arm.com // Software prefetch handling: 74811051Sandreas.hansson@arm.com // To keep the core from waiting on data it won't look at 74911051Sandreas.hansson@arm.com // anyway, send back a response with dummy data. Miss handling 75011051Sandreas.hansson@arm.com // will continue asynchronously. Unfortunately, the core will 75111051Sandreas.hansson@arm.com // insist upon freeing original Packet/Request, so we have to 75211051Sandreas.hansson@arm.com // create a new pair with a different lifecycle. Note that this 75311051Sandreas.hansson@arm.com // processing happens before any MSHR munging on the behalf of 75411051Sandreas.hansson@arm.com // this request because this new Request will be the one stored 75511051Sandreas.hansson@arm.com // into the MSHRs, not the original. 75611051Sandreas.hansson@arm.com if (pkt->cmd.isSWPrefetch()) { 75711051Sandreas.hansson@arm.com assert(needsResponse); 75811051Sandreas.hansson@arm.com assert(pkt->req->hasPaddr()); 75911051Sandreas.hansson@arm.com assert(!pkt->req->isUncacheable()); 76011051Sandreas.hansson@arm.com 76111051Sandreas.hansson@arm.com // There's no reason to add a prefetch as an additional target 76211051Sandreas.hansson@arm.com // to an existing MSHR. If an outstanding request is already 76311051Sandreas.hansson@arm.com // in progress, there is nothing for the prefetch to do. 76411051Sandreas.hansson@arm.com // If this is the case, we don't even create a request at all. 76511051Sandreas.hansson@arm.com PacketPtr pf = nullptr; 76611051Sandreas.hansson@arm.com 76711051Sandreas.hansson@arm.com if (!mshr) { 76811051Sandreas.hansson@arm.com // copy the request and create a new SoftPFReq packet 76911051Sandreas.hansson@arm.com RequestPtr req = new Request(pkt->req->getPaddr(), 77011051Sandreas.hansson@arm.com pkt->req->getSize(), 77111051Sandreas.hansson@arm.com pkt->req->getFlags(), 77211051Sandreas.hansson@arm.com pkt->req->masterId()); 77311051Sandreas.hansson@arm.com pf = new Packet(req, pkt->cmd); 77411051Sandreas.hansson@arm.com pf->allocate(); 77511051Sandreas.hansson@arm.com assert(pf->getAddr() == pkt->getAddr()); 77611051Sandreas.hansson@arm.com assert(pf->getSize() == pkt->getSize()); 77711051Sandreas.hansson@arm.com } 77811051Sandreas.hansson@arm.com 77911051Sandreas.hansson@arm.com pkt->makeTimingResponse(); 78011051Sandreas.hansson@arm.com 78111051Sandreas.hansson@arm.com // request_time is used here, taking into account lat and the delay 78211051Sandreas.hansson@arm.com // charged if the packet comes from the xbar. 78311051Sandreas.hansson@arm.com cpuSidePort->schedTimingResp(pkt, request_time, true); 78411051Sandreas.hansson@arm.com 78511051Sandreas.hansson@arm.com // If an outstanding request is in progress (we found an 78611051Sandreas.hansson@arm.com // MSHR) this is set to null 78711051Sandreas.hansson@arm.com pkt = pf; 78811051Sandreas.hansson@arm.com } 78911051Sandreas.hansson@arm.com 79011051Sandreas.hansson@arm.com if (mshr) { 79111051Sandreas.hansson@arm.com /// MSHR hit 79211051Sandreas.hansson@arm.com /// @note writebacks will be checked in getNextMSHR() 79311051Sandreas.hansson@arm.com /// for any conflicting requests to the same block 79411051Sandreas.hansson@arm.com 79511051Sandreas.hansson@arm.com //@todo remove hw_pf here 79611051Sandreas.hansson@arm.com 79711051Sandreas.hansson@arm.com // Coalesce unless it was a software prefetch (see above). 79811051Sandreas.hansson@arm.com if (pkt) { 79911051Sandreas.hansson@arm.com assert(!pkt->isWriteback()); 80011051Sandreas.hansson@arm.com // CleanEvicts corresponding to blocks which have 80111051Sandreas.hansson@arm.com // outstanding requests in MSHRs are simply sunk here 80211051Sandreas.hansson@arm.com if (pkt->cmd == MemCmd::CleanEvict) { 80311051Sandreas.hansson@arm.com pendingDelete.reset(pkt); 80411051Sandreas.hansson@arm.com } else { 80511051Sandreas.hansson@arm.com DPRINTF(Cache, "%s coalescing MSHR for %s\n", __func__, 80611051Sandreas.hansson@arm.com pkt->print()); 80711051Sandreas.hansson@arm.com 80811051Sandreas.hansson@arm.com assert(pkt->req->masterId() < system->maxMasters()); 80911051Sandreas.hansson@arm.com mshr_hits[pkt->cmdToIndex()][pkt->req->masterId()]++; 81011051Sandreas.hansson@arm.com // We use forward_time here because it is the same 81111051Sandreas.hansson@arm.com // considering new targets. We have multiple 81211051Sandreas.hansson@arm.com // requests for the same address here. It 81311051Sandreas.hansson@arm.com // specifies the latency to allocate an internal 81411051Sandreas.hansson@arm.com // buffer and to schedule an event to the queued 81511051Sandreas.hansson@arm.com // port and also takes into account the additional 81611051Sandreas.hansson@arm.com // delay of the xbar. 81711051Sandreas.hansson@arm.com mshr->allocateTarget(pkt, forward_time, order++, 81811051Sandreas.hansson@arm.com allocOnFill(pkt->cmd)); 81911051Sandreas.hansson@arm.com if (mshr->getNumTargets() == numTarget) { 82011051Sandreas.hansson@arm.com noTargetMSHR = mshr; 82111051Sandreas.hansson@arm.com setBlocked(Blocked_NoTargets); 82211051Sandreas.hansson@arm.com // need to be careful with this... if this mshr isn't 82311051Sandreas.hansson@arm.com // ready yet (i.e. time > curTick()), we don't want to 82411051Sandreas.hansson@arm.com // move it ahead of mshrs that are ready 82511051Sandreas.hansson@arm.com // mshrQueue.moveToFront(mshr); 82611051Sandreas.hansson@arm.com } 82711051Sandreas.hansson@arm.com } 82811051Sandreas.hansson@arm.com // We should call the prefetcher reguardless if the request is 82911051Sandreas.hansson@arm.com // satisfied or not, reguardless if the request is in the MSHR 83011051Sandreas.hansson@arm.com // or not. The request could be a ReadReq hit, but still not 83111051Sandreas.hansson@arm.com // satisfied (potentially because of a prior write to the same 83211051Sandreas.hansson@arm.com // cache line. So, even when not satisfied, tehre is an MSHR 83311051Sandreas.hansson@arm.com // already allocated for this, we need to let the prefetcher 83411051Sandreas.hansson@arm.com // know about the request 83511051Sandreas.hansson@arm.com if (prefetcher) { 83611051Sandreas.hansson@arm.com // Don't notify on SWPrefetch 83711051Sandreas.hansson@arm.com if (!pkt->cmd.isSWPrefetch()) 83811051Sandreas.hansson@arm.com next_pf_time = prefetcher->notify(pkt); 83911051Sandreas.hansson@arm.com } 84011051Sandreas.hansson@arm.com } 84111051Sandreas.hansson@arm.com } else { 84211051Sandreas.hansson@arm.com // no MSHR 84311051Sandreas.hansson@arm.com assert(pkt->req->masterId() < system->maxMasters()); 84411051Sandreas.hansson@arm.com if (pkt->req->isUncacheable()) { 84511051Sandreas.hansson@arm.com mshr_uncacheable[pkt->cmdToIndex()][pkt->req->masterId()]++; 84611051Sandreas.hansson@arm.com } else { 84711051Sandreas.hansson@arm.com mshr_misses[pkt->cmdToIndex()][pkt->req->masterId()]++; 84811051Sandreas.hansson@arm.com } 84911051Sandreas.hansson@arm.com 85011051Sandreas.hansson@arm.com if (pkt->isEviction() || 85111051Sandreas.hansson@arm.com (pkt->req->isUncacheable() && pkt->isWrite())) { 85211051Sandreas.hansson@arm.com // We use forward_time here because there is an 85311051Sandreas.hansson@arm.com // uncached memory write, forwarded to WriteBuffer. 85411051Sandreas.hansson@arm.com allocateWriteBuffer(pkt, forward_time); 85511051Sandreas.hansson@arm.com } else { 85611051Sandreas.hansson@arm.com if (blk && blk->isValid()) { 85711051Sandreas.hansson@arm.com // should have flushed and have no valid block 85811051Sandreas.hansson@arm.com assert(!pkt->req->isUncacheable()); 85911051Sandreas.hansson@arm.com 86011051Sandreas.hansson@arm.com // If we have a write miss to a valid block, we 86111051Sandreas.hansson@arm.com // need to mark the block non-readable. Otherwise 86211051Sandreas.hansson@arm.com // if we allow reads while there's an outstanding 86311051Sandreas.hansson@arm.com // write miss, the read could return stale data 86411051Sandreas.hansson@arm.com // out of the cache block... a more aggressive 86511051Sandreas.hansson@arm.com // system could detect the overlap (if any) and 86611051Sandreas.hansson@arm.com // forward data out of the MSHRs, but we don't do 86711051Sandreas.hansson@arm.com // that yet. Note that we do need to leave the 86811051Sandreas.hansson@arm.com // block valid so that it stays in the cache, in 86911051Sandreas.hansson@arm.com // case we get an upgrade response (and hence no 87011051Sandreas.hansson@arm.com // new data) when the write miss completes. 87111051Sandreas.hansson@arm.com // As long as CPUs do proper store/load forwarding 87211051Sandreas.hansson@arm.com // internally, and have a sufficiently weak memory 87311051Sandreas.hansson@arm.com // model, this is probably unnecessary, but at some 87411051Sandreas.hansson@arm.com // point it must have seemed like we needed it... 87511051Sandreas.hansson@arm.com assert(pkt->needsWritable()); 87611051Sandreas.hansson@arm.com assert(!blk->isWritable()); 87711051Sandreas.hansson@arm.com blk->status &= ~BlkReadable; 87811051Sandreas.hansson@arm.com } 87911051Sandreas.hansson@arm.com // Here we are using forward_time, modelling the latency of 88011051Sandreas.hansson@arm.com // a miss (outbound) just as forwardLatency, neglecting the 88111051Sandreas.hansson@arm.com // lookupLatency component. 88211051Sandreas.hansson@arm.com allocateMissBuffer(pkt, forward_time); 88311051Sandreas.hansson@arm.com } 88411051Sandreas.hansson@arm.com 88511051Sandreas.hansson@arm.com if (prefetcher) { 88611051Sandreas.hansson@arm.com // Don't notify on SWPrefetch 88711051Sandreas.hansson@arm.com if (!pkt->cmd.isSWPrefetch()) 88811051Sandreas.hansson@arm.com next_pf_time = prefetcher->notify(pkt); 88911051Sandreas.hansson@arm.com } 89011051Sandreas.hansson@arm.com } 89111051Sandreas.hansson@arm.com } 89211051Sandreas.hansson@arm.com 89311051Sandreas.hansson@arm.com if (next_pf_time != MaxTick) 89411051Sandreas.hansson@arm.com schedMemSideSendEvent(next_pf_time); 89511051Sandreas.hansson@arm.com 89611051Sandreas.hansson@arm.com return true; 89711051Sandreas.hansson@arm.com} 89811051Sandreas.hansson@arm.com 89911051Sandreas.hansson@arm.comPacketPtr 90011051Sandreas.hansson@arm.comCache::createMissPacket(PacketPtr cpu_pkt, CacheBlk *blk, 90111051Sandreas.hansson@arm.com bool needsWritable) const 90211051Sandreas.hansson@arm.com{ 90311051Sandreas.hansson@arm.com // should never see evictions here 90411051Sandreas.hansson@arm.com assert(!cpu_pkt->isEviction()); 90511051Sandreas.hansson@arm.com 90611051Sandreas.hansson@arm.com bool blkValid = blk && blk->isValid(); 90711051Sandreas.hansson@arm.com 90811051Sandreas.hansson@arm.com if (cpu_pkt->req->isUncacheable() || 90911051Sandreas.hansson@arm.com (!blkValid && cpu_pkt->isUpgrade()) || 91011051Sandreas.hansson@arm.com cpu_pkt->cmd == MemCmd::InvalidateReq) { 91111051Sandreas.hansson@arm.com // uncacheable requests and upgrades from upper-level caches 91211051Sandreas.hansson@arm.com // that missed completely just go through as is 91311051Sandreas.hansson@arm.com return nullptr; 91411051Sandreas.hansson@arm.com } 91511051Sandreas.hansson@arm.com 91611051Sandreas.hansson@arm.com assert(cpu_pkt->needsResponse()); 91711051Sandreas.hansson@arm.com 91811051Sandreas.hansson@arm.com MemCmd cmd; 91911051Sandreas.hansson@arm.com // @TODO make useUpgrades a parameter. 92011051Sandreas.hansson@arm.com // Note that ownership protocols require upgrade, otherwise a 92111051Sandreas.hansson@arm.com // write miss on a shared owned block will generate a ReadExcl, 92211051Sandreas.hansson@arm.com // which will clobber the owned copy. 92311051Sandreas.hansson@arm.com const bool useUpgrades = true; 92411051Sandreas.hansson@arm.com if (cpu_pkt->cmd == MemCmd::WriteLineReq) { 92511051Sandreas.hansson@arm.com assert(!blkValid || !blk->isWritable()); 92611051Sandreas.hansson@arm.com // forward as invalidate to all other caches, this gives us 92711051Sandreas.hansson@arm.com // the line in Exclusive state, and invalidates all other 92811051Sandreas.hansson@arm.com // copies 92911051Sandreas.hansson@arm.com cmd = MemCmd::InvalidateReq; 93011051Sandreas.hansson@arm.com } else if (blkValid && useUpgrades) { 93111051Sandreas.hansson@arm.com // only reason to be here is that blk is read only and we need 93211051Sandreas.hansson@arm.com // it to be writable 93311051Sandreas.hansson@arm.com assert(needsWritable); 93411051Sandreas.hansson@arm.com assert(!blk->isWritable()); 93511051Sandreas.hansson@arm.com cmd = cpu_pkt->isLLSC() ? MemCmd::SCUpgradeReq : MemCmd::UpgradeReq; 93611051Sandreas.hansson@arm.com } else if (cpu_pkt->cmd == MemCmd::SCUpgradeFailReq || 93711051Sandreas.hansson@arm.com cpu_pkt->cmd == MemCmd::StoreCondFailReq) { 93811051Sandreas.hansson@arm.com // Even though this SC will fail, we still need to send out the 93911051Sandreas.hansson@arm.com // request and get the data to supply it to other snoopers in the case 94011051Sandreas.hansson@arm.com // where the determination the StoreCond fails is delayed due to 94111051Sandreas.hansson@arm.com // all caches not being on the same local bus. 94211051Sandreas.hansson@arm.com cmd = MemCmd::SCUpgradeFailReq; 94311051Sandreas.hansson@arm.com } else { 94411051Sandreas.hansson@arm.com // block is invalid 94511051Sandreas.hansson@arm.com cmd = needsWritable ? MemCmd::ReadExReq : 94611051Sandreas.hansson@arm.com (isReadOnly ? MemCmd::ReadCleanReq : MemCmd::ReadSharedReq); 94711051Sandreas.hansson@arm.com } 94811051Sandreas.hansson@arm.com PacketPtr pkt = new Packet(cpu_pkt->req, cmd, blkSize); 94911051Sandreas.hansson@arm.com 95011051Sandreas.hansson@arm.com // if there are upstream caches that have already marked the 95111051Sandreas.hansson@arm.com // packet as having sharers (not passing writable), pass that info 95211051Sandreas.hansson@arm.com // downstream 95311051Sandreas.hansson@arm.com if (cpu_pkt->hasSharers() && !needsWritable) { 95411051Sandreas.hansson@arm.com // note that cpu_pkt may have spent a considerable time in the 95511051Sandreas.hansson@arm.com // MSHR queue and that the information could possibly be out 95611051Sandreas.hansson@arm.com // of date, however, there is no harm in conservatively 95711051Sandreas.hansson@arm.com // assuming the block has sharers 95811051Sandreas.hansson@arm.com pkt->setHasSharers(); 95911051Sandreas.hansson@arm.com DPRINTF(Cache, "%s: passing hasSharers from %s to %s\n", 96011051Sandreas.hansson@arm.com __func__, cpu_pkt->print(), pkt->print()); 96111051Sandreas.hansson@arm.com } 96211051Sandreas.hansson@arm.com 96311051Sandreas.hansson@arm.com // the packet should be block aligned 96411051Sandreas.hansson@arm.com assert(pkt->getAddr() == pkt->getBlockAddr(blkSize)); 96511051Sandreas.hansson@arm.com 96611051Sandreas.hansson@arm.com pkt->allocate(); 96711051Sandreas.hansson@arm.com DPRINTF(Cache, "%s: created %s from %s\n", __func__, pkt->print(), 96811051Sandreas.hansson@arm.com cpu_pkt->print()); 96911051Sandreas.hansson@arm.com return pkt; 97011051Sandreas.hansson@arm.com} 97111051Sandreas.hansson@arm.com 97211051Sandreas.hansson@arm.com 97311051Sandreas.hansson@arm.comTick 97411051Sandreas.hansson@arm.comCache::recvAtomic(PacketPtr pkt) 97511051Sandreas.hansson@arm.com{ 97611051Sandreas.hansson@arm.com // We are in atomic mode so we pay just for lookupLatency here. 97711051Sandreas.hansson@arm.com Cycles lat = lookupLatency; 97811051Sandreas.hansson@arm.com 97911051Sandreas.hansson@arm.com // Forward the request if the system is in cache bypass mode. 98011051Sandreas.hansson@arm.com if (system->bypassCaches()) 98111051Sandreas.hansson@arm.com return ticksToCycles(memSidePort->sendAtomic(pkt)); 98211051Sandreas.hansson@arm.com 98311051Sandreas.hansson@arm.com promoteWholeLineWrites(pkt); 98411051Sandreas.hansson@arm.com 98511051Sandreas.hansson@arm.com // follow the same flow as in recvTimingReq, and check if a cache 98611051Sandreas.hansson@arm.com // above us is responding 98711051Sandreas.hansson@arm.com if (pkt->cacheResponding()) { 98811051Sandreas.hansson@arm.com DPRINTF(Cache, "Cache above responding to %s: not responding\n", 98911051Sandreas.hansson@arm.com pkt->print()); 99011051Sandreas.hansson@arm.com 99111051Sandreas.hansson@arm.com // if a cache is responding, and it had the line in Owned 99211051Sandreas.hansson@arm.com // rather than Modified state, we need to invalidate any 99311051Sandreas.hansson@arm.com // copies that are not on the same path to memory 99411051Sandreas.hansson@arm.com assert(pkt->needsWritable() && !pkt->responderHadWritable()); 99511051Sandreas.hansson@arm.com lat += ticksToCycles(memSidePort->sendAtomic(pkt)); 99611051Sandreas.hansson@arm.com 99711051Sandreas.hansson@arm.com return lat * clockPeriod(); 99811051Sandreas.hansson@arm.com } 99911051Sandreas.hansson@arm.com 100011051Sandreas.hansson@arm.com // should assert here that there are no outstanding MSHRs or 100111051Sandreas.hansson@arm.com // writebacks... that would mean that someone used an atomic 100211051Sandreas.hansson@arm.com // access in timing mode 100311051Sandreas.hansson@arm.com 100411051Sandreas.hansson@arm.com CacheBlk *blk = nullptr; 100511051Sandreas.hansson@arm.com PacketList writebacks; 100611051Sandreas.hansson@arm.com bool satisfied = access(pkt, blk, lat, writebacks); 100711051Sandreas.hansson@arm.com 100811051Sandreas.hansson@arm.com // handle writebacks resulting from the access here to ensure they 100911051Sandreas.hansson@arm.com // logically proceed anything happening below 101011051Sandreas.hansson@arm.com doWritebacksAtomic(writebacks); 101111051Sandreas.hansson@arm.com 101211051Sandreas.hansson@arm.com if (!satisfied) { 101311051Sandreas.hansson@arm.com // MISS 101411051Sandreas.hansson@arm.com 101511051Sandreas.hansson@arm.com // deal with the packets that go through the write path of 101611051Sandreas.hansson@arm.com // the cache, i.e. any evictions and uncacheable writes 101711051Sandreas.hansson@arm.com if (pkt->isEviction() || 101811051Sandreas.hansson@arm.com (pkt->req->isUncacheable() && pkt->isWrite())) { 101911051Sandreas.hansson@arm.com lat += ticksToCycles(memSidePort->sendAtomic(pkt)); 102011051Sandreas.hansson@arm.com return lat * clockPeriod(); 102111051Sandreas.hansson@arm.com } 102211051Sandreas.hansson@arm.com // only misses left 102311051Sandreas.hansson@arm.com 102411051Sandreas.hansson@arm.com PacketPtr bus_pkt = createMissPacket(pkt, blk, pkt->needsWritable()); 102511051Sandreas.hansson@arm.com 102611051Sandreas.hansson@arm.com bool is_forward = (bus_pkt == nullptr); 102711051Sandreas.hansson@arm.com 102811051Sandreas.hansson@arm.com if (is_forward) { 102911051Sandreas.hansson@arm.com // just forwarding the same request to the next level 103011051Sandreas.hansson@arm.com // no local cache operation involved 103111051Sandreas.hansson@arm.com bus_pkt = pkt; 103211051Sandreas.hansson@arm.com } 103311051Sandreas.hansson@arm.com 103411051Sandreas.hansson@arm.com DPRINTF(Cache, "%s: Sending an atomic %s\n", __func__, 103511051Sandreas.hansson@arm.com bus_pkt->print()); 103611051Sandreas.hansson@arm.com 103711051Sandreas.hansson@arm.com#if TRACING_ON 103811051Sandreas.hansson@arm.com CacheBlk::State old_state = blk ? blk->status : 0; 103911051Sandreas.hansson@arm.com#endif 104011051Sandreas.hansson@arm.com 104111051Sandreas.hansson@arm.com lat += ticksToCycles(memSidePort->sendAtomic(bus_pkt)); 104211051Sandreas.hansson@arm.com 104311051Sandreas.hansson@arm.com bool is_invalidate = bus_pkt->isInvalidate(); 104411051Sandreas.hansson@arm.com 104511051Sandreas.hansson@arm.com // We are now dealing with the response handling 104611051Sandreas.hansson@arm.com DPRINTF(Cache, "%s: Receive response: %s in state %i\n", __func__, 104711051Sandreas.hansson@arm.com bus_pkt->print(), old_state); 104811051Sandreas.hansson@arm.com 104911051Sandreas.hansson@arm.com // If packet was a forward, the response (if any) is already 105011051Sandreas.hansson@arm.com // in place in the bus_pkt == pkt structure, so we don't need 105111051Sandreas.hansson@arm.com // to do anything. Otherwise, use the separate bus_pkt to 105211051Sandreas.hansson@arm.com // generate response to pkt and then delete it. 105311051Sandreas.hansson@arm.com if (!is_forward) { 105411051Sandreas.hansson@arm.com if (pkt->needsResponse()) { 105511051Sandreas.hansson@arm.com assert(bus_pkt->isResponse()); 105611051Sandreas.hansson@arm.com if (bus_pkt->isError()) { 105711051Sandreas.hansson@arm.com pkt->makeAtomicResponse(); 105811051Sandreas.hansson@arm.com pkt->copyError(bus_pkt); 105911051Sandreas.hansson@arm.com } else if (pkt->cmd == MemCmd::WriteLineReq) { 106011051Sandreas.hansson@arm.com // note the use of pkt, not bus_pkt here. 106111051Sandreas.hansson@arm.com 106211051Sandreas.hansson@arm.com // write-line request to the cache that promoted 106311051Sandreas.hansson@arm.com // the write to a whole line 106411051Sandreas.hansson@arm.com blk = handleFill(pkt, blk, writebacks, 106511051Sandreas.hansson@arm.com allocOnFill(pkt->cmd)); 106611051Sandreas.hansson@arm.com assert(blk != NULL); 106711051Sandreas.hansson@arm.com is_invalidate = false; 106811051Sandreas.hansson@arm.com satisfyRequest(pkt, blk); 106911051Sandreas.hansson@arm.com } else if (bus_pkt->isRead() || 107011051Sandreas.hansson@arm.com bus_pkt->cmd == MemCmd::UpgradeResp) { 107111051Sandreas.hansson@arm.com // we're updating cache state to allow us to 107211051Sandreas.hansson@arm.com // satisfy the upstream request from the cache 107311051Sandreas.hansson@arm.com blk = handleFill(bus_pkt, blk, writebacks, 107411051Sandreas.hansson@arm.com allocOnFill(pkt->cmd)); 107511051Sandreas.hansson@arm.com satisfyRequest(pkt, blk); 107611051Sandreas.hansson@arm.com maintainClusivity(pkt->fromCache(), blk); 107711051Sandreas.hansson@arm.com } else { 107811051Sandreas.hansson@arm.com // we're satisfying the upstream request without 107911051Sandreas.hansson@arm.com // modifying cache state, e.g., a write-through 108011051Sandreas.hansson@arm.com pkt->makeAtomicResponse(); 108111051Sandreas.hansson@arm.com } 108211051Sandreas.hansson@arm.com } 108311051Sandreas.hansson@arm.com delete bus_pkt; 108411051Sandreas.hansson@arm.com } 108511051Sandreas.hansson@arm.com 108611051Sandreas.hansson@arm.com if (is_invalidate && blk && blk->isValid()) { 108711051Sandreas.hansson@arm.com invalidateBlock(blk); 108811051Sandreas.hansson@arm.com } 108911051Sandreas.hansson@arm.com } 109011051Sandreas.hansson@arm.com 109111051Sandreas.hansson@arm.com // Note that we don't invoke the prefetcher at all in atomic mode. 109211051Sandreas.hansson@arm.com // It's not clear how to do it properly, particularly for 109311051Sandreas.hansson@arm.com // prefetchers that aggressively generate prefetch candidates and 109411051Sandreas.hansson@arm.com // rely on bandwidth contention to throttle them; these will tend 109511051Sandreas.hansson@arm.com // to pollute the cache in atomic mode since there is no bandwidth 109611051Sandreas.hansson@arm.com // contention. If we ever do want to enable prefetching in atomic 109711051Sandreas.hansson@arm.com // mode, though, this is the place to do it... see timingAccess() 109811051Sandreas.hansson@arm.com // for an example (though we'd want to issue the prefetch(es) 109911051Sandreas.hansson@arm.com // immediately rather than calling requestMemSideBus() as we do 110011051Sandreas.hansson@arm.com // there). 110111051Sandreas.hansson@arm.com 110211051Sandreas.hansson@arm.com // do any writebacks resulting from the response handling 110311051Sandreas.hansson@arm.com doWritebacksAtomic(writebacks); 110411051Sandreas.hansson@arm.com 110511051Sandreas.hansson@arm.com // if we used temp block, check to see if its valid and if so 110611051Sandreas.hansson@arm.com // clear it out, but only do so after the call to recvAtomic is 110711051Sandreas.hansson@arm.com // finished so that any downstream observers (such as a snoop 110811051Sandreas.hansson@arm.com // filter), first see the fill, and only then see the eviction 110911051Sandreas.hansson@arm.com if (blk == tempBlock && tempBlock->isValid()) { 111011051Sandreas.hansson@arm.com // the atomic CPU calls recvAtomic for fetch and load/store 111111051Sandreas.hansson@arm.com // sequentuially, and we may already have a tempBlock 111211051Sandreas.hansson@arm.com // writeback from the fetch that we have not yet sent 111311051Sandreas.hansson@arm.com if (tempBlockWriteback) { 111411051Sandreas.hansson@arm.com // if that is the case, write the prevoius one back, and 111511051Sandreas.hansson@arm.com // do not schedule any new event 111611051Sandreas.hansson@arm.com writebackTempBlockAtomic(); 111711051Sandreas.hansson@arm.com } else { 111811051Sandreas.hansson@arm.com // the writeback/clean eviction happens after the call to 111911051Sandreas.hansson@arm.com // recvAtomic has finished (but before any successive 112011051Sandreas.hansson@arm.com // calls), so that the response handling from the fill is 112111051Sandreas.hansson@arm.com // allowed to happen first 112211051Sandreas.hansson@arm.com schedule(writebackTempBlockAtomicEvent, curTick()); 112311051Sandreas.hansson@arm.com } 112411051Sandreas.hansson@arm.com 112511051Sandreas.hansson@arm.com tempBlockWriteback = (blk->isDirty() || writebackClean) ? 112611051Sandreas.hansson@arm.com writebackBlk(blk) : cleanEvictBlk(blk); 112711051Sandreas.hansson@arm.com invalidateBlock(blk); 112811051Sandreas.hansson@arm.com } 112911051Sandreas.hansson@arm.com 113011051Sandreas.hansson@arm.com if (pkt->needsResponse()) { 113111051Sandreas.hansson@arm.com pkt->makeAtomicResponse(); 113211051Sandreas.hansson@arm.com } 113311051Sandreas.hansson@arm.com 113411051Sandreas.hansson@arm.com return lat * clockPeriod(); 113511051Sandreas.hansson@arm.com} 113611051Sandreas.hansson@arm.com 113711051Sandreas.hansson@arm.com 113811051Sandreas.hansson@arm.comvoid 113911051Sandreas.hansson@arm.comCache::functionalAccess(PacketPtr pkt, bool fromCpuSide) 114011051Sandreas.hansson@arm.com{ 114111051Sandreas.hansson@arm.com if (system->bypassCaches()) { 114211051Sandreas.hansson@arm.com // Packets from the memory side are snoop request and 114311051Sandreas.hansson@arm.com // shouldn't happen in bypass mode. 114411051Sandreas.hansson@arm.com assert(fromCpuSide); 114511051Sandreas.hansson@arm.com 114611051Sandreas.hansson@arm.com // The cache should be flushed if we are in cache bypass mode, 114711051Sandreas.hansson@arm.com // so we don't need to check if we need to update anything. 114811051Sandreas.hansson@arm.com memSidePort->sendFunctional(pkt); 114911051Sandreas.hansson@arm.com return; 115011051Sandreas.hansson@arm.com } 115111051Sandreas.hansson@arm.com 115211051Sandreas.hansson@arm.com Addr blk_addr = pkt->getBlockAddr(blkSize); 115311051Sandreas.hansson@arm.com bool is_secure = pkt->isSecure(); 115411051Sandreas.hansson@arm.com CacheBlk *blk = tags->findBlock(pkt->getAddr(), is_secure); 115511051Sandreas.hansson@arm.com MSHR *mshr = mshrQueue.findMatch(blk_addr, is_secure); 115611051Sandreas.hansson@arm.com 115711051Sandreas.hansson@arm.com pkt->pushLabel(name()); 115811051Sandreas.hansson@arm.com 115911051Sandreas.hansson@arm.com CacheBlkPrintWrapper cbpw(blk); 116011051Sandreas.hansson@arm.com 116111051Sandreas.hansson@arm.com // Note that just because an L2/L3 has valid data doesn't mean an 116211051Sandreas.hansson@arm.com // L1 doesn't have a more up-to-date modified copy that still 116311051Sandreas.hansson@arm.com // needs to be found. As a result we always update the request if 116411051Sandreas.hansson@arm.com // we have it, but only declare it satisfied if we are the owner. 116511051Sandreas.hansson@arm.com 116611051Sandreas.hansson@arm.com // see if we have data at all (owned or otherwise) 116711051Sandreas.hansson@arm.com bool have_data = blk && blk->isValid() 116811051Sandreas.hansson@arm.com && pkt->checkFunctional(&cbpw, blk_addr, is_secure, blkSize, 116911051Sandreas.hansson@arm.com blk->data); 117011051Sandreas.hansson@arm.com 117111051Sandreas.hansson@arm.com // data we have is dirty if marked as such or if we have an 117211051Sandreas.hansson@arm.com // in-service MSHR that is pending a modified line 117311051Sandreas.hansson@arm.com bool have_dirty = 117411051Sandreas.hansson@arm.com have_data && (blk->isDirty() || 117511051Sandreas.hansson@arm.com (mshr && mshr->inService && mshr->isPendingModified())); 117611051Sandreas.hansson@arm.com 117711051Sandreas.hansson@arm.com bool done = have_dirty 117811051Sandreas.hansson@arm.com || cpuSidePort->checkFunctional(pkt) 117911051Sandreas.hansson@arm.com || mshrQueue.checkFunctional(pkt, blk_addr) 118011051Sandreas.hansson@arm.com || writeBuffer.checkFunctional(pkt, blk_addr) 118111051Sandreas.hansson@arm.com || memSidePort->checkFunctional(pkt); 118211051Sandreas.hansson@arm.com 118311051Sandreas.hansson@arm.com DPRINTF(CacheVerbose, "%s: %s %s%s%s\n", __func__, pkt->print(), 118411051Sandreas.hansson@arm.com (blk && blk->isValid()) ? "valid " : "", 118511051Sandreas.hansson@arm.com have_data ? "data " : "", done ? "done " : ""); 118611051Sandreas.hansson@arm.com 118711051Sandreas.hansson@arm.com // We're leaving the cache, so pop cache->name() label 118811051Sandreas.hansson@arm.com pkt->popLabel(); 118911051Sandreas.hansson@arm.com 119011051Sandreas.hansson@arm.com if (done) { 119111051Sandreas.hansson@arm.com pkt->makeResponse(); 119211051Sandreas.hansson@arm.com } else { 119311051Sandreas.hansson@arm.com // if it came as a request from the CPU side then make sure it 119411051Sandreas.hansson@arm.com // continues towards the memory side 119511051Sandreas.hansson@arm.com if (fromCpuSide) { 119611051Sandreas.hansson@arm.com memSidePort->sendFunctional(pkt); 119711051Sandreas.hansson@arm.com } else if (cpuSidePort->isSnooping()) { 119811051Sandreas.hansson@arm.com // if it came from the memory side, it must be a snoop request 119911051Sandreas.hansson@arm.com // and we should only forward it if we are forwarding snoops 120011051Sandreas.hansson@arm.com cpuSidePort->sendFunctionalSnoop(pkt); 120111051Sandreas.hansson@arm.com } 120211051Sandreas.hansson@arm.com } 120311051Sandreas.hansson@arm.com} 120411051Sandreas.hansson@arm.com 120511051Sandreas.hansson@arm.com 120611051Sandreas.hansson@arm.com///////////////////////////////////////////////////// 120711051Sandreas.hansson@arm.com// 120811051Sandreas.hansson@arm.com// Response handling: responses from the memory side 120911051Sandreas.hansson@arm.com// 121011051Sandreas.hansson@arm.com///////////////////////////////////////////////////// 121111051Sandreas.hansson@arm.com 121211051Sandreas.hansson@arm.com 121311051Sandreas.hansson@arm.comvoid 121411051Sandreas.hansson@arm.comCache::handleUncacheableWriteResp(PacketPtr pkt) 121511051Sandreas.hansson@arm.com{ 121611051Sandreas.hansson@arm.com Tick completion_time = clockEdge(responseLatency) + 121711051Sandreas.hansson@arm.com pkt->headerDelay + pkt->payloadDelay; 121811051Sandreas.hansson@arm.com 121911051Sandreas.hansson@arm.com // Reset the bus additional time as it is now accounted for 122011051Sandreas.hansson@arm.com pkt->headerDelay = pkt->payloadDelay = 0; 122111051Sandreas.hansson@arm.com 122211051Sandreas.hansson@arm.com cpuSidePort->schedTimingResp(pkt, completion_time, true); 122311051Sandreas.hansson@arm.com} 122411051Sandreas.hansson@arm.com 122511051Sandreas.hansson@arm.comvoid 122611051Sandreas.hansson@arm.comCache::recvTimingResp(PacketPtr pkt) 122711051Sandreas.hansson@arm.com{ 122811051Sandreas.hansson@arm.com assert(pkt->isResponse()); 122911051Sandreas.hansson@arm.com 123011051Sandreas.hansson@arm.com // all header delay should be paid for by the crossbar, unless 123111051Sandreas.hansson@arm.com // this is a prefetch response from above 123211051Sandreas.hansson@arm.com panic_if(pkt->headerDelay != 0 && pkt->cmd != MemCmd::HardPFResp, 123311051Sandreas.hansson@arm.com "%s saw a non-zero packet delay\n", name()); 123411051Sandreas.hansson@arm.com 123511051Sandreas.hansson@arm.com bool is_error = pkt->isError(); 123611051Sandreas.hansson@arm.com 123711051Sandreas.hansson@arm.com if (is_error) { 123811051Sandreas.hansson@arm.com DPRINTF(Cache, "%s: Cache received %s with error\n", __func__, 123911051Sandreas.hansson@arm.com pkt->print()); 124011051Sandreas.hansson@arm.com } 124111051Sandreas.hansson@arm.com 124211051Sandreas.hansson@arm.com DPRINTF(Cache, "%s: Handling response %s\n", __func__, 124311051Sandreas.hansson@arm.com pkt->print()); 124411051Sandreas.hansson@arm.com 124511051Sandreas.hansson@arm.com // if this is a write, we should be looking at an uncacheable 124611051Sandreas.hansson@arm.com // write 124711051Sandreas.hansson@arm.com if (pkt->isWrite()) { 124811051Sandreas.hansson@arm.com assert(pkt->req->isUncacheable()); 124911051Sandreas.hansson@arm.com handleUncacheableWriteResp(pkt); 125011051Sandreas.hansson@arm.com return; 125111051Sandreas.hansson@arm.com } 125211051Sandreas.hansson@arm.com 125311051Sandreas.hansson@arm.com // we have dealt with any (uncacheable) writes above, from here on 125411051Sandreas.hansson@arm.com // we know we are dealing with an MSHR due to a miss or a prefetch 125511051Sandreas.hansson@arm.com MSHR *mshr = dynamic_cast<MSHR*>(pkt->popSenderState()); 125611051Sandreas.hansson@arm.com assert(mshr); 125711051Sandreas.hansson@arm.com 125811051Sandreas.hansson@arm.com if (mshr == noTargetMSHR) { 125911051Sandreas.hansson@arm.com // we always clear at least one target 126011051Sandreas.hansson@arm.com clearBlocked(Blocked_NoTargets); 126111051Sandreas.hansson@arm.com noTargetMSHR = nullptr; 126211051Sandreas.hansson@arm.com } 126311051Sandreas.hansson@arm.com 126411051Sandreas.hansson@arm.com // Initial target is used just for stats 126511051Sandreas.hansson@arm.com MSHR::Target *initial_tgt = mshr->getTarget(); 126611051Sandreas.hansson@arm.com int stats_cmd_idx = initial_tgt->pkt->cmdToIndex(); 126711051Sandreas.hansson@arm.com Tick miss_latency = curTick() - initial_tgt->recvTime; 126811051Sandreas.hansson@arm.com 126911051Sandreas.hansson@arm.com if (pkt->req->isUncacheable()) { 127011051Sandreas.hansson@arm.com assert(pkt->req->masterId() < system->maxMasters()); 127111051Sandreas.hansson@arm.com mshr_uncacheable_lat[stats_cmd_idx][pkt->req->masterId()] += 127211051Sandreas.hansson@arm.com miss_latency; 127311051Sandreas.hansson@arm.com } else { 127411051Sandreas.hansson@arm.com assert(pkt->req->masterId() < system->maxMasters()); 127511051Sandreas.hansson@arm.com mshr_miss_latency[stats_cmd_idx][pkt->req->masterId()] += 127611051Sandreas.hansson@arm.com miss_latency; 127711051Sandreas.hansson@arm.com } 127811051Sandreas.hansson@arm.com 127911051Sandreas.hansson@arm.com bool wasFull = mshrQueue.isFull(); 128011051Sandreas.hansson@arm.com 128111051Sandreas.hansson@arm.com PacketList writebacks; 128211051Sandreas.hansson@arm.com 128311051Sandreas.hansson@arm.com Tick forward_time = clockEdge(forwardLatency) + pkt->headerDelay; 128411051Sandreas.hansson@arm.com 128511051Sandreas.hansson@arm.com // upgrade deferred targets if the response has no sharers, and is 128611051Sandreas.hansson@arm.com // thus passing writable 128711051Sandreas.hansson@arm.com if (!pkt->hasSharers()) { 128811051Sandreas.hansson@arm.com mshr->promoteWritable(); 128911051Sandreas.hansson@arm.com } 129011051Sandreas.hansson@arm.com 129111051Sandreas.hansson@arm.com bool is_fill = !mshr->isForward && 129211051Sandreas.hansson@arm.com (pkt->isRead() || pkt->cmd == MemCmd::UpgradeResp); 129311051Sandreas.hansson@arm.com 129411051Sandreas.hansson@arm.com CacheBlk *blk = tags->findBlock(pkt->getAddr(), pkt->isSecure()); 129511051Sandreas.hansson@arm.com 129611051Sandreas.hansson@arm.com if (is_fill && !is_error) { 129711051Sandreas.hansson@arm.com DPRINTF(Cache, "Block for addr %#llx being updated in Cache\n", 129811051Sandreas.hansson@arm.com pkt->getAddr()); 129911051Sandreas.hansson@arm.com 130011051Sandreas.hansson@arm.com blk = handleFill(pkt, blk, writebacks, mshr->allocOnFill()); 130111051Sandreas.hansson@arm.com assert(blk != nullptr); 130211051Sandreas.hansson@arm.com } 130311051Sandreas.hansson@arm.com 130411051Sandreas.hansson@arm.com // allow invalidation responses originating from write-line 130511051Sandreas.hansson@arm.com // requests to be discarded 130611051Sandreas.hansson@arm.com bool is_invalidate = pkt->isInvalidate(); 130711051Sandreas.hansson@arm.com 130811051Sandreas.hansson@arm.com // First offset for critical word first calculations 130911051Sandreas.hansson@arm.com int initial_offset = initial_tgt->pkt->getOffset(blkSize); 131011051Sandreas.hansson@arm.com 131111051Sandreas.hansson@arm.com bool from_cache = false; 131211051Sandreas.hansson@arm.com MSHR::TargetList targets = mshr->extractServiceableTargets(pkt); 131311051Sandreas.hansson@arm.com for (auto &target: targets) { 131411051Sandreas.hansson@arm.com Packet *tgt_pkt = target.pkt; 131511051Sandreas.hansson@arm.com switch (target.source) { 131611051Sandreas.hansson@arm.com case MSHR::Target::FromCPU: 131711051Sandreas.hansson@arm.com Tick completion_time; 131811051Sandreas.hansson@arm.com // Here we charge on completion_time the delay of the xbar if the 131911051Sandreas.hansson@arm.com // packet comes from it, charged on headerDelay. 132011051Sandreas.hansson@arm.com completion_time = pkt->headerDelay; 132111051Sandreas.hansson@arm.com 132211051Sandreas.hansson@arm.com // Software prefetch handling for cache closest to core 132311051Sandreas.hansson@arm.com if (tgt_pkt->cmd.isSWPrefetch()) { 132411051Sandreas.hansson@arm.com // a software prefetch would have already been ack'd 132511051Sandreas.hansson@arm.com // immediately with dummy data so the core would be able to 132611051Sandreas.hansson@arm.com // retire it. This request completes right here, so we 132711051Sandreas.hansson@arm.com // deallocate it. 132811051Sandreas.hansson@arm.com delete tgt_pkt->req; 132911051Sandreas.hansson@arm.com delete tgt_pkt; 133011051Sandreas.hansson@arm.com break; // skip response 133111051Sandreas.hansson@arm.com } 133211051Sandreas.hansson@arm.com 133311051Sandreas.hansson@arm.com // keep track of whether we have responded to another 133411051Sandreas.hansson@arm.com // cache 133511051Sandreas.hansson@arm.com from_cache = from_cache || tgt_pkt->fromCache(); 133611051Sandreas.hansson@arm.com 133711051Sandreas.hansson@arm.com // unlike the other packet flows, where data is found in other 133811051Sandreas.hansson@arm.com // caches or memory and brought back, write-line requests always 133911051Sandreas.hansson@arm.com // have the data right away, so the above check for "is fill?" 134011051Sandreas.hansson@arm.com // cannot actually be determined until examining the stored MSHR 134111051Sandreas.hansson@arm.com // state. We "catch up" with that logic here, which is duplicated 134211051Sandreas.hansson@arm.com // from above. 134311051Sandreas.hansson@arm.com if (tgt_pkt->cmd == MemCmd::WriteLineReq) { 134411051Sandreas.hansson@arm.com assert(!is_error); 134511051Sandreas.hansson@arm.com // we got the block in a writable state, so promote 134611051Sandreas.hansson@arm.com // any deferred targets if possible 134711051Sandreas.hansson@arm.com mshr->promoteWritable(); 134811051Sandreas.hansson@arm.com // NB: we use the original packet here and not the response! 134911051Sandreas.hansson@arm.com blk = handleFill(tgt_pkt, blk, writebacks, 135011051Sandreas.hansson@arm.com targets.allocOnFill); 135111051Sandreas.hansson@arm.com assert(blk != nullptr); 135211051Sandreas.hansson@arm.com 135311051Sandreas.hansson@arm.com // treat as a fill, and discard the invalidation 135411051Sandreas.hansson@arm.com // response 135511051Sandreas.hansson@arm.com is_fill = true; 135611051Sandreas.hansson@arm.com is_invalidate = false; 135711051Sandreas.hansson@arm.com } 135811051Sandreas.hansson@arm.com 135911051Sandreas.hansson@arm.com if (is_fill) { 136011051Sandreas.hansson@arm.com satisfyRequest(tgt_pkt, blk, true, mshr->hasPostDowngrade()); 136111051Sandreas.hansson@arm.com 136211051Sandreas.hansson@arm.com // How many bytes past the first request is this one 136311051Sandreas.hansson@arm.com int transfer_offset = 136411051Sandreas.hansson@arm.com tgt_pkt->getOffset(blkSize) - initial_offset; 136511051Sandreas.hansson@arm.com if (transfer_offset < 0) { 136611051Sandreas.hansson@arm.com transfer_offset += blkSize; 136711051Sandreas.hansson@arm.com } 136811051Sandreas.hansson@arm.com 136911051Sandreas.hansson@arm.com // If not critical word (offset) return payloadDelay. 137011051Sandreas.hansson@arm.com // responseLatency is the latency of the return path 137111051Sandreas.hansson@arm.com // from lower level caches/memory to an upper level cache or 137211051Sandreas.hansson@arm.com // the core. 137311051Sandreas.hansson@arm.com completion_time += clockEdge(responseLatency) + 137411051Sandreas.hansson@arm.com (transfer_offset ? pkt->payloadDelay : 0); 137511051Sandreas.hansson@arm.com 137611051Sandreas.hansson@arm.com assert(!tgt_pkt->req->isUncacheable()); 137711051Sandreas.hansson@arm.com 137811051Sandreas.hansson@arm.com assert(tgt_pkt->req->masterId() < system->maxMasters()); 137911051Sandreas.hansson@arm.com missLatency[tgt_pkt->cmdToIndex()][tgt_pkt->req->masterId()] += 138011051Sandreas.hansson@arm.com completion_time - target.recvTime; 138111051Sandreas.hansson@arm.com } else if (pkt->cmd == MemCmd::UpgradeFailResp) { 138211051Sandreas.hansson@arm.com // failed StoreCond upgrade 138311051Sandreas.hansson@arm.com assert(tgt_pkt->cmd == MemCmd::StoreCondReq || 138411051Sandreas.hansson@arm.com tgt_pkt->cmd == MemCmd::StoreCondFailReq || 138511051Sandreas.hansson@arm.com tgt_pkt->cmd == MemCmd::SCUpgradeFailReq); 138611051Sandreas.hansson@arm.com // responseLatency is the latency of the return path 138711051Sandreas.hansson@arm.com // from lower level caches/memory to an upper level cache or 138811051Sandreas.hansson@arm.com // the core. 138911051Sandreas.hansson@arm.com completion_time += clockEdge(responseLatency) + 139011051Sandreas.hansson@arm.com pkt->payloadDelay; 139111051Sandreas.hansson@arm.com tgt_pkt->req->setExtraData(0); 139211051Sandreas.hansson@arm.com } else { 139311051Sandreas.hansson@arm.com // We are about to send a response to a cache above 139411051Sandreas.hansson@arm.com // that asked for an invalidation; we need to 139511051Sandreas.hansson@arm.com // invalidate our copy immediately as the most 139611051Sandreas.hansson@arm.com // up-to-date copy of the block will now be in the 139711051Sandreas.hansson@arm.com // cache above. It will also prevent this cache from 139811051Sandreas.hansson@arm.com // responding (if the block was previously dirty) to 139911051Sandreas.hansson@arm.com // snoops as they should snoop the caches above where 140011051Sandreas.hansson@arm.com // they will get the response from. 140111051Sandreas.hansson@arm.com if (is_invalidate && blk && blk->isValid()) { 140211051Sandreas.hansson@arm.com invalidateBlock(blk); 140311051Sandreas.hansson@arm.com } 140411051Sandreas.hansson@arm.com // not a cache fill, just forwarding response 140511051Sandreas.hansson@arm.com // responseLatency is the latency of the return path 140611051Sandreas.hansson@arm.com // from lower level cahces/memory to the core. 140711051Sandreas.hansson@arm.com completion_time += clockEdge(responseLatency) + 140811051Sandreas.hansson@arm.com pkt->payloadDelay; 140911051Sandreas.hansson@arm.com if (pkt->isRead() && !is_error) { 141011051Sandreas.hansson@arm.com // sanity check 141111051Sandreas.hansson@arm.com assert(pkt->getAddr() == tgt_pkt->getAddr()); 141211051Sandreas.hansson@arm.com assert(pkt->getSize() >= tgt_pkt->getSize()); 141311051Sandreas.hansson@arm.com 141411051Sandreas.hansson@arm.com tgt_pkt->setData(pkt->getConstPtr<uint8_t>()); 141511051Sandreas.hansson@arm.com } 141611051Sandreas.hansson@arm.com } 141711051Sandreas.hansson@arm.com tgt_pkt->makeTimingResponse(); 141811051Sandreas.hansson@arm.com // if this packet is an error copy that to the new packet 141911051Sandreas.hansson@arm.com if (is_error) 142011051Sandreas.hansson@arm.com tgt_pkt->copyError(pkt); 142111051Sandreas.hansson@arm.com if (tgt_pkt->cmd == MemCmd::ReadResp && 142211051Sandreas.hansson@arm.com (is_invalidate || mshr->hasPostInvalidate())) { 142311051Sandreas.hansson@arm.com // If intermediate cache got ReadRespWithInvalidate, 142411051Sandreas.hansson@arm.com // propagate that. Response should not have 142511051Sandreas.hansson@arm.com // isInvalidate() set otherwise. 142611051Sandreas.hansson@arm.com tgt_pkt->cmd = MemCmd::ReadRespWithInvalidate; 142711051Sandreas.hansson@arm.com DPRINTF(Cache, "%s: updated cmd to %s\n", __func__, 142811051Sandreas.hansson@arm.com tgt_pkt->print()); 142911051Sandreas.hansson@arm.com } 143011051Sandreas.hansson@arm.com // Reset the bus additional time as it is now accounted for 143111051Sandreas.hansson@arm.com tgt_pkt->headerDelay = tgt_pkt->payloadDelay = 0; 143211051Sandreas.hansson@arm.com cpuSidePort->schedTimingResp(tgt_pkt, completion_time, true); 143311051Sandreas.hansson@arm.com break; 143411051Sandreas.hansson@arm.com 143511051Sandreas.hansson@arm.com case MSHR::Target::FromPrefetcher: 143611051Sandreas.hansson@arm.com assert(tgt_pkt->cmd == MemCmd::HardPFReq); 143711051Sandreas.hansson@arm.com if (blk) 143811051Sandreas.hansson@arm.com blk->status |= BlkHWPrefetched; 143911051Sandreas.hansson@arm.com delete tgt_pkt->req; 144011051Sandreas.hansson@arm.com delete tgt_pkt; 144111051Sandreas.hansson@arm.com break; 144211051Sandreas.hansson@arm.com 144311051Sandreas.hansson@arm.com case MSHR::Target::FromSnoop: 144411051Sandreas.hansson@arm.com // I don't believe that a snoop can be in an error state 144511051Sandreas.hansson@arm.com assert(!is_error); 144611051Sandreas.hansson@arm.com // response to snoop request 144711051Sandreas.hansson@arm.com DPRINTF(Cache, "processing deferred snoop...\n"); 144811051Sandreas.hansson@arm.com // If the response is invalidating, a snooping target can 144911051Sandreas.hansson@arm.com // be satisfied if it is also invalidating. If the reponse is, not 145011051Sandreas.hansson@arm.com // only invalidating, but more specifically an InvalidateResp, the 145111051Sandreas.hansson@arm.com // MSHR was created due to an InvalidateReq and a cache above is 145211051Sandreas.hansson@arm.com // waiting to satisfy a WriteLineReq. In this case even an 145311051Sandreas.hansson@arm.com // non-invalidating snoop is added as a target here since this is 145411051Sandreas.hansson@arm.com // the ordering point. When the InvalidateResp reaches this cache, 145511051Sandreas.hansson@arm.com // the snooping target will snoop further the cache above with the 145611051Sandreas.hansson@arm.com // WriteLineReq. 145711051Sandreas.hansson@arm.com assert(!(is_invalidate && 145811051Sandreas.hansson@arm.com pkt->cmd != MemCmd::InvalidateResp && 145911051Sandreas.hansson@arm.com !mshr->hasPostInvalidate())); 146011051Sandreas.hansson@arm.com handleSnoop(tgt_pkt, blk, true, true, mshr->hasPostInvalidate()); 146111051Sandreas.hansson@arm.com break; 146211051Sandreas.hansson@arm.com 146311051Sandreas.hansson@arm.com default: 146411051Sandreas.hansson@arm.com panic("Illegal target->source enum %d\n", target.source); 146511051Sandreas.hansson@arm.com } 146611051Sandreas.hansson@arm.com } 146711051Sandreas.hansson@arm.com 146811051Sandreas.hansson@arm.com maintainClusivity(from_cache, blk); 146911051Sandreas.hansson@arm.com 147011051Sandreas.hansson@arm.com if (blk && blk->isValid()) { 147111051Sandreas.hansson@arm.com // an invalidate response stemming from a write line request 147211051Sandreas.hansson@arm.com // should not invalidate the block, so check if the 147311051Sandreas.hansson@arm.com // invalidation should be discarded 147411051Sandreas.hansson@arm.com if (is_invalidate || mshr->hasPostInvalidate()) { 147511051Sandreas.hansson@arm.com invalidateBlock(blk); 147611051Sandreas.hansson@arm.com } else if (mshr->hasPostDowngrade()) { 147711051Sandreas.hansson@arm.com blk->status &= ~BlkWritable; 147811051Sandreas.hansson@arm.com } 147911051Sandreas.hansson@arm.com } 148011051Sandreas.hansson@arm.com 148111051Sandreas.hansson@arm.com if (mshr->promoteDeferredTargets()) { 148211051Sandreas.hansson@arm.com // avoid later read getting stale data while write miss is 148311051Sandreas.hansson@arm.com // outstanding.. see comment in timingAccess() 148411051Sandreas.hansson@arm.com if (blk) { 148511051Sandreas.hansson@arm.com blk->status &= ~BlkReadable; 148611051Sandreas.hansson@arm.com } 148711051Sandreas.hansson@arm.com mshrQueue.markPending(mshr); 148811051Sandreas.hansson@arm.com schedMemSideSendEvent(clockEdge() + pkt->payloadDelay); 148911051Sandreas.hansson@arm.com } else { 149011051Sandreas.hansson@arm.com mshrQueue.deallocate(mshr); 149111051Sandreas.hansson@arm.com if (wasFull && !mshrQueue.isFull()) { 149211051Sandreas.hansson@arm.com clearBlocked(Blocked_NoMSHRs); 149311051Sandreas.hansson@arm.com } 149411051Sandreas.hansson@arm.com 149511051Sandreas.hansson@arm.com // Request the bus for a prefetch if this deallocation freed enough 149611051Sandreas.hansson@arm.com // MSHRs for a prefetch to take place 149711051Sandreas.hansson@arm.com if (prefetcher && mshrQueue.canPrefetch()) { 149811051Sandreas.hansson@arm.com Tick next_pf_time = std::max(prefetcher->nextPrefetchReadyTime(), 149911051Sandreas.hansson@arm.com clockEdge()); 150011051Sandreas.hansson@arm.com if (next_pf_time != MaxTick) 150111051Sandreas.hansson@arm.com schedMemSideSendEvent(next_pf_time); 150211051Sandreas.hansson@arm.com } 150311051Sandreas.hansson@arm.com } 150411051Sandreas.hansson@arm.com // reset the xbar additional timinig as it is now accounted for 150511051Sandreas.hansson@arm.com pkt->headerDelay = pkt->payloadDelay = 0; 150611051Sandreas.hansson@arm.com 150711051Sandreas.hansson@arm.com // copy writebacks to write buffer 150811051Sandreas.hansson@arm.com doWritebacks(writebacks, forward_time); 150911051Sandreas.hansson@arm.com 151011051Sandreas.hansson@arm.com // if we used temp block, check to see if its valid and then clear it out 151111051Sandreas.hansson@arm.com if (blk == tempBlock && tempBlock->isValid()) { 151211051Sandreas.hansson@arm.com // We use forwardLatency here because we are copying 151311051Sandreas.hansson@arm.com // Writebacks/CleanEvicts to write buffer. It specifies the latency to 151411051Sandreas.hansson@arm.com // allocate an internal buffer and to schedule an event to the 151511051Sandreas.hansson@arm.com // queued port. 151611051Sandreas.hansson@arm.com if (blk->isDirty() || writebackClean) { 151711051Sandreas.hansson@arm.com PacketPtr wbPkt = writebackBlk(blk); 151811051Sandreas.hansson@arm.com allocateWriteBuffer(wbPkt, forward_time); 151911051Sandreas.hansson@arm.com // Set BLOCK_CACHED flag if cached above. 152011051Sandreas.hansson@arm.com if (isCachedAbove(wbPkt)) 152111051Sandreas.hansson@arm.com wbPkt->setBlockCached(); 152211051Sandreas.hansson@arm.com } else { 152311051Sandreas.hansson@arm.com PacketPtr wcPkt = cleanEvictBlk(blk); 152411051Sandreas.hansson@arm.com // Check to see if block is cached above. If not allocate 152511051Sandreas.hansson@arm.com // write buffer 152611051Sandreas.hansson@arm.com if (isCachedAbove(wcPkt)) 152711051Sandreas.hansson@arm.com delete wcPkt; 152811051Sandreas.hansson@arm.com else 152911051Sandreas.hansson@arm.com allocateWriteBuffer(wcPkt, forward_time); 153011051Sandreas.hansson@arm.com } 153111051Sandreas.hansson@arm.com invalidateBlock(blk); 153211051Sandreas.hansson@arm.com } 153311051Sandreas.hansson@arm.com 153411051Sandreas.hansson@arm.com DPRINTF(CacheVerbose, "%s: Leaving with %s\n", __func__, pkt->print()); 153511051Sandreas.hansson@arm.com delete pkt; 153611051Sandreas.hansson@arm.com} 153711051Sandreas.hansson@arm.com 153811051Sandreas.hansson@arm.comPacketPtr 153911051Sandreas.hansson@arm.comCache::writebackBlk(CacheBlk *blk) 154011051Sandreas.hansson@arm.com{ 154111051Sandreas.hansson@arm.com chatty_assert(!isReadOnly || writebackClean, 154211051Sandreas.hansson@arm.com "Writeback from read-only cache"); 154311051Sandreas.hansson@arm.com assert(blk && blk->isValid() && (blk->isDirty() || writebackClean)); 154411051Sandreas.hansson@arm.com 154511051Sandreas.hansson@arm.com writebacks[Request::wbMasterId]++; 154611051Sandreas.hansson@arm.com 154711051Sandreas.hansson@arm.com Request *req = new Request(tags->regenerateBlkAddr(blk->tag, blk->set), 154811051Sandreas.hansson@arm.com blkSize, 0, Request::wbMasterId); 154911051Sandreas.hansson@arm.com if (blk->isSecure()) 155011051Sandreas.hansson@arm.com req->setFlags(Request::SECURE); 155111051Sandreas.hansson@arm.com 155211051Sandreas.hansson@arm.com req->taskId(blk->task_id); 155311051Sandreas.hansson@arm.com blk->task_id= ContextSwitchTaskId::Unknown; 155411051Sandreas.hansson@arm.com blk->tickInserted = curTick(); 155511051Sandreas.hansson@arm.com 155611051Sandreas.hansson@arm.com PacketPtr pkt = 155711051Sandreas.hansson@arm.com new Packet(req, blk->isDirty() ? 155811051Sandreas.hansson@arm.com MemCmd::WritebackDirty : MemCmd::WritebackClean); 155911051Sandreas.hansson@arm.com 156011051Sandreas.hansson@arm.com DPRINTF(Cache, "Create Writeback %s writable: %d, dirty: %d\n", 156111051Sandreas.hansson@arm.com pkt->print(), blk->isWritable(), blk->isDirty()); 156211051Sandreas.hansson@arm.com 156311051Sandreas.hansson@arm.com if (blk->isWritable()) { 156411051Sandreas.hansson@arm.com // not asserting shared means we pass the block in modified 156511051Sandreas.hansson@arm.com // state, mark our own block non-writeable 156611051Sandreas.hansson@arm.com blk->status &= ~BlkWritable; 156711051Sandreas.hansson@arm.com } else { 156811051Sandreas.hansson@arm.com // we are in the Owned state, tell the receiver 156911051Sandreas.hansson@arm.com pkt->setHasSharers(); 157011051Sandreas.hansson@arm.com } 157111051Sandreas.hansson@arm.com 157211051Sandreas.hansson@arm.com // make sure the block is not marked dirty 157311051Sandreas.hansson@arm.com blk->status &= ~BlkDirty; 157411051Sandreas.hansson@arm.com 157511051Sandreas.hansson@arm.com pkt->allocate(); 157611051Sandreas.hansson@arm.com std::memcpy(pkt->getPtr<uint8_t>(), blk->data, blkSize); 157711051Sandreas.hansson@arm.com 157811051Sandreas.hansson@arm.com return pkt; 157911051Sandreas.hansson@arm.com} 158011051Sandreas.hansson@arm.com 158111051Sandreas.hansson@arm.comPacketPtr 158211051Sandreas.hansson@arm.comCache::cleanEvictBlk(CacheBlk *blk) 158311051Sandreas.hansson@arm.com{ 158411051Sandreas.hansson@arm.com assert(!writebackClean); 158511051Sandreas.hansson@arm.com assert(blk && blk->isValid() && !blk->isDirty()); 158611051Sandreas.hansson@arm.com // Creating a zero sized write, a message to the snoop filter 158711051Sandreas.hansson@arm.com Request *req = 158811051Sandreas.hansson@arm.com new Request(tags->regenerateBlkAddr(blk->tag, blk->set), blkSize, 0, 158911051Sandreas.hansson@arm.com Request::wbMasterId); 159011051Sandreas.hansson@arm.com if (blk->isSecure()) 159111051Sandreas.hansson@arm.com req->setFlags(Request::SECURE); 159211051Sandreas.hansson@arm.com 159311051Sandreas.hansson@arm.com req->taskId(blk->task_id); 159411051Sandreas.hansson@arm.com blk->task_id = ContextSwitchTaskId::Unknown; 159511051Sandreas.hansson@arm.com blk->tickInserted = curTick(); 159611051Sandreas.hansson@arm.com 159711051Sandreas.hansson@arm.com PacketPtr pkt = new Packet(req, MemCmd::CleanEvict); 159811051Sandreas.hansson@arm.com pkt->allocate(); 159911051Sandreas.hansson@arm.com DPRINTF(Cache, "Create CleanEvict %s\n", pkt->print()); 160011051Sandreas.hansson@arm.com 160111051Sandreas.hansson@arm.com return pkt; 160211051Sandreas.hansson@arm.com} 160311051Sandreas.hansson@arm.com 160411051Sandreas.hansson@arm.comvoid 160511051Sandreas.hansson@arm.comCache::memWriteback() 160611051Sandreas.hansson@arm.com{ 160711051Sandreas.hansson@arm.com CacheBlkVisitorWrapper visitor(*this, &Cache::writebackVisitor); 160811051Sandreas.hansson@arm.com tags->forEachBlk(visitor); 160911051Sandreas.hansson@arm.com} 161011051Sandreas.hansson@arm.com 161111051Sandreas.hansson@arm.comvoid 161211051Sandreas.hansson@arm.comCache::memInvalidate() 161311051Sandreas.hansson@arm.com{ 161411051Sandreas.hansson@arm.com CacheBlkVisitorWrapper visitor(*this, &Cache::invalidateVisitor); 161511051Sandreas.hansson@arm.com tags->forEachBlk(visitor); 161611051Sandreas.hansson@arm.com} 161711051Sandreas.hansson@arm.com 161811051Sandreas.hansson@arm.combool 161911051Sandreas.hansson@arm.comCache::isDirty() const 162011051Sandreas.hansson@arm.com{ 162111051Sandreas.hansson@arm.com CacheBlkIsDirtyVisitor visitor; 162211051Sandreas.hansson@arm.com tags->forEachBlk(visitor); 162311051Sandreas.hansson@arm.com 162411051Sandreas.hansson@arm.com return visitor.isDirty(); 162511051Sandreas.hansson@arm.com} 162611051Sandreas.hansson@arm.com 162711051Sandreas.hansson@arm.combool 162811051Sandreas.hansson@arm.comCache::writebackVisitor(CacheBlk &blk) 162911051Sandreas.hansson@arm.com{ 163011051Sandreas.hansson@arm.com if (blk.isDirty()) { 163111051Sandreas.hansson@arm.com assert(blk.isValid()); 163211051Sandreas.hansson@arm.com 163311051Sandreas.hansson@arm.com Request request(tags->regenerateBlkAddr(blk.tag, blk.set), 163411051Sandreas.hansson@arm.com blkSize, 0, Request::funcMasterId); 163511051Sandreas.hansson@arm.com request.taskId(blk.task_id); 163611051Sandreas.hansson@arm.com if (blk.isSecure()) { 163711051Sandreas.hansson@arm.com request.setFlags(Request::SECURE); 163811051Sandreas.hansson@arm.com } 163911051Sandreas.hansson@arm.com 164011051Sandreas.hansson@arm.com Packet packet(&request, MemCmd::WriteReq); 164111051Sandreas.hansson@arm.com packet.dataStatic(blk.data); 164211051Sandreas.hansson@arm.com 164311051Sandreas.hansson@arm.com memSidePort->sendFunctional(&packet); 164411051Sandreas.hansson@arm.com 164511051Sandreas.hansson@arm.com blk.status &= ~BlkDirty; 164611051Sandreas.hansson@arm.com } 164711051Sandreas.hansson@arm.com 164811051Sandreas.hansson@arm.com return true; 164911051Sandreas.hansson@arm.com} 165011051Sandreas.hansson@arm.com 165111051Sandreas.hansson@arm.combool 165211051Sandreas.hansson@arm.comCache::invalidateVisitor(CacheBlk &blk) 165311051Sandreas.hansson@arm.com{ 165411051Sandreas.hansson@arm.com 165511051Sandreas.hansson@arm.com if (blk.isDirty()) 165611051Sandreas.hansson@arm.com warn_once("Invalidating dirty cache lines. Expect things to break.\n"); 165711051Sandreas.hansson@arm.com 165811051Sandreas.hansson@arm.com if (blk.isValid()) { 165911051Sandreas.hansson@arm.com assert(!blk.isDirty()); 166011051Sandreas.hansson@arm.com invalidateBlock(&blk); 166111051Sandreas.hansson@arm.com } 166211051Sandreas.hansson@arm.com 166311051Sandreas.hansson@arm.com return true; 166411051Sandreas.hansson@arm.com} 166511051Sandreas.hansson@arm.com 166611051Sandreas.hansson@arm.comCacheBlk* 166711051Sandreas.hansson@arm.comCache::allocateBlock(Addr addr, bool is_secure, PacketList &writebacks) 166811051Sandreas.hansson@arm.com{ 166911051Sandreas.hansson@arm.com CacheBlk *blk = tags->findVictim(addr); 167011051Sandreas.hansson@arm.com 167111051Sandreas.hansson@arm.com // It is valid to return nullptr if there is no victim 167211051Sandreas.hansson@arm.com if (!blk) 167311051Sandreas.hansson@arm.com return nullptr; 167411051Sandreas.hansson@arm.com 167511051Sandreas.hansson@arm.com if (blk->isValid()) { 167611051Sandreas.hansson@arm.com Addr repl_addr = tags->regenerateBlkAddr(blk->tag, blk->set); 167711051Sandreas.hansson@arm.com MSHR *repl_mshr = mshrQueue.findMatch(repl_addr, blk->isSecure()); 167811051Sandreas.hansson@arm.com if (repl_mshr) { 167911051Sandreas.hansson@arm.com // must be an outstanding upgrade request 168011051Sandreas.hansson@arm.com // on a block we're about to replace... 168111051Sandreas.hansson@arm.com assert(!blk->isWritable() || blk->isDirty()); 168211051Sandreas.hansson@arm.com assert(repl_mshr->needsWritable()); 168311051Sandreas.hansson@arm.com // too hard to replace block with transient state 168411051Sandreas.hansson@arm.com // allocation failed, block not inserted 168511051Sandreas.hansson@arm.com return nullptr; 168611051Sandreas.hansson@arm.com } else { 168711051Sandreas.hansson@arm.com DPRINTF(Cache, "replacement: replacing %#llx (%s) with %#llx " 168811051Sandreas.hansson@arm.com "(%s): %s\n", repl_addr, blk->isSecure() ? "s" : "ns", 168911051Sandreas.hansson@arm.com addr, is_secure ? "s" : "ns", 169011051Sandreas.hansson@arm.com blk->isDirty() ? "writeback" : "clean"); 169111051Sandreas.hansson@arm.com 169211051Sandreas.hansson@arm.com if (blk->wasPrefetched()) { 169311051Sandreas.hansson@arm.com unusedPrefetches++; 169411051Sandreas.hansson@arm.com } 169511051Sandreas.hansson@arm.com // Will send up Writeback/CleanEvict snoops via isCachedAbove 169611051Sandreas.hansson@arm.com // when pushing this writeback list into the write buffer. 169711051Sandreas.hansson@arm.com if (blk->isDirty() || writebackClean) { 169811051Sandreas.hansson@arm.com // Save writeback packet for handling by caller 169911051Sandreas.hansson@arm.com writebacks.push_back(writebackBlk(blk)); 170011051Sandreas.hansson@arm.com } else { 170111051Sandreas.hansson@arm.com writebacks.push_back(cleanEvictBlk(blk)); 170211051Sandreas.hansson@arm.com } 170311051Sandreas.hansson@arm.com } 170411051Sandreas.hansson@arm.com } 170511051Sandreas.hansson@arm.com 170611051Sandreas.hansson@arm.com return blk; 170711051Sandreas.hansson@arm.com} 170811051Sandreas.hansson@arm.com 170911051Sandreas.hansson@arm.comvoid 171011051Sandreas.hansson@arm.comCache::invalidateBlock(CacheBlk *blk) 171111051Sandreas.hansson@arm.com{ 171211051Sandreas.hansson@arm.com if (blk != tempBlock) 171311051Sandreas.hansson@arm.com tags->invalidate(blk); 171411051Sandreas.hansson@arm.com blk->invalidate(); 171511051Sandreas.hansson@arm.com} 171611051Sandreas.hansson@arm.com 171711051Sandreas.hansson@arm.com// Note that the reason we return a list of writebacks rather than 171811051Sandreas.hansson@arm.com// inserting them directly in the write buffer is that this function 171911051Sandreas.hansson@arm.com// is called by both atomic and timing-mode accesses, and in atomic 172011051Sandreas.hansson@arm.com// mode we don't mess with the write buffer (we just perform the 172111051Sandreas.hansson@arm.com// writebacks atomically once the original request is complete). 172211051Sandreas.hansson@arm.comCacheBlk* 172311051Sandreas.hansson@arm.comCache::handleFill(PacketPtr pkt, CacheBlk *blk, PacketList &writebacks, 172411051Sandreas.hansson@arm.com bool allocate) 172511051Sandreas.hansson@arm.com{ 172611051Sandreas.hansson@arm.com assert(pkt->isResponse() || pkt->cmd == MemCmd::WriteLineReq); 172711051Sandreas.hansson@arm.com Addr addr = pkt->getAddr(); 172811051Sandreas.hansson@arm.com bool is_secure = pkt->isSecure(); 172911051Sandreas.hansson@arm.com#if TRACING_ON 173011051Sandreas.hansson@arm.com CacheBlk::State old_state = blk ? blk->status : 0; 173111051Sandreas.hansson@arm.com#endif 173211051Sandreas.hansson@arm.com 173311051Sandreas.hansson@arm.com // When handling a fill, we should have no writes to this line. 173411051Sandreas.hansson@arm.com assert(addr == pkt->getBlockAddr(blkSize)); 173511051Sandreas.hansson@arm.com assert(!writeBuffer.findMatch(addr, is_secure)); 173611051Sandreas.hansson@arm.com 173711051Sandreas.hansson@arm.com if (blk == nullptr) { 173811051Sandreas.hansson@arm.com // better have read new data... 173911051Sandreas.hansson@arm.com assert(pkt->hasData()); 174011051Sandreas.hansson@arm.com 174111051Sandreas.hansson@arm.com // only read responses and write-line requests have data; 174211051Sandreas.hansson@arm.com // note that we don't write the data here for write-line - that 174311051Sandreas.hansson@arm.com // happens in the subsequent call to satisfyRequest 174411051Sandreas.hansson@arm.com assert(pkt->isRead() || pkt->cmd == MemCmd::WriteLineReq); 174511051Sandreas.hansson@arm.com 174611051Sandreas.hansson@arm.com // need to do a replacement if allocating, otherwise we stick 174711051Sandreas.hansson@arm.com // with the temporary storage 174811051Sandreas.hansson@arm.com blk = allocate ? allocateBlock(addr, is_secure, writebacks) : nullptr; 174911051Sandreas.hansson@arm.com 175011051Sandreas.hansson@arm.com if (blk == nullptr) { 175111051Sandreas.hansson@arm.com // No replaceable block or a mostly exclusive 175211051Sandreas.hansson@arm.com // cache... just use temporary storage to complete the 175311051Sandreas.hansson@arm.com // current request and then get rid of it 175411051Sandreas.hansson@arm.com assert(!tempBlock->isValid()); 175511051Sandreas.hansson@arm.com blk = tempBlock; 175611051Sandreas.hansson@arm.com tempBlock->set = tags->extractSet(addr); 175711051Sandreas.hansson@arm.com tempBlock->tag = tags->extractTag(addr); 175811051Sandreas.hansson@arm.com // @todo: set security state as well... 175911051Sandreas.hansson@arm.com DPRINTF(Cache, "using temp block for %#llx (%s)\n", addr, 176011051Sandreas.hansson@arm.com is_secure ? "s" : "ns"); 176111051Sandreas.hansson@arm.com } else { 176211051Sandreas.hansson@arm.com tags->insertBlock(pkt, blk); 176311051Sandreas.hansson@arm.com } 176411051Sandreas.hansson@arm.com 176511051Sandreas.hansson@arm.com // we should never be overwriting a valid block 176611051Sandreas.hansson@arm.com assert(!blk->isValid()); 176711051Sandreas.hansson@arm.com } else { 176811051Sandreas.hansson@arm.com // existing block... probably an upgrade 176911051Sandreas.hansson@arm.com assert(blk->tag == tags->extractTag(addr)); 177011051Sandreas.hansson@arm.com // either we're getting new data or the block should already be valid 177111051Sandreas.hansson@arm.com assert(pkt->hasData() || blk->isValid()); 177211051Sandreas.hansson@arm.com // don't clear block status... if block is already dirty we 177311051Sandreas.hansson@arm.com // don't want to lose that 177411051Sandreas.hansson@arm.com } 177511051Sandreas.hansson@arm.com 177611051Sandreas.hansson@arm.com if (is_secure) 177711051Sandreas.hansson@arm.com blk->status |= BlkSecure; 177811051Sandreas.hansson@arm.com blk->status |= BlkValid | BlkReadable; 177911051Sandreas.hansson@arm.com 178011051Sandreas.hansson@arm.com // sanity check for whole-line writes, which should always be 178111051Sandreas.hansson@arm.com // marked as writable as part of the fill, and then later marked 178211051Sandreas.hansson@arm.com // dirty as part of satisfyRequest 178311051Sandreas.hansson@arm.com if (pkt->cmd == MemCmd::WriteLineReq) { 178411051Sandreas.hansson@arm.com assert(!pkt->hasSharers()); 178511051Sandreas.hansson@arm.com } 178611051Sandreas.hansson@arm.com 178711051Sandreas.hansson@arm.com // here we deal with setting the appropriate state of the line, 178811051Sandreas.hansson@arm.com // and we start by looking at the hasSharers flag, and ignore the 178911051Sandreas.hansson@arm.com // cacheResponding flag (normally signalling dirty data) if the 179011051Sandreas.hansson@arm.com // packet has sharers, thus the line is never allocated as Owned 179111051Sandreas.hansson@arm.com // (dirty but not writable), and always ends up being either 179211051Sandreas.hansson@arm.com // Shared, Exclusive or Modified, see Packet::setCacheResponding 179311051Sandreas.hansson@arm.com // for more details 179411051Sandreas.hansson@arm.com if (!pkt->hasSharers()) { 179511051Sandreas.hansson@arm.com // we could get a writable line from memory (rather than a 179611051Sandreas.hansson@arm.com // cache) even in a read-only cache, note that we set this bit 179711051Sandreas.hansson@arm.com // even for a read-only cache, possibly revisit this decision 179811051Sandreas.hansson@arm.com blk->status |= BlkWritable; 179911051Sandreas.hansson@arm.com 180011051Sandreas.hansson@arm.com // check if we got this via cache-to-cache transfer (i.e., from a 180111051Sandreas.hansson@arm.com // cache that had the block in Modified or Owned state) 180211051Sandreas.hansson@arm.com if (pkt->cacheResponding()) { 180311051Sandreas.hansson@arm.com // we got the block in Modified state, and invalidated the 180411051Sandreas.hansson@arm.com // owners copy 180511051Sandreas.hansson@arm.com blk->status |= BlkDirty; 180611051Sandreas.hansson@arm.com 180711051Sandreas.hansson@arm.com chatty_assert(!isReadOnly, "Should never see dirty snoop response " 180811051Sandreas.hansson@arm.com "in read-only cache %s\n", name()); 180911051Sandreas.hansson@arm.com } 181011051Sandreas.hansson@arm.com } 181111051Sandreas.hansson@arm.com 181211051Sandreas.hansson@arm.com DPRINTF(Cache, "Block addr %#llx (%s) moving from state %x to %s\n", 181311051Sandreas.hansson@arm.com addr, is_secure ? "s" : "ns", old_state, blk->print()); 181411051Sandreas.hansson@arm.com 181511051Sandreas.hansson@arm.com // if we got new data, copy it in (checking for a read response 181611051Sandreas.hansson@arm.com // and a response that has data is the same in the end) 181711051Sandreas.hansson@arm.com if (pkt->isRead()) { 181811051Sandreas.hansson@arm.com // sanity checks 181911051Sandreas.hansson@arm.com assert(pkt->hasData()); 182011051Sandreas.hansson@arm.com assert(pkt->getSize() == blkSize); 182111051Sandreas.hansson@arm.com 182211051Sandreas.hansson@arm.com std::memcpy(blk->data, pkt->getConstPtr<uint8_t>(), blkSize); 182311051Sandreas.hansson@arm.com } 182411051Sandreas.hansson@arm.com // We pay for fillLatency here. 182511051Sandreas.hansson@arm.com blk->whenReady = clockEdge() + fillLatency * clockPeriod() + 182611051Sandreas.hansson@arm.com pkt->payloadDelay; 182711051Sandreas.hansson@arm.com 182811051Sandreas.hansson@arm.com return blk; 182911051Sandreas.hansson@arm.com} 183011051Sandreas.hansson@arm.com 183111051Sandreas.hansson@arm.com 183211051Sandreas.hansson@arm.com///////////////////////////////////////////////////// 183311051Sandreas.hansson@arm.com// 183411051Sandreas.hansson@arm.com// Snoop path: requests coming in from the memory side 183511051Sandreas.hansson@arm.com// 183611051Sandreas.hansson@arm.com///////////////////////////////////////////////////// 183711051Sandreas.hansson@arm.com 183811051Sandreas.hansson@arm.comvoid 183911051Sandreas.hansson@arm.comCache::doTimingSupplyResponse(PacketPtr req_pkt, const uint8_t *blk_data, 184011051Sandreas.hansson@arm.com bool already_copied, bool pending_inval) 184111051Sandreas.hansson@arm.com{ 184211051Sandreas.hansson@arm.com // sanity check 184311051Sandreas.hansson@arm.com assert(req_pkt->isRequest()); 184411051Sandreas.hansson@arm.com assert(req_pkt->needsResponse()); 184511051Sandreas.hansson@arm.com 184611051Sandreas.hansson@arm.com DPRINTF(Cache, "%s: for %s\n", __func__, req_pkt->print()); 184711051Sandreas.hansson@arm.com // timing-mode snoop responses require a new packet, unless we 184811051Sandreas.hansson@arm.com // already made a copy... 184911051Sandreas.hansson@arm.com PacketPtr pkt = req_pkt; 185011051Sandreas.hansson@arm.com if (!already_copied) 185111051Sandreas.hansson@arm.com // do not clear flags, and allocate space for data if the 185211051Sandreas.hansson@arm.com // packet needs it (the only packets that carry data are read 185311051Sandreas.hansson@arm.com // responses) 185411051Sandreas.hansson@arm.com pkt = new Packet(req_pkt, false, req_pkt->isRead()); 185511051Sandreas.hansson@arm.com 185611051Sandreas.hansson@arm.com assert(req_pkt->req->isUncacheable() || req_pkt->isInvalidate() || 185711051Sandreas.hansson@arm.com pkt->hasSharers()); 185811051Sandreas.hansson@arm.com pkt->makeTimingResponse(); 185911051Sandreas.hansson@arm.com if (pkt->isRead()) { 186011051Sandreas.hansson@arm.com pkt->setDataFromBlock(blk_data, blkSize); 186111051Sandreas.hansson@arm.com } 186211051Sandreas.hansson@arm.com if (pkt->cmd == MemCmd::ReadResp && pending_inval) { 186311051Sandreas.hansson@arm.com // Assume we defer a response to a read from a far-away cache 186411051Sandreas.hansson@arm.com // A, then later defer a ReadExcl from a cache B on the same 186511051Sandreas.hansson@arm.com // bus as us. We'll assert cacheResponding in both cases, but 186611051Sandreas.hansson@arm.com // in the latter case cacheResponding will keep the 186711051Sandreas.hansson@arm.com // invalidation from reaching cache A. This special response 186811051Sandreas.hansson@arm.com // tells cache A that it gets the block to satisfy its read, 186911051Sandreas.hansson@arm.com // but must immediately invalidate it. 187011051Sandreas.hansson@arm.com pkt->cmd = MemCmd::ReadRespWithInvalidate; 187111051Sandreas.hansson@arm.com } 187211051Sandreas.hansson@arm.com // Here we consider forward_time, paying for just forward latency and 187311051Sandreas.hansson@arm.com // also charging the delay provided by the xbar. 187411051Sandreas.hansson@arm.com // forward_time is used as send_time in next allocateWriteBuffer(). 187511051Sandreas.hansson@arm.com Tick forward_time = clockEdge(forwardLatency) + pkt->headerDelay; 187611051Sandreas.hansson@arm.com // Here we reset the timing of the packet. 187711051Sandreas.hansson@arm.com pkt->headerDelay = pkt->payloadDelay = 0; 187811051Sandreas.hansson@arm.com DPRINTF(CacheVerbose, "%s: created response: %s tick: %lu\n", __func__, 187911051Sandreas.hansson@arm.com pkt->print(), forward_time); 188011051Sandreas.hansson@arm.com memSidePort->schedTimingSnoopResp(pkt, forward_time, true); 188111051Sandreas.hansson@arm.com} 188211051Sandreas.hansson@arm.com 188311051Sandreas.hansson@arm.comuint32_t 188411051Sandreas.hansson@arm.comCache::handleSnoop(PacketPtr pkt, CacheBlk *blk, bool is_timing, 188511051Sandreas.hansson@arm.com bool is_deferred, bool pending_inval) 188611051Sandreas.hansson@arm.com{ 188711051Sandreas.hansson@arm.com DPRINTF(CacheVerbose, "%s: for %s\n", __func__, pkt->print()); 188811051Sandreas.hansson@arm.com // deferred snoops can only happen in timing mode 188911051Sandreas.hansson@arm.com assert(!(is_deferred && !is_timing)); 189011051Sandreas.hansson@arm.com // pending_inval only makes sense on deferred snoops 189111051Sandreas.hansson@arm.com assert(!(pending_inval && !is_deferred)); 189211051Sandreas.hansson@arm.com assert(pkt->isRequest()); 189311051Sandreas.hansson@arm.com 189411051Sandreas.hansson@arm.com // the packet may get modified if we or a forwarded snooper 189511051Sandreas.hansson@arm.com // responds in atomic mode, so remember a few things about the 189611051Sandreas.hansson@arm.com // original packet up front 189711051Sandreas.hansson@arm.com bool invalidate = pkt->isInvalidate(); 189811051Sandreas.hansson@arm.com bool M5_VAR_USED needs_writable = pkt->needsWritable(); 189911051Sandreas.hansson@arm.com 190011051Sandreas.hansson@arm.com // at the moment we could get an uncacheable write which does not 190111051Sandreas.hansson@arm.com // have the invalidate flag, and we need a suitable way of dealing 190211051Sandreas.hansson@arm.com // with this case 190311051Sandreas.hansson@arm.com panic_if(invalidate && pkt->req->isUncacheable(), 190411051Sandreas.hansson@arm.com "%s got an invalidating uncacheable snoop request %s", 190511051Sandreas.hansson@arm.com name(), pkt->print()); 190611051Sandreas.hansson@arm.com 190711051Sandreas.hansson@arm.com uint32_t snoop_delay = 0; 190811051Sandreas.hansson@arm.com 190911051Sandreas.hansson@arm.com if (forwardSnoops) { 191011051Sandreas.hansson@arm.com // first propagate snoop upward to see if anyone above us wants to 191111051Sandreas.hansson@arm.com // handle it. save & restore packet src since it will get 191211051Sandreas.hansson@arm.com // rewritten to be relative to cpu-side bus (if any) 191311051Sandreas.hansson@arm.com bool alreadyResponded = pkt->cacheResponding(); 191411051Sandreas.hansson@arm.com if (is_timing) { 191511051Sandreas.hansson@arm.com // copy the packet so that we can clear any flags before 191611051Sandreas.hansson@arm.com // forwarding it upwards, we also allocate data (passing 191711051Sandreas.hansson@arm.com // the pointer along in case of static data), in case 191811051Sandreas.hansson@arm.com // there is a snoop hit in upper levels 191911051Sandreas.hansson@arm.com Packet snoopPkt(pkt, true, true); 192011051Sandreas.hansson@arm.com snoopPkt.setExpressSnoop(); 192111051Sandreas.hansson@arm.com // the snoop packet does not need to wait any additional 192211051Sandreas.hansson@arm.com // time 192311051Sandreas.hansson@arm.com snoopPkt.headerDelay = snoopPkt.payloadDelay = 0; 192411051Sandreas.hansson@arm.com cpuSidePort->sendTimingSnoopReq(&snoopPkt); 192511051Sandreas.hansson@arm.com 192611051Sandreas.hansson@arm.com // add the header delay (including crossbar and snoop 192711051Sandreas.hansson@arm.com // delays) of the upward snoop to the snoop delay for this 192811051Sandreas.hansson@arm.com // cache 192911051Sandreas.hansson@arm.com snoop_delay += snoopPkt.headerDelay; 193011051Sandreas.hansson@arm.com 193111051Sandreas.hansson@arm.com if (snoopPkt.cacheResponding()) { 193211051Sandreas.hansson@arm.com // cache-to-cache response from some upper cache 193311051Sandreas.hansson@arm.com assert(!alreadyResponded); 193411051Sandreas.hansson@arm.com pkt->setCacheResponding(); 193511051Sandreas.hansson@arm.com } 193611051Sandreas.hansson@arm.com // upstream cache has the block, or has an outstanding 193711051Sandreas.hansson@arm.com // MSHR, pass the flag on 193811051Sandreas.hansson@arm.com if (snoopPkt.hasSharers()) { 193911051Sandreas.hansson@arm.com pkt->setHasSharers(); 194011051Sandreas.hansson@arm.com } 194111051Sandreas.hansson@arm.com // If this request is a prefetch or clean evict and an upper level 194211051Sandreas.hansson@arm.com // signals block present, make sure to propagate the block 194311051Sandreas.hansson@arm.com // presence to the requester. 194411051Sandreas.hansson@arm.com if (snoopPkt.isBlockCached()) { 194511051Sandreas.hansson@arm.com pkt->setBlockCached(); 194611051Sandreas.hansson@arm.com } 194711051Sandreas.hansson@arm.com } else { 194811051Sandreas.hansson@arm.com cpuSidePort->sendAtomicSnoop(pkt); 194911051Sandreas.hansson@arm.com if (!alreadyResponded && pkt->cacheResponding()) { 195011051Sandreas.hansson@arm.com // cache-to-cache response from some upper cache: 195111051Sandreas.hansson@arm.com // forward response to original requester 195211051Sandreas.hansson@arm.com assert(pkt->isResponse()); 195311051Sandreas.hansson@arm.com } 195411051Sandreas.hansson@arm.com } 195511051Sandreas.hansson@arm.com } 195611051Sandreas.hansson@arm.com 195711051Sandreas.hansson@arm.com if (!blk || !blk->isValid()) { 195811051Sandreas.hansson@arm.com DPRINTF(CacheVerbose, "%s: snoop miss for %s\n", __func__, 195911051Sandreas.hansson@arm.com pkt->print()); 196011051Sandreas.hansson@arm.com if (is_deferred) { 196111051Sandreas.hansson@arm.com // we no longer have the block, and will not respond, but a 196211051Sandreas.hansson@arm.com // packet was allocated in MSHR::handleSnoop and we have 196311051Sandreas.hansson@arm.com // to delete it 196411051Sandreas.hansson@arm.com assert(pkt->needsResponse()); 196511051Sandreas.hansson@arm.com 196611051Sandreas.hansson@arm.com // we have passed the block to a cache upstream, that 196711051Sandreas.hansson@arm.com // cache should be responding 196811051Sandreas.hansson@arm.com assert(pkt->cacheResponding()); 196911051Sandreas.hansson@arm.com 197011051Sandreas.hansson@arm.com delete pkt; 197111051Sandreas.hansson@arm.com } 197211051Sandreas.hansson@arm.com return snoop_delay; 197311051Sandreas.hansson@arm.com } else { 197411051Sandreas.hansson@arm.com DPRINTF(Cache, "%s: snoop hit for %s, old state is %s\n", __func__, 197511051Sandreas.hansson@arm.com pkt->print(), blk->print()); 197611051Sandreas.hansson@arm.com } 197711051Sandreas.hansson@arm.com 197811051Sandreas.hansson@arm.com chatty_assert(!(isReadOnly && blk->isDirty()), 197911051Sandreas.hansson@arm.com "Should never have a dirty block in a read-only cache %s\n", 198011051Sandreas.hansson@arm.com name()); 198111051Sandreas.hansson@arm.com 198211051Sandreas.hansson@arm.com // We may end up modifying both the block state and the packet (if 198311051Sandreas.hansson@arm.com // we respond in atomic mode), so just figure out what to do now 198411051Sandreas.hansson@arm.com // and then do it later. We respond to all snoops that need 198511051Sandreas.hansson@arm.com // responses provided we have the block in dirty state. The 198611051Sandreas.hansson@arm.com // invalidation itself is taken care of below. 198711051Sandreas.hansson@arm.com bool respond = blk->isDirty() && pkt->needsResponse(); 198811051Sandreas.hansson@arm.com bool have_writable = blk->isWritable(); 198911051Sandreas.hansson@arm.com 199011051Sandreas.hansson@arm.com // Invalidate any prefetch's from below that would strip write permissions 199111051Sandreas.hansson@arm.com // MemCmd::HardPFReq is only observed by upstream caches. After missing 199211051Sandreas.hansson@arm.com // above and in it's own cache, a new MemCmd::ReadReq is created that 199311051Sandreas.hansson@arm.com // downstream caches observe. 199411051Sandreas.hansson@arm.com if (pkt->mustCheckAbove()) { 199511051Sandreas.hansson@arm.com DPRINTF(Cache, "Found addr %#llx in upper level cache for snoop %s " 199611051Sandreas.hansson@arm.com "from lower cache\n", pkt->getAddr(), pkt->print()); 199711051Sandreas.hansson@arm.com pkt->setBlockCached(); 199811051Sandreas.hansson@arm.com return snoop_delay; 199911051Sandreas.hansson@arm.com } 200011051Sandreas.hansson@arm.com 200111051Sandreas.hansson@arm.com if (pkt->isRead() && !invalidate) { 200211051Sandreas.hansson@arm.com // reading without requiring the line in a writable state 200311051Sandreas.hansson@arm.com assert(!needs_writable); 200411051Sandreas.hansson@arm.com pkt->setHasSharers(); 200511051Sandreas.hansson@arm.com 200611051Sandreas.hansson@arm.com // if the requesting packet is uncacheable, retain the line in 200711051Sandreas.hansson@arm.com // the current state, otherwhise unset the writable flag, 200811051Sandreas.hansson@arm.com // which means we go from Modified to Owned (and will respond 200911051Sandreas.hansson@arm.com // below), remain in Owned (and will respond below), from 201011051Sandreas.hansson@arm.com // Exclusive to Shared, or remain in Shared 201111051Sandreas.hansson@arm.com if (!pkt->req->isUncacheable()) 201211051Sandreas.hansson@arm.com blk->status &= ~BlkWritable; 201311051Sandreas.hansson@arm.com } 201411051Sandreas.hansson@arm.com 201511051Sandreas.hansson@arm.com if (respond) { 201611051Sandreas.hansson@arm.com // prevent anyone else from responding, cache as well as 201711051Sandreas.hansson@arm.com // memory, and also prevent any memory from even seeing the 201811051Sandreas.hansson@arm.com // request 201911051Sandreas.hansson@arm.com pkt->setCacheResponding(); 202011051Sandreas.hansson@arm.com if (have_writable) { 202111051Sandreas.hansson@arm.com // inform the cache hierarchy that this cache had the line 202211051Sandreas.hansson@arm.com // in the Modified state so that we avoid unnecessary 202311051Sandreas.hansson@arm.com // invalidations (see Packet::setResponderHadWritable) 202411051Sandreas.hansson@arm.com pkt->setResponderHadWritable(); 202511051Sandreas.hansson@arm.com 202611051Sandreas.hansson@arm.com // in the case of an uncacheable request there is no point 202711051Sandreas.hansson@arm.com // in setting the responderHadWritable flag, but since the 202811051Sandreas.hansson@arm.com // recipient does not care there is no harm in doing so 202911051Sandreas.hansson@arm.com } else { 203011051Sandreas.hansson@arm.com // if the packet has needsWritable set we invalidate our 203111051Sandreas.hansson@arm.com // copy below and all other copies will be invalidates 203211051Sandreas.hansson@arm.com // through express snoops, and if needsWritable is not set 203311051Sandreas.hansson@arm.com // we already called setHasSharers above 203411051Sandreas.hansson@arm.com } 203511051Sandreas.hansson@arm.com 203611051Sandreas.hansson@arm.com // if we are returning a writable and dirty (Modified) line, 203711051Sandreas.hansson@arm.com // we should be invalidating the line 203811051Sandreas.hansson@arm.com panic_if(!invalidate && !pkt->hasSharers(), 203911051Sandreas.hansson@arm.com "%s is passing a Modified line through %s, " 204011051Sandreas.hansson@arm.com "but keeping the block", name(), pkt->print()); 204111051Sandreas.hansson@arm.com 204211051Sandreas.hansson@arm.com if (is_timing) { 204311051Sandreas.hansson@arm.com doTimingSupplyResponse(pkt, blk->data, is_deferred, pending_inval); 204411051Sandreas.hansson@arm.com } else { 204511051Sandreas.hansson@arm.com pkt->makeAtomicResponse(); 204611051Sandreas.hansson@arm.com // packets such as upgrades do not actually have any data 204711051Sandreas.hansson@arm.com // payload 204811051Sandreas.hansson@arm.com if (pkt->hasData()) 204911051Sandreas.hansson@arm.com pkt->setDataFromBlock(blk->data, blkSize); 205011051Sandreas.hansson@arm.com } 205111051Sandreas.hansson@arm.com } 205211051Sandreas.hansson@arm.com 205311051Sandreas.hansson@arm.com if (!respond && is_deferred) { 205411051Sandreas.hansson@arm.com assert(pkt->needsResponse()); 205511051Sandreas.hansson@arm.com 205611051Sandreas.hansson@arm.com // if we copied the deferred packet with the intention to 205711051Sandreas.hansson@arm.com // respond, but are not responding, then a cache above us must 205811051Sandreas.hansson@arm.com // be, and we can use this as the indication of whether this 205911051Sandreas.hansson@arm.com // is a packet where we created a copy of the request or not 206011051Sandreas.hansson@arm.com if (!pkt->cacheResponding()) { 206111051Sandreas.hansson@arm.com delete pkt->req; 206211051Sandreas.hansson@arm.com } 206311051Sandreas.hansson@arm.com 206411051Sandreas.hansson@arm.com delete pkt; 206511051Sandreas.hansson@arm.com } 206611051Sandreas.hansson@arm.com 206711051Sandreas.hansson@arm.com // Do this last in case it deallocates block data or something 206811051Sandreas.hansson@arm.com // like that 206911051Sandreas.hansson@arm.com if (invalidate) { 207011051Sandreas.hansson@arm.com invalidateBlock(blk); 207111051Sandreas.hansson@arm.com } 207211051Sandreas.hansson@arm.com 207311051Sandreas.hansson@arm.com DPRINTF(Cache, "new state is %s\n", blk->print()); 207411051Sandreas.hansson@arm.com 207511051Sandreas.hansson@arm.com return snoop_delay; 207611051Sandreas.hansson@arm.com} 207711051Sandreas.hansson@arm.com 207811051Sandreas.hansson@arm.com 207911051Sandreas.hansson@arm.comvoid 208011051Sandreas.hansson@arm.comCache::recvTimingSnoopReq(PacketPtr pkt) 208111051Sandreas.hansson@arm.com{ 208211051Sandreas.hansson@arm.com DPRINTF(CacheVerbose, "%s: for %s\n", __func__, pkt->print()); 208311051Sandreas.hansson@arm.com 208411051Sandreas.hansson@arm.com // Snoops shouldn't happen when bypassing caches 208511051Sandreas.hansson@arm.com assert(!system->bypassCaches()); 208611051Sandreas.hansson@arm.com 208711051Sandreas.hansson@arm.com // no need to snoop requests that are not in range 208811051Sandreas.hansson@arm.com if (!inRange(pkt->getAddr())) { 208911051Sandreas.hansson@arm.com return; 209011051Sandreas.hansson@arm.com } 209111051Sandreas.hansson@arm.com 209211051Sandreas.hansson@arm.com bool is_secure = pkt->isSecure(); 209311051Sandreas.hansson@arm.com CacheBlk *blk = tags->findBlock(pkt->getAddr(), is_secure); 209411051Sandreas.hansson@arm.com 209511051Sandreas.hansson@arm.com Addr blk_addr = pkt->getBlockAddr(blkSize); 209611051Sandreas.hansson@arm.com MSHR *mshr = mshrQueue.findMatch(blk_addr, is_secure); 209711051Sandreas.hansson@arm.com 209811051Sandreas.hansson@arm.com // Update the latency cost of the snoop so that the crossbar can 209911051Sandreas.hansson@arm.com // account for it. Do not overwrite what other neighbouring caches 210011051Sandreas.hansson@arm.com // have already done, rather take the maximum. The update is 210111051Sandreas.hansson@arm.com // tentative, for cases where we return before an upward snoop 210211051Sandreas.hansson@arm.com // happens below. 210311051Sandreas.hansson@arm.com pkt->snoopDelay = std::max<uint32_t>(pkt->snoopDelay, 210411051Sandreas.hansson@arm.com lookupLatency * clockPeriod()); 210511051Sandreas.hansson@arm.com 210611051Sandreas.hansson@arm.com // Inform request(Prefetch, CleanEvict or Writeback) from below of 210711051Sandreas.hansson@arm.com // MSHR hit, set setBlockCached. 210811051Sandreas.hansson@arm.com if (mshr && pkt->mustCheckAbove()) { 210911051Sandreas.hansson@arm.com DPRINTF(Cache, "Setting block cached for %s from lower cache on " 211011051Sandreas.hansson@arm.com "mshr hit\n", pkt->print()); 211111051Sandreas.hansson@arm.com pkt->setBlockCached(); 211211051Sandreas.hansson@arm.com return; 211311051Sandreas.hansson@arm.com } 211411051Sandreas.hansson@arm.com 211511051Sandreas.hansson@arm.com // Let the MSHR itself track the snoop and decide whether we want 211611051Sandreas.hansson@arm.com // to go ahead and do the regular cache snoop 211711051Sandreas.hansson@arm.com if (mshr && mshr->handleSnoop(pkt, order++)) { 211811051Sandreas.hansson@arm.com DPRINTF(Cache, "Deferring snoop on in-service MSHR to blk %#llx (%s)." 211911051Sandreas.hansson@arm.com "mshrs: %s\n", blk_addr, is_secure ? "s" : "ns", 212011051Sandreas.hansson@arm.com mshr->print()); 212111051Sandreas.hansson@arm.com 212211051Sandreas.hansson@arm.com if (mshr->getNumTargets() > numTarget) 212311051Sandreas.hansson@arm.com warn("allocating bonus target for snoop"); //handle later 212411051Sandreas.hansson@arm.com return; 212511051Sandreas.hansson@arm.com } 212611051Sandreas.hansson@arm.com 212711051Sandreas.hansson@arm.com //We also need to check the writeback buffers and handle those 212811051Sandreas.hansson@arm.com WriteQueueEntry *wb_entry = writeBuffer.findMatch(blk_addr, is_secure); 212911051Sandreas.hansson@arm.com if (wb_entry) { 213011051Sandreas.hansson@arm.com DPRINTF(Cache, "Snoop hit in writeback to addr %#llx (%s)\n", 213111051Sandreas.hansson@arm.com pkt->getAddr(), is_secure ? "s" : "ns"); 213211051Sandreas.hansson@arm.com // Expect to see only Writebacks and/or CleanEvicts here, both of 213311051Sandreas.hansson@arm.com // which should not be generated for uncacheable data. 213411051Sandreas.hansson@arm.com assert(!wb_entry->isUncacheable()); 213511051Sandreas.hansson@arm.com // There should only be a single request responsible for generating 213611051Sandreas.hansson@arm.com // Writebacks/CleanEvicts. 213711051Sandreas.hansson@arm.com assert(wb_entry->getNumTargets() == 1); 213811051Sandreas.hansson@arm.com PacketPtr wb_pkt = wb_entry->getTarget()->pkt; 213911051Sandreas.hansson@arm.com assert(wb_pkt->isEviction()); 214011051Sandreas.hansson@arm.com 214111051Sandreas.hansson@arm.com if (pkt->isEviction()) { 214211051Sandreas.hansson@arm.com // if the block is found in the write queue, set the BLOCK_CACHED 214311051Sandreas.hansson@arm.com // flag for Writeback/CleanEvict snoop. On return the snoop will 214411051Sandreas.hansson@arm.com // propagate the BLOCK_CACHED flag in Writeback packets and prevent 214511051Sandreas.hansson@arm.com // any CleanEvicts from travelling down the memory hierarchy. 214611051Sandreas.hansson@arm.com pkt->setBlockCached(); 214711051Sandreas.hansson@arm.com DPRINTF(Cache, "%s: Squashing %s from lower cache on writequeue " 214811051Sandreas.hansson@arm.com "hit\n", __func__, pkt->print()); 214911051Sandreas.hansson@arm.com return; 215011051Sandreas.hansson@arm.com } 215111051Sandreas.hansson@arm.com 215211051Sandreas.hansson@arm.com // conceptually writebacks are no different to other blocks in 215311051Sandreas.hansson@arm.com // this cache, so the behaviour is modelled after handleSnoop, 215411051Sandreas.hansson@arm.com // the difference being that instead of querying the block 215511051Sandreas.hansson@arm.com // state to determine if it is dirty and writable, we use the 215611051Sandreas.hansson@arm.com // command and fields of the writeback packet 215711051Sandreas.hansson@arm.com bool respond = wb_pkt->cmd == MemCmd::WritebackDirty && 215811051Sandreas.hansson@arm.com pkt->needsResponse(); 215911051Sandreas.hansson@arm.com bool have_writable = !wb_pkt->hasSharers(); 216011051Sandreas.hansson@arm.com bool invalidate = pkt->isInvalidate(); 216111051Sandreas.hansson@arm.com 216211051Sandreas.hansson@arm.com if (!pkt->req->isUncacheable() && pkt->isRead() && !invalidate) { 216311051Sandreas.hansson@arm.com assert(!pkt->needsWritable()); 216411051Sandreas.hansson@arm.com pkt->setHasSharers(); 216511051Sandreas.hansson@arm.com wb_pkt->setHasSharers(); 216611051Sandreas.hansson@arm.com } 216711051Sandreas.hansson@arm.com 216811051Sandreas.hansson@arm.com if (respond) { 216911051Sandreas.hansson@arm.com pkt->setCacheResponding(); 217011051Sandreas.hansson@arm.com 217111051Sandreas.hansson@arm.com if (have_writable) { 217211051Sandreas.hansson@arm.com pkt->setResponderHadWritable(); 217311051Sandreas.hansson@arm.com } 217411051Sandreas.hansson@arm.com 217511051Sandreas.hansson@arm.com doTimingSupplyResponse(pkt, wb_pkt->getConstPtr<uint8_t>(), 217611051Sandreas.hansson@arm.com false, false); 217711051Sandreas.hansson@arm.com } 217811051Sandreas.hansson@arm.com 217911051Sandreas.hansson@arm.com if (invalidate) { 218011051Sandreas.hansson@arm.com // Invalidation trumps our writeback... discard here 218111051Sandreas.hansson@arm.com // Note: markInService will remove entry from writeback buffer. 218211051Sandreas.hansson@arm.com markInService(wb_entry); 218311051Sandreas.hansson@arm.com delete wb_pkt; 218411051Sandreas.hansson@arm.com } 218511051Sandreas.hansson@arm.com } 218611051Sandreas.hansson@arm.com 218711051Sandreas.hansson@arm.com // If this was a shared writeback, there may still be 218811051Sandreas.hansson@arm.com // other shared copies above that require invalidation. 218911051Sandreas.hansson@arm.com // We could be more selective and return here if the 219011051Sandreas.hansson@arm.com // request is non-exclusive or if the writeback is 219111051Sandreas.hansson@arm.com // exclusive. 219211051Sandreas.hansson@arm.com uint32_t snoop_delay = handleSnoop(pkt, blk, true, false, false); 219311051Sandreas.hansson@arm.com 219411051Sandreas.hansson@arm.com // Override what we did when we first saw the snoop, as we now 219511051Sandreas.hansson@arm.com // also have the cost of the upwards snoops to account for 219611051Sandreas.hansson@arm.com pkt->snoopDelay = std::max<uint32_t>(pkt->snoopDelay, snoop_delay + 219711051Sandreas.hansson@arm.com lookupLatency * clockPeriod()); 219811051Sandreas.hansson@arm.com} 219911051Sandreas.hansson@arm.com 220011051Sandreas.hansson@arm.combool 220111051Sandreas.hansson@arm.comCache::CpuSidePort::recvTimingSnoopResp(PacketPtr pkt) 220211051Sandreas.hansson@arm.com{ 220311051Sandreas.hansson@arm.com // Express snoop responses from master to slave, e.g., from L1 to L2 220411051Sandreas.hansson@arm.com cache->recvTimingSnoopResp(pkt); 220511051Sandreas.hansson@arm.com return true; 220611051Sandreas.hansson@arm.com} 220711051Sandreas.hansson@arm.com 220811051Sandreas.hansson@arm.comTick 220911051Sandreas.hansson@arm.comCache::recvAtomicSnoop(PacketPtr pkt) 221011051Sandreas.hansson@arm.com{ 221111051Sandreas.hansson@arm.com // Snoops shouldn't happen when bypassing caches 221211051Sandreas.hansson@arm.com assert(!system->bypassCaches()); 221311051Sandreas.hansson@arm.com 221411051Sandreas.hansson@arm.com // no need to snoop requests that are not in range. 221511051Sandreas.hansson@arm.com if (!inRange(pkt->getAddr())) { 221611051Sandreas.hansson@arm.com return 0; 221711051Sandreas.hansson@arm.com } 221811051Sandreas.hansson@arm.com 221911051Sandreas.hansson@arm.com CacheBlk *blk = tags->findBlock(pkt->getAddr(), pkt->isSecure()); 222011051Sandreas.hansson@arm.com uint32_t snoop_delay = handleSnoop(pkt, blk, false, false, false); 222111051Sandreas.hansson@arm.com return snoop_delay + lookupLatency * clockPeriod(); 222211051Sandreas.hansson@arm.com} 222311051Sandreas.hansson@arm.com 222411051Sandreas.hansson@arm.com 222511051Sandreas.hansson@arm.comQueueEntry* 222611051Sandreas.hansson@arm.comCache::getNextQueueEntry() 222711051Sandreas.hansson@arm.com{ 222811051Sandreas.hansson@arm.com // Check both MSHR queue and write buffer for potential requests, 222911051Sandreas.hansson@arm.com // note that null does not mean there is no request, it could 223011051Sandreas.hansson@arm.com // simply be that it is not ready 223111051Sandreas.hansson@arm.com MSHR *miss_mshr = mshrQueue.getNext(); 223211051Sandreas.hansson@arm.com WriteQueueEntry *wq_entry = writeBuffer.getNext(); 223311051Sandreas.hansson@arm.com 223411051Sandreas.hansson@arm.com // If we got a write buffer request ready, first priority is a 223511051Sandreas.hansson@arm.com // full write buffer, otherwise we favour the miss requests 223611051Sandreas.hansson@arm.com if (wq_entry && (writeBuffer.isFull() || !miss_mshr)) { 223711051Sandreas.hansson@arm.com // need to search MSHR queue for conflicting earlier miss. 223811051Sandreas.hansson@arm.com MSHR *conflict_mshr = 223911051Sandreas.hansson@arm.com mshrQueue.findPending(wq_entry->blkAddr, 224011051Sandreas.hansson@arm.com wq_entry->isSecure); 224111051Sandreas.hansson@arm.com 224211051Sandreas.hansson@arm.com if (conflict_mshr && conflict_mshr->order < wq_entry->order) { 224311051Sandreas.hansson@arm.com // Service misses in order until conflict is cleared. 224411051Sandreas.hansson@arm.com return conflict_mshr; 224511051Sandreas.hansson@arm.com 224611051Sandreas.hansson@arm.com // @todo Note that we ignore the ready time of the conflict here 224711051Sandreas.hansson@arm.com } 224811051Sandreas.hansson@arm.com 224911051Sandreas.hansson@arm.com // No conflicts; issue write 225011051Sandreas.hansson@arm.com return wq_entry; 225111051Sandreas.hansson@arm.com } else if (miss_mshr) { 225211051Sandreas.hansson@arm.com // need to check for conflicting earlier writeback 225311051Sandreas.hansson@arm.com WriteQueueEntry *conflict_mshr = 225411051Sandreas.hansson@arm.com writeBuffer.findPending(miss_mshr->blkAddr, 225511051Sandreas.hansson@arm.com miss_mshr->isSecure); 225611051Sandreas.hansson@arm.com if (conflict_mshr) { 225711051Sandreas.hansson@arm.com // not sure why we don't check order here... it was in the 225811051Sandreas.hansson@arm.com // original code but commented out. 225911051Sandreas.hansson@arm.com 226011051Sandreas.hansson@arm.com // The only way this happens is if we are 226111051Sandreas.hansson@arm.com // doing a write and we didn't have permissions 226211051Sandreas.hansson@arm.com // then subsequently saw a writeback (owned got evicted) 226311051Sandreas.hansson@arm.com // We need to make sure to perform the writeback first 226411051Sandreas.hansson@arm.com // To preserve the dirty data, then we can issue the write 226511051Sandreas.hansson@arm.com 226611051Sandreas.hansson@arm.com // should we return wq_entry here instead? I.e. do we 226711051Sandreas.hansson@arm.com // have to flush writes in order? I don't think so... not 226811051Sandreas.hansson@arm.com // for Alpha anyway. Maybe for x86? 226911051Sandreas.hansson@arm.com return conflict_mshr; 227011051Sandreas.hansson@arm.com 227111051Sandreas.hansson@arm.com // @todo Note that we ignore the ready time of the conflict here 227211051Sandreas.hansson@arm.com } 227311051Sandreas.hansson@arm.com 227411051Sandreas.hansson@arm.com // No conflicts; issue read 227511051Sandreas.hansson@arm.com return miss_mshr; 227611051Sandreas.hansson@arm.com } 227711051Sandreas.hansson@arm.com 227811051Sandreas.hansson@arm.com // fall through... no pending requests. Try a prefetch. 227911051Sandreas.hansson@arm.com assert(!miss_mshr && !wq_entry); 228011051Sandreas.hansson@arm.com if (prefetcher && mshrQueue.canPrefetch()) { 228111051Sandreas.hansson@arm.com // If we have a miss queue slot, we can try a prefetch 228211051Sandreas.hansson@arm.com PacketPtr pkt = prefetcher->getPacket(); 228311051Sandreas.hansson@arm.com if (pkt) { 228411051Sandreas.hansson@arm.com Addr pf_addr = pkt->getBlockAddr(blkSize); 228511051Sandreas.hansson@arm.com if (!tags->findBlock(pf_addr, pkt->isSecure()) && 228611051Sandreas.hansson@arm.com !mshrQueue.findMatch(pf_addr, pkt->isSecure()) && 228711051Sandreas.hansson@arm.com !writeBuffer.findMatch(pf_addr, pkt->isSecure())) { 228811051Sandreas.hansson@arm.com // Update statistic on number of prefetches issued 228911051Sandreas.hansson@arm.com // (hwpf_mshr_misses) 229011051Sandreas.hansson@arm.com assert(pkt->req->masterId() < system->maxMasters()); 229111051Sandreas.hansson@arm.com mshr_misses[pkt->cmdToIndex()][pkt->req->masterId()]++; 229211051Sandreas.hansson@arm.com 229311051Sandreas.hansson@arm.com // allocate an MSHR and return it, note 229411051Sandreas.hansson@arm.com // that we send the packet straight away, so do not 229511051Sandreas.hansson@arm.com // schedule the send 229611051Sandreas.hansson@arm.com return allocateMissBuffer(pkt, curTick(), false); 229711051Sandreas.hansson@arm.com } else { 229811051Sandreas.hansson@arm.com // free the request and packet 229911051Sandreas.hansson@arm.com delete pkt->req; 230011051Sandreas.hansson@arm.com delete pkt; 230111051Sandreas.hansson@arm.com } 230211051Sandreas.hansson@arm.com } 230311051Sandreas.hansson@arm.com } 230411051Sandreas.hansson@arm.com 230511051Sandreas.hansson@arm.com return nullptr; 230611051Sandreas.hansson@arm.com} 230711051Sandreas.hansson@arm.com 230811051Sandreas.hansson@arm.combool 230911051Sandreas.hansson@arm.comCache::isCachedAbove(PacketPtr pkt, bool is_timing) const 231011051Sandreas.hansson@arm.com{ 231111051Sandreas.hansson@arm.com if (!forwardSnoops) 231211051Sandreas.hansson@arm.com return false; 231311051Sandreas.hansson@arm.com // Mirroring the flow of HardPFReqs, the cache sends CleanEvict and 231411051Sandreas.hansson@arm.com // Writeback snoops into upper level caches to check for copies of the 231511051Sandreas.hansson@arm.com // same block. Using the BLOCK_CACHED flag with the Writeback/CleanEvict 231611051Sandreas.hansson@arm.com // packet, the cache can inform the crossbar below of presence or absence 231711051Sandreas.hansson@arm.com // of the block. 231811051Sandreas.hansson@arm.com if (is_timing) { 231911051Sandreas.hansson@arm.com Packet snoop_pkt(pkt, true, false); 232011051Sandreas.hansson@arm.com snoop_pkt.setExpressSnoop(); 232111051Sandreas.hansson@arm.com // Assert that packet is either Writeback or CleanEvict and not a 232211051Sandreas.hansson@arm.com // prefetch request because prefetch requests need an MSHR and may 232311051Sandreas.hansson@arm.com // generate a snoop response. 232411051Sandreas.hansson@arm.com assert(pkt->isEviction()); 232511051Sandreas.hansson@arm.com snoop_pkt.senderState = nullptr; 232611051Sandreas.hansson@arm.com cpuSidePort->sendTimingSnoopReq(&snoop_pkt); 232711051Sandreas.hansson@arm.com // Writeback/CleanEvict snoops do not generate a snoop response. 232811051Sandreas.hansson@arm.com assert(!(snoop_pkt.cacheResponding())); 232911051Sandreas.hansson@arm.com return snoop_pkt.isBlockCached(); 233011051Sandreas.hansson@arm.com } else { 233111051Sandreas.hansson@arm.com cpuSidePort->sendAtomicSnoop(pkt); 233211051Sandreas.hansson@arm.com return pkt->isBlockCached(); 233311051Sandreas.hansson@arm.com } 233411051Sandreas.hansson@arm.com} 233511051Sandreas.hansson@arm.com 233611051Sandreas.hansson@arm.comTick 233711051Sandreas.hansson@arm.comCache::nextQueueReadyTime() const 233811051Sandreas.hansson@arm.com{ 233911051Sandreas.hansson@arm.com Tick nextReady = std::min(mshrQueue.nextReadyTime(), 234011051Sandreas.hansson@arm.com writeBuffer.nextReadyTime()); 234111051Sandreas.hansson@arm.com 234211051Sandreas.hansson@arm.com // Don't signal prefetch ready time if no MSHRs available 234311051Sandreas.hansson@arm.com // Will signal once enoguh MSHRs are deallocated 234411051Sandreas.hansson@arm.com if (prefetcher && mshrQueue.canPrefetch()) { 234511051Sandreas.hansson@arm.com nextReady = std::min(nextReady, 234611051Sandreas.hansson@arm.com prefetcher->nextPrefetchReadyTime()); 234711051Sandreas.hansson@arm.com } 234811051Sandreas.hansson@arm.com 234911051Sandreas.hansson@arm.com return nextReady; 235011051Sandreas.hansson@arm.com} 235111051Sandreas.hansson@arm.com 235211051Sandreas.hansson@arm.combool 235311051Sandreas.hansson@arm.comCache::sendMSHRQueuePacket(MSHR* mshr) 235411051Sandreas.hansson@arm.com{ 235511051Sandreas.hansson@arm.com assert(mshr); 235611051Sandreas.hansson@arm.com 235711051Sandreas.hansson@arm.com // use request from 1st target 235811051Sandreas.hansson@arm.com PacketPtr tgt_pkt = mshr->getTarget()->pkt; 235911051Sandreas.hansson@arm.com 236011051Sandreas.hansson@arm.com DPRINTF(Cache, "%s: MSHR %s\n", __func__, tgt_pkt->print()); 236111051Sandreas.hansson@arm.com 236211051Sandreas.hansson@arm.com CacheBlk *blk = tags->findBlock(mshr->blkAddr, mshr->isSecure); 236311051Sandreas.hansson@arm.com 236411051Sandreas.hansson@arm.com if (tgt_pkt->cmd == MemCmd::HardPFReq && forwardSnoops) { 236511051Sandreas.hansson@arm.com // we should never have hardware prefetches to allocated 236611051Sandreas.hansson@arm.com // blocks 236711051Sandreas.hansson@arm.com assert(blk == nullptr); 236811051Sandreas.hansson@arm.com 236911051Sandreas.hansson@arm.com // We need to check the caches above us to verify that 237011051Sandreas.hansson@arm.com // they don't have a copy of this block in the dirty state 237111051Sandreas.hansson@arm.com // at the moment. Without this check we could get a stale 237211051Sandreas.hansson@arm.com // copy from memory that might get used in place of the 237311051Sandreas.hansson@arm.com // dirty one. 237411051Sandreas.hansson@arm.com Packet snoop_pkt(tgt_pkt, true, false); 237511051Sandreas.hansson@arm.com snoop_pkt.setExpressSnoop(); 237611051Sandreas.hansson@arm.com // We are sending this packet upwards, but if it hits we will 237711051Sandreas.hansson@arm.com // get a snoop response that we end up treating just like a 237811051Sandreas.hansson@arm.com // normal response, hence it needs the MSHR as its sender 237911051Sandreas.hansson@arm.com // state 238011051Sandreas.hansson@arm.com snoop_pkt.senderState = mshr; 238111051Sandreas.hansson@arm.com cpuSidePort->sendTimingSnoopReq(&snoop_pkt); 238211051Sandreas.hansson@arm.com 238311051Sandreas.hansson@arm.com // Check to see if the prefetch was squashed by an upper cache (to 238411051Sandreas.hansson@arm.com // prevent us from grabbing the line) or if a Check to see if a 238511053Sandreas.hansson@arm.com // writeback arrived between the time the prefetch was placed in 238611053Sandreas.hansson@arm.com // the MSHRs and when it was selected to be sent or if the 238711053Sandreas.hansson@arm.com // prefetch was squashed by an upper cache. 238811053Sandreas.hansson@arm.com 238911053Sandreas.hansson@arm.com // It is important to check cacheResponding before 239011053Sandreas.hansson@arm.com // prefetchSquashed. If another cache has committed to 239111053Sandreas.hansson@arm.com // responding, it will be sending a dirty response which will 239211051Sandreas.hansson@arm.com // arrive at the MSHR allocated for this request. Checking the 239311051Sandreas.hansson@arm.com // prefetchSquash first may result in the MSHR being 239411051Sandreas.hansson@arm.com // prematurely deallocated. 239511051Sandreas.hansson@arm.com if (snoop_pkt.cacheResponding()) { 239611051Sandreas.hansson@arm.com auto M5_VAR_USED r = outstandingSnoop.insert(snoop_pkt.req); 239711051Sandreas.hansson@arm.com assert(r.second); 239811051Sandreas.hansson@arm.com 239911051Sandreas.hansson@arm.com // if we are getting a snoop response with no sharers it 240011051Sandreas.hansson@arm.com // will be allocated as Modified 240111051Sandreas.hansson@arm.com bool pending_modified_resp = !snoop_pkt.hasSharers(); 240211051Sandreas.hansson@arm.com markInService(mshr, pending_modified_resp); 240311051Sandreas.hansson@arm.com 240411051Sandreas.hansson@arm.com DPRINTF(Cache, "Upward snoop of prefetch for addr" 240511051Sandreas.hansson@arm.com " %#x (%s) hit\n", 240611051Sandreas.hansson@arm.com tgt_pkt->getAddr(), tgt_pkt->isSecure()? "s": "ns"); 240711051Sandreas.hansson@arm.com return false; 240811051Sandreas.hansson@arm.com } 240911051Sandreas.hansson@arm.com 241011051Sandreas.hansson@arm.com if (snoop_pkt.isBlockCached()) { 241111051Sandreas.hansson@arm.com DPRINTF(Cache, "Block present, prefetch squashed by cache. " 241211051Sandreas.hansson@arm.com "Deallocating mshr target %#x.\n", 241311051Sandreas.hansson@arm.com mshr->blkAddr); 241411051Sandreas.hansson@arm.com 241511051Sandreas.hansson@arm.com // Deallocate the mshr target 241611051Sandreas.hansson@arm.com if (mshrQueue.forceDeallocateTarget(mshr)) { 241711051Sandreas.hansson@arm.com // Clear block if this deallocation resulted freed an 241811051Sandreas.hansson@arm.com // mshr when all had previously been utilized 241911051Sandreas.hansson@arm.com clearBlocked(Blocked_NoMSHRs); 242011051Sandreas.hansson@arm.com } 242111051Sandreas.hansson@arm.com return false; 242211051Sandreas.hansson@arm.com } 242311051Sandreas.hansson@arm.com } 242411051Sandreas.hansson@arm.com 242511051Sandreas.hansson@arm.com // either a prefetch that is not present upstream, or a normal 242611051Sandreas.hansson@arm.com // MSHR request, proceed to get the packet to send downstream 242711051Sandreas.hansson@arm.com PacketPtr pkt = createMissPacket(tgt_pkt, blk, mshr->needsWritable()); 242811051Sandreas.hansson@arm.com 242911051Sandreas.hansson@arm.com mshr->isForward = (pkt == nullptr); 243011051Sandreas.hansson@arm.com 243111051Sandreas.hansson@arm.com if (mshr->isForward) { 243211051Sandreas.hansson@arm.com // not a cache block request, but a response is expected 243311051Sandreas.hansson@arm.com // make copy of current packet to forward, keep current 243411051Sandreas.hansson@arm.com // copy for response handling 243511051Sandreas.hansson@arm.com pkt = new Packet(tgt_pkt, false, true); 243611051Sandreas.hansson@arm.com assert(!pkt->isWrite()); 243711051Sandreas.hansson@arm.com } 243811051Sandreas.hansson@arm.com 243911051Sandreas.hansson@arm.com // play it safe and append (rather than set) the sender state, 244011051Sandreas.hansson@arm.com // as forwarded packets may already have existing state 244111051Sandreas.hansson@arm.com pkt->pushSenderState(mshr); 244211051Sandreas.hansson@arm.com 244311051Sandreas.hansson@arm.com if (!memSidePort->sendTimingReq(pkt)) { 244411051Sandreas.hansson@arm.com // we are awaiting a retry, but we 244511051Sandreas.hansson@arm.com // delete the packet and will be creating a new packet 244611051Sandreas.hansson@arm.com // when we get the opportunity 244711051Sandreas.hansson@arm.com delete pkt; 244811051Sandreas.hansson@arm.com 244911051Sandreas.hansson@arm.com // note that we have now masked any requestBus and 245011051Sandreas.hansson@arm.com // schedSendEvent (we will wait for a retry before 245111051Sandreas.hansson@arm.com // doing anything), and this is so even if we do not 245211051Sandreas.hansson@arm.com // care about this packet and might override it before 245311051Sandreas.hansson@arm.com // it gets retried 245411051Sandreas.hansson@arm.com return true; 245511051Sandreas.hansson@arm.com } else { 245611051Sandreas.hansson@arm.com // As part of the call to sendTimingReq the packet is 245711051Sandreas.hansson@arm.com // forwarded to all neighbouring caches (and any caches 245811051Sandreas.hansson@arm.com // above them) as a snoop. Thus at this point we know if 245911051Sandreas.hansson@arm.com // any of the neighbouring caches are responding, and if 246011051Sandreas.hansson@arm.com // so, we know it is dirty, and we can determine if it is 246111051Sandreas.hansson@arm.com // being passed as Modified, making our MSHR the ordering 246211051Sandreas.hansson@arm.com // point 246311051Sandreas.hansson@arm.com bool pending_modified_resp = !pkt->hasSharers() && 246411051Sandreas.hansson@arm.com pkt->cacheResponding(); 246511051Sandreas.hansson@arm.com markInService(mshr, pending_modified_resp); 246611051Sandreas.hansson@arm.com return false; 246711051Sandreas.hansson@arm.com } 246811051Sandreas.hansson@arm.com} 246911051Sandreas.hansson@arm.com 247011051Sandreas.hansson@arm.combool 247111051Sandreas.hansson@arm.comCache::sendWriteQueuePacket(WriteQueueEntry* wq_entry) 247211051Sandreas.hansson@arm.com{ 247311051Sandreas.hansson@arm.com assert(wq_entry); 247411051Sandreas.hansson@arm.com 247511051Sandreas.hansson@arm.com // always a single target for write queue entries 247611051Sandreas.hansson@arm.com PacketPtr tgt_pkt = wq_entry->getTarget()->pkt; 247711051Sandreas.hansson@arm.com 247811051Sandreas.hansson@arm.com DPRINTF(Cache, "%s: write %s\n", __func__, tgt_pkt->print()); 247911051Sandreas.hansson@arm.com 248011051Sandreas.hansson@arm.com // forward as is, both for evictions and uncacheable writes 248111051Sandreas.hansson@arm.com if (!memSidePort->sendTimingReq(tgt_pkt)) { 248211051Sandreas.hansson@arm.com // note that we have now masked any requestBus and 248311051Sandreas.hansson@arm.com // schedSendEvent (we will wait for a retry before 248411051Sandreas.hansson@arm.com // doing anything), and this is so even if we do not 248511051Sandreas.hansson@arm.com // care about this packet and might override it before 248611051Sandreas.hansson@arm.com // it gets retried 248711051Sandreas.hansson@arm.com return true; 248811051Sandreas.hansson@arm.com } else { 248911051Sandreas.hansson@arm.com markInService(wq_entry); 249011051Sandreas.hansson@arm.com return false; 249111051Sandreas.hansson@arm.com } 249211051Sandreas.hansson@arm.com} 249311051Sandreas.hansson@arm.com 249411051Sandreas.hansson@arm.comvoid 249511051Sandreas.hansson@arm.comCache::serialize(CheckpointOut &cp) const 249611051Sandreas.hansson@arm.com{ 249711051Sandreas.hansson@arm.com bool dirty(isDirty()); 249811051Sandreas.hansson@arm.com 249911051Sandreas.hansson@arm.com if (dirty) { 250011051Sandreas.hansson@arm.com warn("*** The cache still contains dirty data. ***\n"); 250111051Sandreas.hansson@arm.com warn(" Make sure to drain the system using the correct flags.\n"); 250211051Sandreas.hansson@arm.com warn(" This checkpoint will not restore correctly and dirty data " 250311051Sandreas.hansson@arm.com " in the cache will be lost!\n"); 250411051Sandreas.hansson@arm.com } 250511051Sandreas.hansson@arm.com 250611051Sandreas.hansson@arm.com // Since we don't checkpoint the data in the cache, any dirty data 250711051Sandreas.hansson@arm.com // will be lost when restoring from a checkpoint of a system that 250811051Sandreas.hansson@arm.com // wasn't drained properly. Flag the checkpoint as invalid if the 250911051Sandreas.hansson@arm.com // cache contains dirty data. 251011051Sandreas.hansson@arm.com bool bad_checkpoint(dirty); 251111051Sandreas.hansson@arm.com SERIALIZE_SCALAR(bad_checkpoint); 251211051Sandreas.hansson@arm.com} 251311051Sandreas.hansson@arm.com 251411051Sandreas.hansson@arm.comvoid 251511051Sandreas.hansson@arm.comCache::unserialize(CheckpointIn &cp) 251611051Sandreas.hansson@arm.com{ 251711051Sandreas.hansson@arm.com bool bad_checkpoint; 2518 UNSERIALIZE_SCALAR(bad_checkpoint); 2519 if (bad_checkpoint) { 2520 fatal("Restoring from checkpoints with dirty caches is not supported " 2521 "in the classic memory system. Please remove any caches or " 2522 " drain them properly before taking checkpoints.\n"); 2523 } 2524} 2525 2526/////////////// 2527// 2528// CpuSidePort 2529// 2530/////////////// 2531 2532AddrRangeList 2533Cache::CpuSidePort::getAddrRanges() const 2534{ 2535 return cache->getAddrRanges(); 2536} 2537 2538bool 2539Cache::CpuSidePort::recvTimingReq(PacketPtr pkt) 2540{ 2541 assert(!cache->system->bypassCaches()); 2542 2543 bool success = false; 2544 2545 // always let express snoop packets through if even if blocked 2546 if (pkt->isExpressSnoop()) { 2547 // do not change the current retry state 2548 bool M5_VAR_USED bypass_success = cache->recvTimingReq(pkt); 2549 assert(bypass_success); 2550 return true; 2551 } else if (blocked || mustSendRetry) { 2552 // either already committed to send a retry, or blocked 2553 success = false; 2554 } else { 2555 // pass it on to the cache, and let the cache decide if we 2556 // have to retry or not 2557 success = cache->recvTimingReq(pkt); 2558 } 2559 2560 // remember if we have to retry 2561 mustSendRetry = !success; 2562 return success; 2563} 2564 2565Tick 2566Cache::CpuSidePort::recvAtomic(PacketPtr pkt) 2567{ 2568 return cache->recvAtomic(pkt); 2569} 2570 2571void 2572Cache::CpuSidePort::recvFunctional(PacketPtr pkt) 2573{ 2574 // functional request 2575 cache->functionalAccess(pkt, true); 2576} 2577 2578Cache:: 2579CpuSidePort::CpuSidePort(const std::string &_name, Cache *_cache, 2580 const std::string &_label) 2581 : BaseCache::CacheSlavePort(_name, _cache, _label), cache(_cache) 2582{ 2583} 2584 2585Cache* 2586CacheParams::create() 2587{ 2588 assert(tags); 2589 2590 return new Cache(this); 2591} 2592/////////////// 2593// 2594// MemSidePort 2595// 2596/////////////// 2597 2598bool 2599Cache::MemSidePort::recvTimingResp(PacketPtr pkt) 2600{ 2601 cache->recvTimingResp(pkt); 2602 return true; 2603} 2604 2605// Express snooping requests to memside port 2606void 2607Cache::MemSidePort::recvTimingSnoopReq(PacketPtr pkt) 2608{ 2609 // handle snooping requests 2610 cache->recvTimingSnoopReq(pkt); 2611} 2612 2613Tick 2614Cache::MemSidePort::recvAtomicSnoop(PacketPtr pkt) 2615{ 2616 return cache->recvAtomicSnoop(pkt); 2617} 2618 2619void 2620Cache::MemSidePort::recvFunctionalSnoop(PacketPtr pkt) 2621{ 2622 // functional snoop (note that in contrast to atomic we don't have 2623 // a specific functionalSnoop method, as they have the same 2624 // behaviour regardless) 2625 cache->functionalAccess(pkt, false); 2626} 2627 2628void 2629Cache::CacheReqPacketQueue::sendDeferredPacket() 2630{ 2631 // sanity check 2632 assert(!waitingOnRetry); 2633 2634 // there should never be any deferred request packets in the 2635 // queue, instead we resly on the cache to provide the packets 2636 // from the MSHR queue or write queue 2637 assert(deferredPacketReadyTime() == MaxTick); 2638 2639 // check for request packets (requests & writebacks) 2640 QueueEntry* entry = cache.getNextQueueEntry(); 2641 2642 if (!entry) { 2643 // can happen if e.g. we attempt a writeback and fail, but 2644 // before the retry, the writeback is eliminated because 2645 // we snoop another cache's ReadEx. 2646 } else { 2647 // let our snoop responses go first if there are responses to 2648 // the same addresses 2649 if (checkConflictingSnoop(entry->blkAddr)) { 2650 return; 2651 } 2652 waitingOnRetry = entry->sendPacket(cache); 2653 } 2654 2655 // if we succeeded and are not waiting for a retry, schedule the 2656 // next send considering when the next queue is ready, note that 2657 // snoop responses have their own packet queue and thus schedule 2658 // their own events 2659 if (!waitingOnRetry) { 2660 schedSendEvent(cache.nextQueueReadyTime()); 2661 } 2662} 2663 2664Cache:: 2665MemSidePort::MemSidePort(const std::string &_name, Cache *_cache, 2666 const std::string &_label) 2667 : BaseCache::CacheMasterPort(_name, _cache, _reqQueue, _snoopRespQueue), 2668 _reqQueue(*_cache, *this, _snoopRespQueue, _label), 2669 _snoopRespQueue(*_cache, *this, _label), cache(_cache) 2670{ 2671} 2672