cache.cc revision 11053
12810Srdreslin@umich.edu/* 211375Sandreas.hansson@arm.com * Copyright (c) 2010-2015 ARM Limited 311051Sandreas.hansson@arm.com * All rights reserved. 411051Sandreas.hansson@arm.com * 511051Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall 611051Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual 711051Sandreas.hansson@arm.com * property including but not limited to intellectual property relating 811051Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software 911051Sandreas.hansson@arm.com * licensed hereunder. You may use the software subject to the license 1011051Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated 1111051Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software, 1211051Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form. 1311051Sandreas.hansson@arm.com * 1411051Sandreas.hansson@arm.com * Copyright (c) 2002-2005 The Regents of The University of Michigan 1511051Sandreas.hansson@arm.com * Copyright (c) 2010,2015 Advanced Micro Devices, Inc. 162810Srdreslin@umich.edu * All rights reserved. 172810Srdreslin@umich.edu * 182810Srdreslin@umich.edu * Redistribution and use in source and binary forms, with or without 192810Srdreslin@umich.edu * modification, are permitted provided that the following conditions are 202810Srdreslin@umich.edu * met: redistributions of source code must retain the above copyright 212810Srdreslin@umich.edu * notice, this list of conditions and the following disclaimer; 222810Srdreslin@umich.edu * redistributions in binary form must reproduce the above copyright 232810Srdreslin@umich.edu * notice, this list of conditions and the following disclaimer in the 242810Srdreslin@umich.edu * documentation and/or other materials provided with the distribution; 252810Srdreslin@umich.edu * neither the name of the copyright holders nor the names of its 262810Srdreslin@umich.edu * contributors may be used to endorse or promote products derived from 272810Srdreslin@umich.edu * this software without specific prior written permission. 282810Srdreslin@umich.edu * 292810Srdreslin@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 302810Srdreslin@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 312810Srdreslin@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 322810Srdreslin@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 332810Srdreslin@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 342810Srdreslin@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 352810Srdreslin@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 362810Srdreslin@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 372810Srdreslin@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 382810Srdreslin@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 392810Srdreslin@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402810Srdreslin@umich.edu * 412810Srdreslin@umich.edu * Authors: Erik Hallnor 4211051Sandreas.hansson@arm.com * Dave Greene 4311051Sandreas.hansson@arm.com * Nathan Binkert 442810Srdreslin@umich.edu * Steve Reinhardt 4511051Sandreas.hansson@arm.com * Ron Dreslinski 4611051Sandreas.hansson@arm.com * Andreas Sandberg 472810Srdreslin@umich.edu */ 482810Srdreslin@umich.edu 492810Srdreslin@umich.edu/** 502810Srdreslin@umich.edu * @file 5111051Sandreas.hansson@arm.com * Cache definitions. 522810Srdreslin@umich.edu */ 532810Srdreslin@umich.edu 5411051Sandreas.hansson@arm.com#include "mem/cache/cache.hh" 552810Srdreslin@umich.edu 5611051Sandreas.hansson@arm.com#include "base/misc.hh" 5711051Sandreas.hansson@arm.com#include "base/types.hh" 5811051Sandreas.hansson@arm.com#include "debug/Cache.hh" 5911051Sandreas.hansson@arm.com#include "debug/CachePort.hh" 6011051Sandreas.hansson@arm.com#include "debug/CacheTags.hh" 6111288Ssteve.reinhardt@amd.com#include "mem/cache/blk.hh" 6211051Sandreas.hansson@arm.com#include "mem/cache/mshr.hh" 6311051Sandreas.hansson@arm.com#include "mem/cache/prefetch/base.hh" 6411051Sandreas.hansson@arm.com#include "sim/sim_exit.hh" 6511051Sandreas.hansson@arm.com 6611051Sandreas.hansson@arm.comCache::Cache(const CacheParams *p) 6711053Sandreas.hansson@arm.com : BaseCache(p, p->system->cacheLineSize()), 6811053Sandreas.hansson@arm.com tags(p->tags), 6911051Sandreas.hansson@arm.com prefetcher(p->prefetcher), 7011051Sandreas.hansson@arm.com doFastWrites(true), 7111051Sandreas.hansson@arm.com prefetchOnAccess(p->prefetch_on_access) 7211197Sandreas.hansson@arm.com{ 7311197Sandreas.hansson@arm.com tempBlock = new CacheBlk(); 7411199Sandreas.hansson@arm.com tempBlock->data = new uint8_t[blkSize]; 7511197Sandreas.hansson@arm.com 7611197Sandreas.hansson@arm.com cpuSidePort = new CpuSidePort(p->name + ".cpu_side", this, 7711197Sandreas.hansson@arm.com "CpuSidePort"); 7811051Sandreas.hansson@arm.com memSidePort = new MemSidePort(p->name + ".mem_side", this, 7911051Sandreas.hansson@arm.com "MemSidePort"); 8011051Sandreas.hansson@arm.com 8111051Sandreas.hansson@arm.com tags->setCache(this); 8211051Sandreas.hansson@arm.com if (prefetcher) 8311051Sandreas.hansson@arm.com prefetcher->setCache(this); 8411051Sandreas.hansson@arm.com} 8511051Sandreas.hansson@arm.com 8611051Sandreas.hansson@arm.comCache::~Cache() 8711051Sandreas.hansson@arm.com{ 8811051Sandreas.hansson@arm.com delete [] tempBlock->data; 8911051Sandreas.hansson@arm.com delete tempBlock; 9011051Sandreas.hansson@arm.com 9111051Sandreas.hansson@arm.com delete cpuSidePort; 9211051Sandreas.hansson@arm.com delete memSidePort; 9311051Sandreas.hansson@arm.com} 9411051Sandreas.hansson@arm.com 9511051Sandreas.hansson@arm.comvoid 9611051Sandreas.hansson@arm.comCache::regStats() 9711051Sandreas.hansson@arm.com{ 9811051Sandreas.hansson@arm.com BaseCache::regStats(); 9911051Sandreas.hansson@arm.com} 10011051Sandreas.hansson@arm.com 10111051Sandreas.hansson@arm.comvoid 10211051Sandreas.hansson@arm.comCache::cmpAndSwap(CacheBlk *blk, PacketPtr pkt) 10311051Sandreas.hansson@arm.com{ 10411051Sandreas.hansson@arm.com assert(pkt->isRequest()); 10511051Sandreas.hansson@arm.com 10611051Sandreas.hansson@arm.com uint64_t overwrite_val; 10711051Sandreas.hansson@arm.com bool overwrite_mem; 10811051Sandreas.hansson@arm.com uint64_t condition_val64; 10911051Sandreas.hansson@arm.com uint32_t condition_val32; 11011051Sandreas.hansson@arm.com 11111051Sandreas.hansson@arm.com int offset = tags->extractBlkOffset(pkt->getAddr()); 11211051Sandreas.hansson@arm.com uint8_t *blk_data = blk->data + offset; 11311051Sandreas.hansson@arm.com 11411051Sandreas.hansson@arm.com assert(sizeof(uint64_t) >= pkt->getSize()); 11511051Sandreas.hansson@arm.com 11611051Sandreas.hansson@arm.com overwrite_mem = true; 11711051Sandreas.hansson@arm.com // keep a copy of our possible write value, and copy what is at the 11811051Sandreas.hansson@arm.com // memory address into the packet 11911051Sandreas.hansson@arm.com pkt->writeData((uint8_t *)&overwrite_val); 12011051Sandreas.hansson@arm.com pkt->setData(blk_data); 12111051Sandreas.hansson@arm.com 12211051Sandreas.hansson@arm.com if (pkt->req->isCondSwap()) { 12311051Sandreas.hansson@arm.com if (pkt->getSize() == sizeof(uint64_t)) { 12411051Sandreas.hansson@arm.com condition_val64 = pkt->req->getExtraData(); 12511051Sandreas.hansson@arm.com overwrite_mem = !std::memcmp(&condition_val64, blk_data, 12611051Sandreas.hansson@arm.com sizeof(uint64_t)); 12711051Sandreas.hansson@arm.com } else if (pkt->getSize() == sizeof(uint32_t)) { 12811051Sandreas.hansson@arm.com condition_val32 = (uint32_t)pkt->req->getExtraData(); 12911051Sandreas.hansson@arm.com overwrite_mem = !std::memcmp(&condition_val32, blk_data, 13011051Sandreas.hansson@arm.com sizeof(uint32_t)); 13111051Sandreas.hansson@arm.com } else 13211051Sandreas.hansson@arm.com panic("Invalid size for conditional read/write\n"); 13311051Sandreas.hansson@arm.com } 13411051Sandreas.hansson@arm.com 13511051Sandreas.hansson@arm.com if (overwrite_mem) { 13611051Sandreas.hansson@arm.com std::memcpy(blk_data, &overwrite_val, pkt->getSize()); 13711051Sandreas.hansson@arm.com blk->status |= BlkDirty; 13811051Sandreas.hansson@arm.com } 13911051Sandreas.hansson@arm.com} 14011051Sandreas.hansson@arm.com 14111051Sandreas.hansson@arm.com 14211051Sandreas.hansson@arm.comvoid 14311051Sandreas.hansson@arm.comCache::satisfyCpuSideRequest(PacketPtr pkt, CacheBlk *blk, 14411051Sandreas.hansson@arm.com bool deferred_response, bool pending_downgrade) 14511051Sandreas.hansson@arm.com{ 14611051Sandreas.hansson@arm.com assert(pkt->isRequest()); 14711051Sandreas.hansson@arm.com 14811051Sandreas.hansson@arm.com assert(blk && blk->isValid()); 14911601Sandreas.hansson@arm.com // Occasionally this is not true... if we are a lower-level cache 15011601Sandreas.hansson@arm.com // satisfying a string of Read and ReadEx requests from 15111051Sandreas.hansson@arm.com // upper-level caches, a Read will mark the block as shared but we 15211051Sandreas.hansson@arm.com // can satisfy a following ReadEx anyway since we can rely on the 15311051Sandreas.hansson@arm.com // Read requester(s) to have buffered the ReadEx snoop and to 15411051Sandreas.hansson@arm.com // invalidate their blocks after receiving them. 15511051Sandreas.hansson@arm.com // assert(!pkt->needsExclusive() || blk->isWritable()); 15611051Sandreas.hansson@arm.com assert(pkt->getOffset(blkSize) + pkt->getSize() <= blkSize); 15711051Sandreas.hansson@arm.com 15811051Sandreas.hansson@arm.com // Check RMW operations first since both isRead() and 15911051Sandreas.hansson@arm.com // isWrite() will be true for them 16011051Sandreas.hansson@arm.com if (pkt->cmd == MemCmd::SwapReq) { 16111284Sandreas.hansson@arm.com cmpAndSwap(blk, pkt); 16211051Sandreas.hansson@arm.com } else if (pkt->isWrite()) { 16311051Sandreas.hansson@arm.com assert(blk->isWritable()); 16411051Sandreas.hansson@arm.com // Write or WriteLine at the first cache with block in Exclusive 16511051Sandreas.hansson@arm.com if (blk->checkWrite(pkt)) { 16611051Sandreas.hansson@arm.com pkt->writeDataToBlock(blk->data, blkSize); 16711051Sandreas.hansson@arm.com } 16811051Sandreas.hansson@arm.com // Always mark the line as dirty even if we are a failed 16911284Sandreas.hansson@arm.com // StoreCond so we supply data to any snoops that have 17011284Sandreas.hansson@arm.com // appended themselves to this cache before knowing the store 17111284Sandreas.hansson@arm.com // will fail. 17211284Sandreas.hansson@arm.com blk->status |= BlkDirty; 17311051Sandreas.hansson@arm.com DPRINTF(Cache, "%s for %s addr %#llx size %d (write)\n", __func__, 17411284Sandreas.hansson@arm.com pkt->cmdString(), pkt->getAddr(), pkt->getSize()); 17511051Sandreas.hansson@arm.com } else if (pkt->isRead()) { 17611051Sandreas.hansson@arm.com if (pkt->isLLSC()) { 17711051Sandreas.hansson@arm.com blk->trackLoadLocked(pkt); 17811284Sandreas.hansson@arm.com } 17911284Sandreas.hansson@arm.com pkt->setDataFromBlock(blk->data, blkSize); 18011284Sandreas.hansson@arm.com // determine if this read is from a (coherent) cache, or not 18111284Sandreas.hansson@arm.com // by looking at the command type; we could potentially add a 18211051Sandreas.hansson@arm.com // packet attribute such as 'FromCache' to make this check a 18311744Snikos.nikoleris@arm.com // bit cleaner 18411051Sandreas.hansson@arm.com if (pkt->cmd == MemCmd::ReadExReq || 18511051Sandreas.hansson@arm.com pkt->cmd == MemCmd::ReadSharedReq || 18611051Sandreas.hansson@arm.com pkt->cmd == MemCmd::ReadCleanReq || 18711051Sandreas.hansson@arm.com pkt->cmd == MemCmd::SCUpgradeFailReq) { 18811286Sandreas.hansson@arm.com assert(pkt->getSize() == blkSize); 18911286Sandreas.hansson@arm.com // special handling for coherent block requests from 19011286Sandreas.hansson@arm.com // upper-level caches 19111051Sandreas.hansson@arm.com if (pkt->needsExclusive()) { 19211286Sandreas.hansson@arm.com // sanity check 19311600Sandreas.hansson@arm.com assert(pkt->cmd == MemCmd::ReadExReq || 19411600Sandreas.hansson@arm.com pkt->cmd == MemCmd::SCUpgradeFailReq); 19511051Sandreas.hansson@arm.com 19611051Sandreas.hansson@arm.com // if we have a dirty copy, make sure the recipient 19711051Sandreas.hansson@arm.com // keeps it marked dirty 19811284Sandreas.hansson@arm.com if (blk->isDirty()) { 19911051Sandreas.hansson@arm.com pkt->assertMemInhibit(); 20011051Sandreas.hansson@arm.com } 20111051Sandreas.hansson@arm.com // on ReadExReq we give up our copy unconditionally 20211602Sandreas.hansson@arm.com if (blk != tempBlock) 20311051Sandreas.hansson@arm.com tags->invalidate(blk); 20411051Sandreas.hansson@arm.com blk->invalidate(); 20511284Sandreas.hansson@arm.com } else if (blk->isWritable() && !pending_downgrade && 20611051Sandreas.hansson@arm.com !pkt->sharedAsserted() && 20711284Sandreas.hansson@arm.com pkt->cmd != MemCmd::ReadCleanReq) { 20811602Sandreas.hansson@arm.com // we can give the requester an exclusive copy (by not 20911051Sandreas.hansson@arm.com // asserting shared line) on a read request if: 21011051Sandreas.hansson@arm.com // - we have an exclusive copy at this level (& below) 21111284Sandreas.hansson@arm.com // - we don't have a pending snoop from below 21211051Sandreas.hansson@arm.com // signaling another read request 21311284Sandreas.hansson@arm.com // - no other cache above has a copy (otherwise it 21411284Sandreas.hansson@arm.com // would have asseretd shared line on request) 21511284Sandreas.hansson@arm.com // - we are not satisfying an instruction fetch (this 21611051Sandreas.hansson@arm.com // prevents dirty data in the i-cache) 21711051Sandreas.hansson@arm.com 21811051Sandreas.hansson@arm.com if (blk->isDirty()) { 21911284Sandreas.hansson@arm.com // special considerations if we're owner: 22011284Sandreas.hansson@arm.com if (!deferred_response) { 22111284Sandreas.hansson@arm.com // if we are responding immediately and can 22211284Sandreas.hansson@arm.com // signal that we're transferring ownership 22311051Sandreas.hansson@arm.com // along with exclusivity, do so 22411051Sandreas.hansson@arm.com pkt->assertMemInhibit(); 22511051Sandreas.hansson@arm.com blk->status &= ~BlkDirty; 22611284Sandreas.hansson@arm.com } else { 22711284Sandreas.hansson@arm.com // if we're responding after our own miss, 22811284Sandreas.hansson@arm.com // there's a window where the recipient didn't 22911197Sandreas.hansson@arm.com // know it was getting ownership and may not 23011601Sandreas.hansson@arm.com // have responded to snoops correctly, so we 23111601Sandreas.hansson@arm.com // can't pass off ownership *or* exclusivity 23211601Sandreas.hansson@arm.com pkt->assertShared(); 23311601Sandreas.hansson@arm.com } 23411601Sandreas.hansson@arm.com } 23511601Sandreas.hansson@arm.com } else { 23611601Sandreas.hansson@arm.com // otherwise only respond with a shared copy 23711601Sandreas.hansson@arm.com pkt->assertShared(); 23811197Sandreas.hansson@arm.com } 23911601Sandreas.hansson@arm.com } 24011601Sandreas.hansson@arm.com } else { 24111601Sandreas.hansson@arm.com // Upgrade or Invalidate, since we have it Exclusively (E or 24211601Sandreas.hansson@arm.com // M), we ack then invalidate. 24311601Sandreas.hansson@arm.com assert(pkt->isUpgrade() || pkt->isInvalidate()); 24411601Sandreas.hansson@arm.com assert(blk != tempBlock); 24511601Sandreas.hansson@arm.com tags->invalidate(blk); 24611051Sandreas.hansson@arm.com blk->invalidate(); 24711051Sandreas.hansson@arm.com DPRINTF(Cache, "%s for %s addr %#llx size %d (invalidation)\n", 24811051Sandreas.hansson@arm.com __func__, pkt->cmdString(), pkt->getAddr(), pkt->getSize()); 24911051Sandreas.hansson@arm.com } 25011051Sandreas.hansson@arm.com} 25111284Sandreas.hansson@arm.com 25211284Sandreas.hansson@arm.com 25311051Sandreas.hansson@arm.com///////////////////////////////////////////////////// 25411051Sandreas.hansson@arm.com// 25511051Sandreas.hansson@arm.com// MSHR helper functions 25611051Sandreas.hansson@arm.com// 25711284Sandreas.hansson@arm.com///////////////////////////////////////////////////// 25811051Sandreas.hansson@arm.com 25911051Sandreas.hansson@arm.com 26011602Sandreas.hansson@arm.comvoid 26111602Sandreas.hansson@arm.comCache::markInService(MSHR *mshr, bool pending_dirty_resp) 26211602Sandreas.hansson@arm.com{ 26311602Sandreas.hansson@arm.com markInServiceInternal(mshr, pending_dirty_resp); 26411602Sandreas.hansson@arm.com} 26511602Sandreas.hansson@arm.com 26611602Sandreas.hansson@arm.com 26711602Sandreas.hansson@arm.comvoid 26811602Sandreas.hansson@arm.comCache::squash(int threadNum) 26911602Sandreas.hansson@arm.com{ 27011602Sandreas.hansson@arm.com bool unblock = false; 27111051Sandreas.hansson@arm.com BlockedCause cause = NUM_BLOCKED_CAUSES; 27211602Sandreas.hansson@arm.com 27311197Sandreas.hansson@arm.com if (noTargetMSHR && noTargetMSHR->threadNum == threadNum) { 27411744Snikos.nikoleris@arm.com noTargetMSHR = NULL; 27511744Snikos.nikoleris@arm.com unblock = true; 27611051Sandreas.hansson@arm.com cause = Blocked_NoTargets; 27711051Sandreas.hansson@arm.com } 27811051Sandreas.hansson@arm.com if (mshrQueue.isFull()) { 27911051Sandreas.hansson@arm.com unblock = true; 28011051Sandreas.hansson@arm.com cause = Blocked_NoMSHRs; 28111051Sandreas.hansson@arm.com } 28211051Sandreas.hansson@arm.com mshrQueue.squash(threadNum); 28311051Sandreas.hansson@arm.com if (unblock && !mshrQueue.isFull()) { 28411051Sandreas.hansson@arm.com clearBlocked(cause); 28511051Sandreas.hansson@arm.com } 28611051Sandreas.hansson@arm.com} 28711051Sandreas.hansson@arm.com 28811051Sandreas.hansson@arm.com///////////////////////////////////////////////////// 28911051Sandreas.hansson@arm.com// 29011051Sandreas.hansson@arm.com// Access path: requests coming in from the CPU side 29111051Sandreas.hansson@arm.com// 29211051Sandreas.hansson@arm.com///////////////////////////////////////////////////// 29311051Sandreas.hansson@arm.com 29411051Sandreas.hansson@arm.combool 29511051Sandreas.hansson@arm.comCache::access(PacketPtr pkt, CacheBlk *&blk, Cycles &lat, 29611744Snikos.nikoleris@arm.com PacketList &writebacks) 29711051Sandreas.hansson@arm.com{ 29811051Sandreas.hansson@arm.com // sanity check 29911744Snikos.nikoleris@arm.com assert(pkt->isRequest()); 30011051Sandreas.hansson@arm.com 30111051Sandreas.hansson@arm.com chatty_assert(!(isReadOnly && pkt->isWrite()), 30211051Sandreas.hansson@arm.com "Should never see a write in a read-only cache %s\n", 30311051Sandreas.hansson@arm.com name()); 30411199Sandreas.hansson@arm.com 30511051Sandreas.hansson@arm.com DPRINTF(Cache, "%s for %s addr %#llx size %d\n", __func__, 30611051Sandreas.hansson@arm.com pkt->cmdString(), pkt->getAddr(), pkt->getSize()); 30711051Sandreas.hansson@arm.com 30811867Snikos.nikoleris@arm.com if (pkt->req->isUncacheable()) { 30911051Sandreas.hansson@arm.com DPRINTF(Cache, "%s%s addr %#llx uncacheable\n", pkt->cmdString(), 31011051Sandreas.hansson@arm.com pkt->req->isInstFetch() ? " (ifetch)" : "", 31111484Snikos.nikoleris@arm.com pkt->getAddr()); 31211051Sandreas.hansson@arm.com 31311051Sandreas.hansson@arm.com if (pkt->req->isClearLL()) 31411051Sandreas.hansson@arm.com tags->clearLocks(); 31511051Sandreas.hansson@arm.com 31611051Sandreas.hansson@arm.com // flush and invalidate any existing block 31711051Sandreas.hansson@arm.com CacheBlk *old_blk(tags->findBlock(pkt->getAddr(), pkt->isSecure())); 31811051Sandreas.hansson@arm.com if (old_blk && old_blk->isValid()) { 31911870Snikos.nikoleris@arm.com if (old_blk->isDirty()) 32011051Sandreas.hansson@arm.com writebacks.push_back(writebackBlk(old_blk)); 32111744Snikos.nikoleris@arm.com else 32211051Sandreas.hansson@arm.com writebacks.push_back(cleanEvictBlk(old_blk)); 32311051Sandreas.hansson@arm.com tags->invalidate(old_blk); 32411051Sandreas.hansson@arm.com old_blk->invalidate(); 32511199Sandreas.hansson@arm.com } 32611051Sandreas.hansson@arm.com 32711051Sandreas.hansson@arm.com blk = NULL; 32811051Sandreas.hansson@arm.com // lookupLatency is the latency in case the request is uncacheable. 32911051Sandreas.hansson@arm.com lat = lookupLatency; 33011051Sandreas.hansson@arm.com return false; 33111051Sandreas.hansson@arm.com } 33211051Sandreas.hansson@arm.com 33311051Sandreas.hansson@arm.com ContextID id = pkt->req->hasContextId() ? 33411375Sandreas.hansson@arm.com pkt->req->contextId() : InvalidContextID; 33511375Sandreas.hansson@arm.com // Here lat is the value passed as parameter to accessBlock() function 33611375Sandreas.hansson@arm.com // that can modify its value. 33711199Sandreas.hansson@arm.com blk = tags->accessBlock(pkt->getAddr(), pkt->isSecure(), lat, id); 33811199Sandreas.hansson@arm.com 33911199Sandreas.hansson@arm.com DPRINTF(Cache, "%s%s addr %#llx size %d (%s) %s\n", pkt->cmdString(), 34011199Sandreas.hansson@arm.com pkt->req->isInstFetch() ? " (ifetch)" : "", 34111199Sandreas.hansson@arm.com pkt->getAddr(), pkt->getSize(), pkt->isSecure() ? "s" : "ns", 34211199Sandreas.hansson@arm.com blk ? "hit " + blk->print() : "miss"); 34311199Sandreas.hansson@arm.com 34411199Sandreas.hansson@arm.com 34511199Sandreas.hansson@arm.com if (pkt->evictingBlock()) { 34611199Sandreas.hansson@arm.com // We check for presence of block in above caches before issuing 34711199Sandreas.hansson@arm.com // Writeback or CleanEvict to write buffer. Therefore the only 34811199Sandreas.hansson@arm.com // possible cases can be of a CleanEvict packet coming from above 34911199Sandreas.hansson@arm.com // encountering a Writeback generated in this cache peer cache and 35011199Sandreas.hansson@arm.com // waiting in the write buffer. Cases of upper level peer caches 35111199Sandreas.hansson@arm.com // generating CleanEvict and Writeback or simply CleanEvict and 35211199Sandreas.hansson@arm.com // CleanEvict almost simultaneously will be caught by snoops sent out 35311199Sandreas.hansson@arm.com // by crossbar. 35411199Sandreas.hansson@arm.com std::vector<MSHR *> outgoing; 35511199Sandreas.hansson@arm.com if (writeBuffer.findMatches(pkt->getAddr(), pkt->isSecure(), 35611199Sandreas.hansson@arm.com outgoing)) { 35711375Sandreas.hansson@arm.com assert(outgoing.size() == 1); 35811199Sandreas.hansson@arm.com PacketPtr wbPkt = outgoing[0]->getTarget()->pkt; 35911199Sandreas.hansson@arm.com assert(pkt->cmd == MemCmd::CleanEvict && 36011051Sandreas.hansson@arm.com wbPkt->cmd == MemCmd::Writeback); 36111051Sandreas.hansson@arm.com // As the CleanEvict is coming from above, it would have snooped 36211051Sandreas.hansson@arm.com // into other peer caches of the same level while traversing the 36311051Sandreas.hansson@arm.com // crossbar. If a copy of the block had been found, the CleanEvict 36411051Sandreas.hansson@arm.com // would have been deleted in the crossbar. Now that the 36511199Sandreas.hansson@arm.com // CleanEvict is here we can be sure none of the other upper level 36611051Sandreas.hansson@arm.com // caches connected to this cache have the block, so we can clear 36711199Sandreas.hansson@arm.com // the BLOCK_CACHED flag in the Writeback if set and discard the 36811199Sandreas.hansson@arm.com // CleanEvict by returning true. 36911199Sandreas.hansson@arm.com wbPkt->clearBlockCached(); 37011199Sandreas.hansson@arm.com return true; 37111199Sandreas.hansson@arm.com } 37211199Sandreas.hansson@arm.com } 37311199Sandreas.hansson@arm.com 37411199Sandreas.hansson@arm.com // Writeback handling is special case. We can write the block into 37511199Sandreas.hansson@arm.com // the cache without having a writeable copy (or any copy at all). 37611199Sandreas.hansson@arm.com if (pkt->cmd == MemCmd::Writeback) { 37711199Sandreas.hansson@arm.com assert(blkSize == pkt->getSize()); 37811199Sandreas.hansson@arm.com if (blk == NULL) { 37911484Snikos.nikoleris@arm.com // need to do a replacement 38011051Sandreas.hansson@arm.com blk = allocateBlock(pkt->getAddr(), pkt->isSecure(), writebacks); 38111051Sandreas.hansson@arm.com if (blk == NULL) { 38211484Snikos.nikoleris@arm.com // no replaceable block available: give up, fwd to next level. 38311051Sandreas.hansson@arm.com incMissCount(pkt); 38411051Sandreas.hansson@arm.com return false; 38511051Sandreas.hansson@arm.com } 38611051Sandreas.hansson@arm.com tags->insertBlock(pkt, blk); 38711051Sandreas.hansson@arm.com 38811051Sandreas.hansson@arm.com blk->status = (BlkValid | BlkReadable); 38911051Sandreas.hansson@arm.com if (pkt->isSecure()) { 39011051Sandreas.hansson@arm.com blk->status |= BlkSecure; 39111051Sandreas.hansson@arm.com } 39211051Sandreas.hansson@arm.com } 39311051Sandreas.hansson@arm.com blk->status |= BlkDirty; 39411199Sandreas.hansson@arm.com // if shared is not asserted we got the writeback in modified 39511199Sandreas.hansson@arm.com // state, if it is asserted we are in the owned state 39611199Sandreas.hansson@arm.com if (!pkt->sharedAsserted()) { 39711199Sandreas.hansson@arm.com blk->status |= BlkWritable; 39811199Sandreas.hansson@arm.com } 39911284Sandreas.hansson@arm.com // nothing else to do; writeback doesn't expect response 40011284Sandreas.hansson@arm.com assert(!pkt->needsResponse()); 40111284Sandreas.hansson@arm.com std::memcpy(blk->data, pkt->getConstPtr<uint8_t>(), blkSize); 40211284Sandreas.hansson@arm.com DPRINTF(Cache, "%s new state is %s\n", __func__, blk->print()); 40311051Sandreas.hansson@arm.com incHitCount(pkt); 40411051Sandreas.hansson@arm.com return true; 40511051Sandreas.hansson@arm.com } else if (pkt->cmd == MemCmd::CleanEvict) { 40611051Sandreas.hansson@arm.com if (blk != NULL) { 40711051Sandreas.hansson@arm.com // Found the block in the tags, need to stop CleanEvict from 40811051Sandreas.hansson@arm.com // propagating further down the hierarchy. Returning true will 40911051Sandreas.hansson@arm.com // treat the CleanEvict like a satisfied write request and delete 41011051Sandreas.hansson@arm.com // it. 41111051Sandreas.hansson@arm.com return true; 41211484Snikos.nikoleris@arm.com } 41311051Sandreas.hansson@arm.com // We didn't find the block here, propagate the CleanEvict further 41411051Sandreas.hansson@arm.com // down the memory hierarchy. Returning false will treat the CleanEvict 41511051Sandreas.hansson@arm.com // like a Writeback which could not find a replaceable block so has to 41611051Sandreas.hansson@arm.com // go to next level. 41711051Sandreas.hansson@arm.com return false; 41811051Sandreas.hansson@arm.com } else if ((blk != NULL) && 41911051Sandreas.hansson@arm.com (pkt->needsExclusive() ? blk->isWritable() 42011051Sandreas.hansson@arm.com : blk->isReadable())) { 42111051Sandreas.hansson@arm.com // OK to satisfy access 42211051Sandreas.hansson@arm.com incHitCount(pkt); 42311051Sandreas.hansson@arm.com satisfyCpuSideRequest(pkt, blk); 42411601Sandreas.hansson@arm.com return true; 42511601Sandreas.hansson@arm.com } 42611051Sandreas.hansson@arm.com 42711051Sandreas.hansson@arm.com // Can't satisfy access normally... either no block (blk == NULL) 42811601Sandreas.hansson@arm.com // or have block but need exclusive & only have shared. 42911601Sandreas.hansson@arm.com 43011601Sandreas.hansson@arm.com incMissCount(pkt); 43111051Sandreas.hansson@arm.com 43211051Sandreas.hansson@arm.com if (blk == NULL && pkt->isLLSC() && pkt->isWrite()) { 43311051Sandreas.hansson@arm.com // complete miss on store conditional... just give up now 43411484Snikos.nikoleris@arm.com pkt->req->setExtraData(0); 43511284Sandreas.hansson@arm.com return true; 43611051Sandreas.hansson@arm.com } 43711051Sandreas.hansson@arm.com 43811051Sandreas.hansson@arm.com return false; 43911484Snikos.nikoleris@arm.com} 44011051Sandreas.hansson@arm.com 44111051Sandreas.hansson@arm.com 44211051Sandreas.hansson@arm.comclass ForwardResponseRecord : public Packet::SenderState 44311051Sandreas.hansson@arm.com{ 44411051Sandreas.hansson@arm.com public: 44511051Sandreas.hansson@arm.com 44611051Sandreas.hansson@arm.com ForwardResponseRecord() {} 44711051Sandreas.hansson@arm.com}; 44811051Sandreas.hansson@arm.com 44911601Sandreas.hansson@arm.comvoid 45011601Sandreas.hansson@arm.comCache::doWritebacks(PacketList& writebacks, Tick forward_time) 45111601Sandreas.hansson@arm.com{ 45211601Sandreas.hansson@arm.com while (!writebacks.empty()) { 45311601Sandreas.hansson@arm.com PacketPtr wbPkt = writebacks.front(); 45411601Sandreas.hansson@arm.com // We use forwardLatency here because we are copying writebacks to 45511601Sandreas.hansson@arm.com // write buffer. Call isCachedAbove for both Writebacks and 45611601Sandreas.hansson@arm.com // CleanEvicts. If isCachedAbove returns true we set BLOCK_CACHED flag 45711601Sandreas.hansson@arm.com // in Writebacks and discard CleanEvicts. 45811601Sandreas.hansson@arm.com if (isCachedAbove(wbPkt)) { 45911601Sandreas.hansson@arm.com if (wbPkt->cmd == MemCmd::CleanEvict) { 46011601Sandreas.hansson@arm.com // Delete CleanEvict because cached copies exist above. The 46111051Sandreas.hansson@arm.com // packet destructor will delete the request object because 46211051Sandreas.hansson@arm.com // this is a non-snoop request packet which does not require a 46311051Sandreas.hansson@arm.com // response. 46411051Sandreas.hansson@arm.com delete wbPkt; 46511051Sandreas.hansson@arm.com } else { 46611051Sandreas.hansson@arm.com // Set BLOCK_CACHED flag in Writeback and send below, so that 46711051Sandreas.hansson@arm.com // the Writeback does not reset the bit corresponding to this 46811051Sandreas.hansson@arm.com // address in the snoop filter below. 46911051Sandreas.hansson@arm.com wbPkt->setBlockCached(); 47011051Sandreas.hansson@arm.com allocateWriteBuffer(wbPkt, forward_time); 47111051Sandreas.hansson@arm.com } 47211051Sandreas.hansson@arm.com } else { 47311051Sandreas.hansson@arm.com // If the block is not cached above, send packet below. Both 47411051Sandreas.hansson@arm.com // CleanEvict and Writeback with BLOCK_CACHED flag cleared will 47511051Sandreas.hansson@arm.com // reset the bit corresponding to this address in the snoop filter 47611199Sandreas.hansson@arm.com // below. 47711199Sandreas.hansson@arm.com allocateWriteBuffer(wbPkt, forward_time); 47811199Sandreas.hansson@arm.com } 47911199Sandreas.hansson@arm.com writebacks.pop_front(); 48011199Sandreas.hansson@arm.com } 48111051Sandreas.hansson@arm.com} 48211199Sandreas.hansson@arm.com 48311051Sandreas.hansson@arm.com 48411051Sandreas.hansson@arm.comvoid 48511051Sandreas.hansson@arm.comCache::recvTimingSnoopResp(PacketPtr pkt) 48611051Sandreas.hansson@arm.com{ 48711051Sandreas.hansson@arm.com DPRINTF(Cache, "%s for %s addr %#llx size %d\n", __func__, 48811051Sandreas.hansson@arm.com pkt->cmdString(), pkt->getAddr(), pkt->getSize()); 48911051Sandreas.hansson@arm.com 49011051Sandreas.hansson@arm.com assert(pkt->isResponse()); 49111051Sandreas.hansson@arm.com 49211051Sandreas.hansson@arm.com // must be cache-to-cache response from upper to lower level 49311051Sandreas.hansson@arm.com ForwardResponseRecord *rec = 49411051Sandreas.hansson@arm.com dynamic_cast<ForwardResponseRecord *>(pkt->senderState); 49511051Sandreas.hansson@arm.com assert(!system->bypassCaches()); 49611051Sandreas.hansson@arm.com 49711051Sandreas.hansson@arm.com if (rec == NULL) { 49811051Sandreas.hansson@arm.com // @todo What guarantee do we have that this HardPFResp is 49911051Sandreas.hansson@arm.com // actually for this cache, and not a cache closer to the 50011130Sali.jafri@arm.com // memory? 50111130Sali.jafri@arm.com assert(pkt->cmd == MemCmd::HardPFResp); 50211130Sali.jafri@arm.com // Check if it's a prefetch response and handle it. We shouldn't 50311130Sali.jafri@arm.com // get any other kinds of responses without FRRs. 50411130Sali.jafri@arm.com DPRINTF(Cache, "Got prefetch response from above for addr %#llx (%s)\n", 50511130Sali.jafri@arm.com pkt->getAddr(), pkt->isSecure() ? "s" : "ns"); 50611130Sali.jafri@arm.com recvTimingResp(pkt); 50711130Sali.jafri@arm.com return; 50811130Sali.jafri@arm.com } 50911199Sandreas.hansson@arm.com 51011130Sali.jafri@arm.com pkt->popSenderState(); 51111130Sali.jafri@arm.com delete rec; 51211130Sali.jafri@arm.com // forwardLatency is set here because there is a response from an 51311130Sali.jafri@arm.com // upper level cache. 51411130Sali.jafri@arm.com // To pay the delay that occurs if the packet comes from the bus, 51511130Sali.jafri@arm.com // we charge also headerDelay. 51611130Sali.jafri@arm.com Tick snoop_resp_time = clockEdge(forwardLatency) + pkt->headerDelay; 51711130Sali.jafri@arm.com // Reset the timing of the packet. 51811130Sali.jafri@arm.com pkt->headerDelay = pkt->payloadDelay = 0; 51911130Sali.jafri@arm.com memSidePort->schedTimingSnoopResp(pkt, snoop_resp_time); 52011130Sali.jafri@arm.com} 52111130Sali.jafri@arm.com 52211130Sali.jafri@arm.comvoid 52311130Sali.jafri@arm.comCache::promoteWholeLineWrites(PacketPtr pkt) 52411130Sali.jafri@arm.com{ 52511130Sali.jafri@arm.com // Cache line clearing instructions 52611130Sali.jafri@arm.com if (doFastWrites && (pkt->cmd == MemCmd::WriteReq) && 52711130Sali.jafri@arm.com (pkt->getSize() == blkSize) && (pkt->getOffset(blkSize) == 0)) { 52811130Sali.jafri@arm.com pkt->cmd = MemCmd::WriteLineReq; 52911130Sali.jafri@arm.com DPRINTF(Cache, "packet promoted from Write to WriteLineReq\n"); 53011130Sali.jafri@arm.com } 53111130Sali.jafri@arm.com} 53211130Sali.jafri@arm.com 53311051Sandreas.hansson@arm.combool 53411051Sandreas.hansson@arm.comCache::recvTimingReq(PacketPtr pkt) 53511051Sandreas.hansson@arm.com{ 53611051Sandreas.hansson@arm.com DPRINTF(CacheTags, "%s tags: %s\n", __func__, tags->print()); 53711744Snikos.nikoleris@arm.com//@todo Add back in MemDebug Calls 53811051Sandreas.hansson@arm.com// MemDebug::cacheAccess(pkt); 53911051Sandreas.hansson@arm.com 54011051Sandreas.hansson@arm.com 54111051Sandreas.hansson@arm.com /// @todo temporary hack to deal with memory corruption issue until 54211276Sandreas.hansson@arm.com /// 4-phase transactions are complete 54311276Sandreas.hansson@arm.com for (int x = 0; x < pendingDelete.size(); x++) 54411276Sandreas.hansson@arm.com delete pendingDelete[x]; 54511276Sandreas.hansson@arm.com pendingDelete.clear(); 54611276Sandreas.hansson@arm.com 54711276Sandreas.hansson@arm.com assert(pkt->isRequest()); 54811276Sandreas.hansson@arm.com 54911276Sandreas.hansson@arm.com // Just forward the packet if caches are disabled. 55011276Sandreas.hansson@arm.com if (system->bypassCaches()) { 55111051Sandreas.hansson@arm.com // @todo This should really enqueue the packet rather 55211276Sandreas.hansson@arm.com bool M5_VAR_USED success = memSidePort->sendTimingReq(pkt); 55311276Sandreas.hansson@arm.com assert(success); 55411276Sandreas.hansson@arm.com return true; 55511276Sandreas.hansson@arm.com } 55611276Sandreas.hansson@arm.com 55711051Sandreas.hansson@arm.com promoteWholeLineWrites(pkt); 55811051Sandreas.hansson@arm.com 55911051Sandreas.hansson@arm.com if (pkt->memInhibitAsserted()) { 56011051Sandreas.hansson@arm.com // a cache above us (but not where the packet came from) is 56111051Sandreas.hansson@arm.com // responding to the request 56211051Sandreas.hansson@arm.com DPRINTF(Cache, "mem inhibited on addr %#llx (%s): not responding\n", 56311051Sandreas.hansson@arm.com pkt->getAddr(), pkt->isSecure() ? "s" : "ns"); 56411051Sandreas.hansson@arm.com 56511051Sandreas.hansson@arm.com // if the packet needs exclusive, and the cache that has 56611051Sandreas.hansson@arm.com // promised to respond (setting the inhibit flag) is not 56711051Sandreas.hansson@arm.com // providing exclusive (it is in O vs M state), we know that 56811051Sandreas.hansson@arm.com // there may be other shared copies in the system; go out and 56911051Sandreas.hansson@arm.com // invalidate them all 57011051Sandreas.hansson@arm.com if (pkt->needsExclusive() && !pkt->isSupplyExclusive()) { 57111051Sandreas.hansson@arm.com // create a downstream express snoop with cleared packet 57211051Sandreas.hansson@arm.com // flags, there is no need to allocate any data as the 57311051Sandreas.hansson@arm.com // packet is merely used to co-ordinate state transitions 57411051Sandreas.hansson@arm.com Packet *snoop_pkt = new Packet(pkt, true, false); 57511051Sandreas.hansson@arm.com 57611051Sandreas.hansson@arm.com // also reset the bus time that the original packet has 57711051Sandreas.hansson@arm.com // not yet paid for 57811051Sandreas.hansson@arm.com snoop_pkt->headerDelay = snoop_pkt->payloadDelay = 0; 57911051Sandreas.hansson@arm.com 58011051Sandreas.hansson@arm.com // make this an instantaneous express snoop, and let the 58111051Sandreas.hansson@arm.com // other caches in the system know that the packet is 58211051Sandreas.hansson@arm.com // inhibited, because we have found the authorative copy 58311051Sandreas.hansson@arm.com // (O) that will supply the right data 58411051Sandreas.hansson@arm.com snoop_pkt->setExpressSnoop(); 58511830Sbaz21@cam.ac.uk snoop_pkt->assertMemInhibit(); 58611051Sandreas.hansson@arm.com 58711051Sandreas.hansson@arm.com // this express snoop travels towards the memory, and at 58811051Sandreas.hansson@arm.com // every crossbar it is snooped upwards thus reaching 58911051Sandreas.hansson@arm.com // every cache in the system 59011051Sandreas.hansson@arm.com bool M5_VAR_USED success = memSidePort->sendTimingReq(snoop_pkt); 59111051Sandreas.hansson@arm.com // express snoops always succeed 59211051Sandreas.hansson@arm.com assert(success); 59311051Sandreas.hansson@arm.com 59411051Sandreas.hansson@arm.com // main memory will delete the packet 59511051Sandreas.hansson@arm.com } 59611051Sandreas.hansson@arm.com 59711051Sandreas.hansson@arm.com /// @todo nominally we should just delete the packet here, 59811051Sandreas.hansson@arm.com /// however, until 4-phase stuff we can't because sending 59911284Sandreas.hansson@arm.com /// cache is still relying on it. 60011051Sandreas.hansson@arm.com pendingDelete.push_back(pkt); 60111284Sandreas.hansson@arm.com 60211284Sandreas.hansson@arm.com // no need to take any action in this particular cache as the 60311744Snikos.nikoleris@arm.com // caches along the path to memory are allowed to keep lines 60411744Snikos.nikoleris@arm.com // in a shared state, and a cache above us already committed 60511051Sandreas.hansson@arm.com // to responding 60611284Sandreas.hansson@arm.com return true; 60711284Sandreas.hansson@arm.com } 60811284Sandreas.hansson@arm.com 60911284Sandreas.hansson@arm.com // anything that is merely forwarded pays for the forward latency and 61011284Sandreas.hansson@arm.com // the delay provided by the crossbar 61111334Sandreas.hansson@arm.com Tick forward_time = clockEdge(forwardLatency) + pkt->headerDelay; 61211284Sandreas.hansson@arm.com 61311334Sandreas.hansson@arm.com // We use lookupLatency here because it is used to specify the latency 61411334Sandreas.hansson@arm.com // to access. 61511334Sandreas.hansson@arm.com Cycles lat = lookupLatency; 61611334Sandreas.hansson@arm.com CacheBlk *blk = NULL; 61711284Sandreas.hansson@arm.com bool satisfied = false; 61811334Sandreas.hansson@arm.com { 61911334Sandreas.hansson@arm.com PacketList writebacks; 62011334Sandreas.hansson@arm.com // Note that lat is passed by reference here. The function 62111334Sandreas.hansson@arm.com // access() calls accessBlock() which can modify lat value. 62211334Sandreas.hansson@arm.com satisfied = access(pkt, blk, lat, writebacks); 62311334Sandreas.hansson@arm.com 62411051Sandreas.hansson@arm.com // copy writebacks to write buffer here to ensure they logically 62511334Sandreas.hansson@arm.com // proceed anything happening below 62611334Sandreas.hansson@arm.com doWritebacks(writebacks, forward_time); 62711334Sandreas.hansson@arm.com } 62811334Sandreas.hansson@arm.com 62911051Sandreas.hansson@arm.com // Here we charge the headerDelay that takes into account the latencies 63011334Sandreas.hansson@arm.com // of the bus, if the packet comes from it. 63111334Sandreas.hansson@arm.com // The latency charged it is just lat that is the value of lookupLatency 63211334Sandreas.hansson@arm.com // modified by access() function, or if not just lookupLatency. 63311051Sandreas.hansson@arm.com // In case of a hit we are neglecting response latency. 63411334Sandreas.hansson@arm.com // In case of a miss we are neglecting forward latency. 63511334Sandreas.hansson@arm.com Tick request_time = clockEdge(lat) + pkt->headerDelay; 63611334Sandreas.hansson@arm.com // Here we reset the timing of the packet. 63711334Sandreas.hansson@arm.com pkt->headerDelay = pkt->payloadDelay = 0; 63811334Sandreas.hansson@arm.com 63911334Sandreas.hansson@arm.com // track time of availability of next prefetch, if any 64011334Sandreas.hansson@arm.com Tick next_pf_time = MaxTick; 64111051Sandreas.hansson@arm.com 64211334Sandreas.hansson@arm.com bool needsResponse = pkt->needsResponse(); 64311334Sandreas.hansson@arm.com 64411334Sandreas.hansson@arm.com if (satisfied) { 64511334Sandreas.hansson@arm.com // should never be satisfying an uncacheable access as we 64611334Sandreas.hansson@arm.com // flush and invalidate any existing block as part of the 64711334Sandreas.hansson@arm.com // lookup 64811334Sandreas.hansson@arm.com assert(!pkt->req->isUncacheable()); 64911334Sandreas.hansson@arm.com 65011051Sandreas.hansson@arm.com // hit (for all other request types) 65111284Sandreas.hansson@arm.com 65211284Sandreas.hansson@arm.com if (prefetcher && (prefetchOnAccess || (blk && blk->wasPrefetched()))) { 65311190Sandreas.hansson@arm.com if (blk) 65411051Sandreas.hansson@arm.com blk->status &= ~BlkHWPrefetched; 65511334Sandreas.hansson@arm.com 65611334Sandreas.hansson@arm.com // Don't notify on SWPrefetch 65711334Sandreas.hansson@arm.com if (!pkt->cmd.isSWPrefetch()) 65811334Sandreas.hansson@arm.com next_pf_time = prefetcher->notify(pkt); 65911334Sandreas.hansson@arm.com } 66011051Sandreas.hansson@arm.com 66111051Sandreas.hansson@arm.com if (needsResponse) { 66211051Sandreas.hansson@arm.com pkt->makeTimingResponse(); 66311051Sandreas.hansson@arm.com // @todo: Make someone pay for this 66411051Sandreas.hansson@arm.com pkt->headerDelay = pkt->payloadDelay = 0; 66511051Sandreas.hansson@arm.com 66611051Sandreas.hansson@arm.com // In this case we are considering request_time that takes 66711051Sandreas.hansson@arm.com // into account the delay of the xbar, if any, and just 66811051Sandreas.hansson@arm.com // lat, neglecting responseLatency, modelling hit latency 66911051Sandreas.hansson@arm.com // just as lookupLatency or or the value of lat overriden 67011484Snikos.nikoleris@arm.com // by access(), that calls accessBlock() function. 67111051Sandreas.hansson@arm.com cpuSidePort->schedTimingResp(pkt, request_time); 67211051Sandreas.hansson@arm.com } else { 67311051Sandreas.hansson@arm.com /// @todo nominally we should just delete the packet here, 67411051Sandreas.hansson@arm.com /// however, until 4-phase stuff we can't because sending cache is 67511051Sandreas.hansson@arm.com /// still relying on it. If the block is found in access(), 67611051Sandreas.hansson@arm.com /// CleanEvict and Writeback messages will be deleted here as 67711051Sandreas.hansson@arm.com /// well. 67811051Sandreas.hansson@arm.com pendingDelete.push_back(pkt); 67911051Sandreas.hansson@arm.com } 68011051Sandreas.hansson@arm.com } else { 68111051Sandreas.hansson@arm.com // miss 68211051Sandreas.hansson@arm.com 68311051Sandreas.hansson@arm.com Addr blk_addr = blockAlign(pkt->getAddr()); 68411051Sandreas.hansson@arm.com 68511051Sandreas.hansson@arm.com // ignore any existing MSHR if we are dealing with an 68611051Sandreas.hansson@arm.com // uncacheable request 68711051Sandreas.hansson@arm.com MSHR *mshr = pkt->req->isUncacheable() ? nullptr : 68811051Sandreas.hansson@arm.com mshrQueue.findMatch(blk_addr, pkt->isSecure()); 68911051Sandreas.hansson@arm.com 69011051Sandreas.hansson@arm.com // Software prefetch handling: 69111051Sandreas.hansson@arm.com // To keep the core from waiting on data it won't look at 69211051Sandreas.hansson@arm.com // anyway, send back a response with dummy data. Miss handling 69311051Sandreas.hansson@arm.com // will continue asynchronously. Unfortunately, the core will 69411051Sandreas.hansson@arm.com // insist upon freeing original Packet/Request, so we have to 69511051Sandreas.hansson@arm.com // create a new pair with a different lifecycle. Note that this 69611051Sandreas.hansson@arm.com // processing happens before any MSHR munging on the behalf of 69711051Sandreas.hansson@arm.com // this request because this new Request will be the one stored 69811051Sandreas.hansson@arm.com // into the MSHRs, not the original. 69911051Sandreas.hansson@arm.com if (pkt->cmd.isSWPrefetch()) { 70011051Sandreas.hansson@arm.com assert(needsResponse); 70111051Sandreas.hansson@arm.com assert(pkt->req->hasPaddr()); 70211051Sandreas.hansson@arm.com assert(!pkt->req->isUncacheable()); 70311051Sandreas.hansson@arm.com 70411051Sandreas.hansson@arm.com // There's no reason to add a prefetch as an additional target 70511051Sandreas.hansson@arm.com // to an existing MSHR. If an outstanding request is already 70611483Snikos.nikoleris@arm.com // in progress, there is nothing for the prefetch to do. 70711483Snikos.nikoleris@arm.com // If this is the case, we don't even create a request at all. 70811051Sandreas.hansson@arm.com PacketPtr pf = nullptr; 70911051Sandreas.hansson@arm.com 71011051Sandreas.hansson@arm.com if (!mshr) { 71111051Sandreas.hansson@arm.com // copy the request and create a new SoftPFReq packet 71211051Sandreas.hansson@arm.com RequestPtr req = new Request(pkt->req->getPaddr(), 71311051Sandreas.hansson@arm.com pkt->req->getSize(), 71411051Sandreas.hansson@arm.com pkt->req->getFlags(), 71511051Sandreas.hansson@arm.com pkt->req->masterId()); 71611051Sandreas.hansson@arm.com pf = new Packet(req, pkt->cmd); 71711051Sandreas.hansson@arm.com pf->allocate(); 71811051Sandreas.hansson@arm.com assert(pf->getAddr() == pkt->getAddr()); 71911051Sandreas.hansson@arm.com assert(pf->getSize() == pkt->getSize()); 72011051Sandreas.hansson@arm.com } 72111051Sandreas.hansson@arm.com 72211051Sandreas.hansson@arm.com pkt->makeTimingResponse(); 72311051Sandreas.hansson@arm.com // for debugging, set all the bits in the response data 72411051Sandreas.hansson@arm.com // (also keeps valgrind from complaining when debugging settings 72511051Sandreas.hansson@arm.com // print out instruction results) 72611194Sali.jafri@arm.com std::memset(pkt->getPtr<uint8_t>(), 0xFF, pkt->getSize()); 72711051Sandreas.hansson@arm.com // request_time is used here, taking into account lat and the delay 72811744Snikos.nikoleris@arm.com // charged if the packet comes from the xbar. 72911744Snikos.nikoleris@arm.com cpuSidePort->schedTimingResp(pkt, request_time); 73011199Sandreas.hansson@arm.com 73111190Sandreas.hansson@arm.com // If an outstanding request is in progress (we found an 73211190Sandreas.hansson@arm.com // MSHR) this is set to null 73311190Sandreas.hansson@arm.com pkt = pf; 73411190Sandreas.hansson@arm.com } 73511190Sandreas.hansson@arm.com 73611051Sandreas.hansson@arm.com if (mshr) { 73711051Sandreas.hansson@arm.com /// MSHR hit 73811051Sandreas.hansson@arm.com /// @note writebacks will be checked in getNextMSHR() 73911051Sandreas.hansson@arm.com /// for any conflicting requests to the same block 74011892Snikos.nikoleris@arm.com 74111051Sandreas.hansson@arm.com //@todo remove hw_pf here 74211051Sandreas.hansson@arm.com 74311051Sandreas.hansson@arm.com // Coalesce unless it was a software prefetch (see above). 74411051Sandreas.hansson@arm.com if (pkt) { 74511051Sandreas.hansson@arm.com assert(pkt->cmd != MemCmd::Writeback); 74611051Sandreas.hansson@arm.com // CleanEvicts corresponding to blocks which have outstanding 74711051Sandreas.hansson@arm.com // requests in MSHRs can be deleted here. 74811051Sandreas.hansson@arm.com if (pkt->cmd == MemCmd::CleanEvict) { 74911051Sandreas.hansson@arm.com pendingDelete.push_back(pkt); 75011051Sandreas.hansson@arm.com } else { 75111051Sandreas.hansson@arm.com DPRINTF(Cache, "%s coalescing MSHR for %s addr %#llx size %d\n", 75211051Sandreas.hansson@arm.com __func__, pkt->cmdString(), pkt->getAddr(), 75311051Sandreas.hansson@arm.com pkt->getSize()); 75411051Sandreas.hansson@arm.com 75511051Sandreas.hansson@arm.com assert(pkt->req->masterId() < system->maxMasters()); 75611051Sandreas.hansson@arm.com mshr_hits[pkt->cmdToIndex()][pkt->req->masterId()]++; 75711051Sandreas.hansson@arm.com if (mshr->threadNum != 0/*pkt->req->threadId()*/) { 75811051Sandreas.hansson@arm.com mshr->threadNum = -1; 75911051Sandreas.hansson@arm.com } 76011051Sandreas.hansson@arm.com // We use forward_time here because it is the same 76111051Sandreas.hansson@arm.com // considering new targets. We have multiple 76211051Sandreas.hansson@arm.com // requests for the same address here. It 76311051Sandreas.hansson@arm.com // specifies the latency to allocate an internal 76411051Sandreas.hansson@arm.com // buffer and to schedule an event to the queued 76511051Sandreas.hansson@arm.com // port and also takes into account the additional 76611051Sandreas.hansson@arm.com // delay of the xbar. 76711051Sandreas.hansson@arm.com mshr->allocateTarget(pkt, forward_time, order++); 76811051Sandreas.hansson@arm.com if (mshr->getNumTargets() == numTarget) { 76911051Sandreas.hansson@arm.com noTargetMSHR = mshr; 77011051Sandreas.hansson@arm.com setBlocked(Blocked_NoTargets); 77111051Sandreas.hansson@arm.com // need to be careful with this... if this mshr isn't 77211051Sandreas.hansson@arm.com // ready yet (i.e. time > curTick()), we don't want to 77311051Sandreas.hansson@arm.com // move it ahead of mshrs that are ready 77411051Sandreas.hansson@arm.com // mshrQueue.moveToFront(mshr); 77511051Sandreas.hansson@arm.com } 77611051Sandreas.hansson@arm.com } 77711051Sandreas.hansson@arm.com // We should call the prefetcher reguardless if the request is 77811051Sandreas.hansson@arm.com // satisfied or not, reguardless if the request is in the MSHR or 77911051Sandreas.hansson@arm.com // not. The request could be a ReadReq hit, but still not 78011286Sandreas.hansson@arm.com // satisfied (potentially because of a prior write to the same 78111051Sandreas.hansson@arm.com // cache line. So, even when not satisfied, tehre is an MSHR 78211051Sandreas.hansson@arm.com // already allocated for this, we need to let the prefetcher know 78311194Sali.jafri@arm.com // about the request 78411051Sandreas.hansson@arm.com if (prefetcher) { 78511051Sandreas.hansson@arm.com // Don't notify on SWPrefetch 78611051Sandreas.hansson@arm.com if (!pkt->cmd.isSWPrefetch()) 78711051Sandreas.hansson@arm.com next_pf_time = prefetcher->notify(pkt); 78811051Sandreas.hansson@arm.com } 78911051Sandreas.hansson@arm.com } 79011051Sandreas.hansson@arm.com } else { 79111051Sandreas.hansson@arm.com // no MSHR 79211051Sandreas.hansson@arm.com assert(pkt->req->masterId() < system->maxMasters()); 79311051Sandreas.hansson@arm.com if (pkt->req->isUncacheable()) { 79411051Sandreas.hansson@arm.com mshr_uncacheable[pkt->cmdToIndex()][pkt->req->masterId()]++; 79511051Sandreas.hansson@arm.com } else { 79611051Sandreas.hansson@arm.com mshr_misses[pkt->cmdToIndex()][pkt->req->masterId()]++; 79711051Sandreas.hansson@arm.com } 79811051Sandreas.hansson@arm.com 79911199Sandreas.hansson@arm.com if (pkt->evictingBlock() || 80011199Sandreas.hansson@arm.com (pkt->req->isUncacheable() && pkt->isWrite())) { 80111199Sandreas.hansson@arm.com // We use forward_time here because there is an 80211051Sandreas.hansson@arm.com // uncached memory write, forwarded to WriteBuffer. 80311190Sandreas.hansson@arm.com allocateWriteBuffer(pkt, forward_time); 80411051Sandreas.hansson@arm.com } else { 80511744Snikos.nikoleris@arm.com if (blk && blk->isValid()) { 80611744Snikos.nikoleris@arm.com // should have flushed and have no valid block 80711051Sandreas.hansson@arm.com assert(!pkt->req->isUncacheable()); 80811051Sandreas.hansson@arm.com 80911051Sandreas.hansson@arm.com // If we have a write miss to a valid block, we 81011051Sandreas.hansson@arm.com // need to mark the block non-readable. Otherwise 81111051Sandreas.hansson@arm.com // if we allow reads while there's an outstanding 81211051Sandreas.hansson@arm.com // write miss, the read could return stale data 81311051Sandreas.hansson@arm.com // out of the cache block... a more aggressive 81411051Sandreas.hansson@arm.com // system could detect the overlap (if any) and 81511051Sandreas.hansson@arm.com // forward data out of the MSHRs, but we don't do 81611051Sandreas.hansson@arm.com // that yet. Note that we do need to leave the 81711197Sandreas.hansson@arm.com // block valid so that it stays in the cache, in 81811197Sandreas.hansson@arm.com // case we get an upgrade response (and hence no 81911051Sandreas.hansson@arm.com // new data) when the write miss completes. 82011051Sandreas.hansson@arm.com // As long as CPUs do proper store/load forwarding 82111051Sandreas.hansson@arm.com // internally, and have a sufficiently weak memory 82211051Sandreas.hansson@arm.com // model, this is probably unnecessary, but at some 82311051Sandreas.hansson@arm.com // point it must have seemed like we needed it... 82411051Sandreas.hansson@arm.com assert(pkt->needsExclusive()); 82511051Sandreas.hansson@arm.com assert(!blk->isWritable()); 82611051Sandreas.hansson@arm.com blk->status &= ~BlkReadable; 82711051Sandreas.hansson@arm.com } 82811051Sandreas.hansson@arm.com // Here we are using forward_time, modelling the latency of 82911483Snikos.nikoleris@arm.com // a miss (outbound) just as forwardLatency, neglecting the 83011483Snikos.nikoleris@arm.com // lookupLatency component. 83111051Sandreas.hansson@arm.com allocateMissBuffer(pkt, forward_time); 83211051Sandreas.hansson@arm.com } 83311483Snikos.nikoleris@arm.com 83411483Snikos.nikoleris@arm.com if (prefetcher) { 83511051Sandreas.hansson@arm.com // Don't notify on SWPrefetch 83611051Sandreas.hansson@arm.com if (!pkt->cmd.isSWPrefetch()) 83711051Sandreas.hansson@arm.com next_pf_time = prefetcher->notify(pkt); 83811051Sandreas.hansson@arm.com } 83911051Sandreas.hansson@arm.com } 84011051Sandreas.hansson@arm.com } 84111051Sandreas.hansson@arm.com 84211051Sandreas.hansson@arm.com if (next_pf_time != MaxTick) 84311051Sandreas.hansson@arm.com schedMemSideSendEvent(next_pf_time); 84411051Sandreas.hansson@arm.com 84511051Sandreas.hansson@arm.com return true; 84611051Sandreas.hansson@arm.com} 84711051Sandreas.hansson@arm.com 84811051Sandreas.hansson@arm.com 84911051Sandreas.hansson@arm.com// See comment in cache.hh. 85011199Sandreas.hansson@arm.comPacketPtr 85111051Sandreas.hansson@arm.comCache::getBusPacket(PacketPtr cpu_pkt, CacheBlk *blk, 85211051Sandreas.hansson@arm.com bool needsExclusive) const 85311051Sandreas.hansson@arm.com{ 85411051Sandreas.hansson@arm.com bool blkValid = blk && blk->isValid(); 85511051Sandreas.hansson@arm.com 85611051Sandreas.hansson@arm.com if (cpu_pkt->req->isUncacheable()) { 85711051Sandreas.hansson@arm.com // note that at the point we see the uncacheable request we 85811051Sandreas.hansson@arm.com // flush any block, but there could be an outstanding MSHR, 85911051Sandreas.hansson@arm.com // and the cache could have filled again before we actually 86011051Sandreas.hansson@arm.com // send out the forwarded uncacheable request (blk could thus 86111051Sandreas.hansson@arm.com // be non-null) 86211051Sandreas.hansson@arm.com return NULL; 86311051Sandreas.hansson@arm.com } 86411051Sandreas.hansson@arm.com 86511051Sandreas.hansson@arm.com if (!blkValid && 86611051Sandreas.hansson@arm.com (cpu_pkt->isUpgrade() || 86711051Sandreas.hansson@arm.com cpu_pkt->evictingBlock())) { 86811051Sandreas.hansson@arm.com // Writebacks that weren't allocated in access() and upgrades 86911051Sandreas.hansson@arm.com // from upper-level caches that missed completely just go 87011051Sandreas.hansson@arm.com // through. 87111051Sandreas.hansson@arm.com return NULL; 87211051Sandreas.hansson@arm.com } 87311051Sandreas.hansson@arm.com 87411051Sandreas.hansson@arm.com assert(cpu_pkt->needsResponse()); 87511284Sandreas.hansson@arm.com 87611051Sandreas.hansson@arm.com MemCmd cmd; 87711051Sandreas.hansson@arm.com // @TODO make useUpgrades a parameter. 87811051Sandreas.hansson@arm.com // Note that ownership protocols require upgrade, otherwise a 87911051Sandreas.hansson@arm.com // write miss on a shared owned block will generate a ReadExcl, 88011051Sandreas.hansson@arm.com // which will clobber the owned copy. 88111051Sandreas.hansson@arm.com const bool useUpgrades = true; 88211051Sandreas.hansson@arm.com if (blkValid && useUpgrades) { 88311051Sandreas.hansson@arm.com // only reason to be here is that blk is shared 88411051Sandreas.hansson@arm.com // (read-only) and we need exclusive 88511051Sandreas.hansson@arm.com assert(needsExclusive); 88611051Sandreas.hansson@arm.com assert(!blk->isWritable()); 88711051Sandreas.hansson@arm.com cmd = cpu_pkt->isLLSC() ? MemCmd::SCUpgradeReq : MemCmd::UpgradeReq; 88811051Sandreas.hansson@arm.com } else if (cpu_pkt->cmd == MemCmd::SCUpgradeFailReq || 88911051Sandreas.hansson@arm.com cpu_pkt->cmd == MemCmd::StoreCondFailReq) { 89011051Sandreas.hansson@arm.com // Even though this SC will fail, we still need to send out the 89111051Sandreas.hansson@arm.com // request and get the data to supply it to other snoopers in the case 89211051Sandreas.hansson@arm.com // where the determination the StoreCond fails is delayed due to 89311051Sandreas.hansson@arm.com // all caches not being on the same local bus. 89411051Sandreas.hansson@arm.com cmd = MemCmd::SCUpgradeFailReq; 89511051Sandreas.hansson@arm.com } else if (cpu_pkt->cmd == MemCmd::WriteLineReq) { 89611051Sandreas.hansson@arm.com // forward as invalidate to all other caches, this gives us 89711051Sandreas.hansson@arm.com // the line in exclusive state, and invalidates all other 89811051Sandreas.hansson@arm.com // copies 89911051Sandreas.hansson@arm.com cmd = MemCmd::InvalidateReq; 90011452Sandreas.hansson@arm.com } else { 90111452Sandreas.hansson@arm.com // block is invalid 90211051Sandreas.hansson@arm.com cmd = needsExclusive ? MemCmd::ReadExReq : 90311452Sandreas.hansson@arm.com (isReadOnly ? MemCmd::ReadCleanReq : MemCmd::ReadSharedReq); 90411452Sandreas.hansson@arm.com } 90511452Sandreas.hansson@arm.com PacketPtr pkt = new Packet(cpu_pkt->req, cmd, blkSize); 90611051Sandreas.hansson@arm.com 90711051Sandreas.hansson@arm.com // if there are sharers in the upper levels, pass that info downstream 90811452Sandreas.hansson@arm.com if (cpu_pkt->sharedAsserted()) { 90911745Sandreas.hansson@arm.com // note that cpu_pkt may have spent a considerable time in the 91011745Sandreas.hansson@arm.com // MSHR queue and that the information could possibly be out 91111452Sandreas.hansson@arm.com // of date, however, there is no harm in conservatively 91211452Sandreas.hansson@arm.com // assuming the block is shared 91311452Sandreas.hansson@arm.com pkt->assertShared(); 91411051Sandreas.hansson@arm.com DPRINTF(Cache, "%s passing shared from %s to %s addr %#llx size %d\n", 91511051Sandreas.hansson@arm.com __func__, cpu_pkt->cmdString(), pkt->cmdString(), 91611051Sandreas.hansson@arm.com pkt->getAddr(), pkt->getSize()); 91711051Sandreas.hansson@arm.com } 91811051Sandreas.hansson@arm.com 91911051Sandreas.hansson@arm.com // the packet should be block aligned 92011051Sandreas.hansson@arm.com assert(pkt->getAddr() == blockAlign(pkt->getAddr())); 92111051Sandreas.hansson@arm.com 92211051Sandreas.hansson@arm.com pkt->allocate(); 92311051Sandreas.hansson@arm.com DPRINTF(Cache, "%s created %s from %s for addr %#llx size %d\n", 92411747Snikos.nikoleris@arm.com __func__, pkt->cmdString(), cpu_pkt->cmdString(), pkt->getAddr(), 92511747Snikos.nikoleris@arm.com pkt->getSize()); 92611747Snikos.nikoleris@arm.com return pkt; 92711747Snikos.nikoleris@arm.com} 92811747Snikos.nikoleris@arm.com 92911747Snikos.nikoleris@arm.com 93011747Snikos.nikoleris@arm.comTick 93111284Sandreas.hansson@arm.comCache::recvAtomic(PacketPtr pkt) 93211284Sandreas.hansson@arm.com{ 93311284Sandreas.hansson@arm.com // We are in atomic mode so we pay just for lookupLatency here. 93411051Sandreas.hansson@arm.com Cycles lat = lookupLatency; 93511051Sandreas.hansson@arm.com // @TODO: make this a parameter 93611051Sandreas.hansson@arm.com bool last_level_cache = false; 93711051Sandreas.hansson@arm.com 93811051Sandreas.hansson@arm.com // Forward the request if the system is in cache bypass mode. 93911051Sandreas.hansson@arm.com if (system->bypassCaches()) 94011051Sandreas.hansson@arm.com return ticksToCycles(memSidePort->sendAtomic(pkt)); 94111051Sandreas.hansson@arm.com 94211051Sandreas.hansson@arm.com promoteWholeLineWrites(pkt); 94311051Sandreas.hansson@arm.com 94411051Sandreas.hansson@arm.com if (pkt->memInhibitAsserted()) { 94511284Sandreas.hansson@arm.com // have to invalidate ourselves and any lower caches even if 94611051Sandreas.hansson@arm.com // upper cache will be responding 94711051Sandreas.hansson@arm.com if (pkt->isInvalidate()) { 94811051Sandreas.hansson@arm.com CacheBlk *blk = tags->findBlock(pkt->getAddr(), pkt->isSecure()); 94911051Sandreas.hansson@arm.com if (blk && blk->isValid()) { 95011284Sandreas.hansson@arm.com tags->invalidate(blk); 95111284Sandreas.hansson@arm.com blk->invalidate(); 95211284Sandreas.hansson@arm.com DPRINTF(Cache, "rcvd mem-inhibited %s on %#llx (%s):" 95311602Sandreas.hansson@arm.com " invalidating\n", 95411051Sandreas.hansson@arm.com pkt->cmdString(), pkt->getAddr(), 95511051Sandreas.hansson@arm.com pkt->isSecure() ? "s" : "ns"); 95611051Sandreas.hansson@arm.com } 95711284Sandreas.hansson@arm.com if (!last_level_cache) { 95811284Sandreas.hansson@arm.com DPRINTF(Cache, "forwarding mem-inhibited %s on %#llx (%s)\n", 95911744Snikos.nikoleris@arm.com pkt->cmdString(), pkt->getAddr(), 96011744Snikos.nikoleris@arm.com pkt->isSecure() ? "s" : "ns"); 96111051Sandreas.hansson@arm.com lat += ticksToCycles(memSidePort->sendAtomic(pkt)); 96211051Sandreas.hansson@arm.com } 96311051Sandreas.hansson@arm.com } else { 96411892Snikos.nikoleris@arm.com DPRINTF(Cache, "rcvd mem-inhibited %s on %#llx: not responding\n", 96511051Sandreas.hansson@arm.com pkt->cmdString(), pkt->getAddr()); 96611051Sandreas.hansson@arm.com } 96711744Snikos.nikoleris@arm.com 96811744Snikos.nikoleris@arm.com return lat * clockPeriod(); 96911051Sandreas.hansson@arm.com } 97011051Sandreas.hansson@arm.com 97111051Sandreas.hansson@arm.com // should assert here that there are no outstanding MSHRs or 97211051Sandreas.hansson@arm.com // writebacks... that would mean that someone used an atomic 97311051Sandreas.hansson@arm.com // access in timing mode 97411051Sandreas.hansson@arm.com 97511051Sandreas.hansson@arm.com CacheBlk *blk = NULL; 97611051Sandreas.hansson@arm.com PacketList writebacks; 97711051Sandreas.hansson@arm.com bool satisfied = access(pkt, blk, lat, writebacks); 97811051Sandreas.hansson@arm.com 97911051Sandreas.hansson@arm.com // handle writebacks resulting from the access here to ensure they 98011051Sandreas.hansson@arm.com // logically proceed anything happening below 98111051Sandreas.hansson@arm.com while (!writebacks.empty()){ 98211051Sandreas.hansson@arm.com PacketPtr wbPkt = writebacks.front(); 98311051Sandreas.hansson@arm.com memSidePort->sendAtomic(wbPkt); 98411051Sandreas.hansson@arm.com writebacks.pop_front(); 98511333Sandreas.hansson@arm.com delete wbPkt; 98611333Sandreas.hansson@arm.com } 98711284Sandreas.hansson@arm.com 98811744Snikos.nikoleris@arm.com if (!satisfied) { 98911744Snikos.nikoleris@arm.com // MISS 99011333Sandreas.hansson@arm.com 99111333Sandreas.hansson@arm.com PacketPtr bus_pkt = getBusPacket(pkt, blk, pkt->needsExclusive()); 99211333Sandreas.hansson@arm.com 99311333Sandreas.hansson@arm.com bool is_forward = (bus_pkt == NULL); 99411334Sandreas.hansson@arm.com 99511334Sandreas.hansson@arm.com if (is_forward) { 99611051Sandreas.hansson@arm.com // just forwarding the same request to the next level 99711051Sandreas.hansson@arm.com // no local cache operation involved 99811051Sandreas.hansson@arm.com bus_pkt = pkt; 99911051Sandreas.hansson@arm.com } 100011051Sandreas.hansson@arm.com 100111051Sandreas.hansson@arm.com DPRINTF(Cache, "Sending an atomic %s for %#llx (%s)\n", 100211051Sandreas.hansson@arm.com bus_pkt->cmdString(), bus_pkt->getAddr(), 100311051Sandreas.hansson@arm.com bus_pkt->isSecure() ? "s" : "ns"); 100411484Snikos.nikoleris@arm.com 100511051Sandreas.hansson@arm.com#if TRACING_ON 100611051Sandreas.hansson@arm.com CacheBlk::State old_state = blk ? blk->status : 0; 100711051Sandreas.hansson@arm.com#endif 100811051Sandreas.hansson@arm.com 100911051Sandreas.hansson@arm.com lat += ticksToCycles(memSidePort->sendAtomic(bus_pkt)); 101011130Sali.jafri@arm.com 101111051Sandreas.hansson@arm.com // We are now dealing with the response handling 101211051Sandreas.hansson@arm.com DPRINTF(Cache, "Receive response: %s for addr %#llx (%s) in state %i\n", 101311051Sandreas.hansson@arm.com bus_pkt->cmdString(), bus_pkt->getAddr(), 101411051Sandreas.hansson@arm.com bus_pkt->isSecure() ? "s" : "ns", 101511452Sandreas.hansson@arm.com old_state); 101611452Sandreas.hansson@arm.com 101711452Sandreas.hansson@arm.com // If packet was a forward, the response (if any) is already 101811452Sandreas.hansson@arm.com // in place in the bus_pkt == pkt structure, so we don't need 101911452Sandreas.hansson@arm.com // to do anything. Otherwise, use the separate bus_pkt to 102011452Sandreas.hansson@arm.com // generate response to pkt and then delete it. 102111452Sandreas.hansson@arm.com if (!is_forward) { 102211452Sandreas.hansson@arm.com if (pkt->needsResponse()) { 102311452Sandreas.hansson@arm.com assert(bus_pkt->isResponse()); 102411452Sandreas.hansson@arm.com if (bus_pkt->isError()) { 102511051Sandreas.hansson@arm.com pkt->makeAtomicResponse(); 102611484Snikos.nikoleris@arm.com pkt->copyError(bus_pkt); 102711051Sandreas.hansson@arm.com } else if (pkt->cmd == MemCmd::InvalidateReq) { 102811051Sandreas.hansson@arm.com if (blk) { 102911051Sandreas.hansson@arm.com // invalidate response to a cache that received 103011051Sandreas.hansson@arm.com // an invalidate request 103111051Sandreas.hansson@arm.com satisfyCpuSideRequest(pkt, blk); 103211051Sandreas.hansson@arm.com } 103311051Sandreas.hansson@arm.com } else if (pkt->cmd == MemCmd::WriteLineReq) { 103411744Snikos.nikoleris@arm.com // note the use of pkt, not bus_pkt here. 103511744Snikos.nikoleris@arm.com 103611051Sandreas.hansson@arm.com // write-line request to the cache that promoted 103711051Sandreas.hansson@arm.com // the write to a whole line 103811051Sandreas.hansson@arm.com blk = handleFill(pkt, blk, writebacks); 103911051Sandreas.hansson@arm.com satisfyCpuSideRequest(pkt, blk); 104011051Sandreas.hansson@arm.com } else if (bus_pkt->isRead() || 104111051Sandreas.hansson@arm.com bus_pkt->cmd == MemCmd::UpgradeResp) { 104211051Sandreas.hansson@arm.com // we're updating cache state to allow us to 104311452Sandreas.hansson@arm.com // satisfy the upstream request from the cache 104411452Sandreas.hansson@arm.com blk = handleFill(bus_pkt, blk, writebacks); 104511051Sandreas.hansson@arm.com satisfyCpuSideRequest(pkt, blk); 104611744Snikos.nikoleris@arm.com } else { 104711744Snikos.nikoleris@arm.com // we're satisfying the upstream request without 104811051Sandreas.hansson@arm.com // modifying cache state, e.g., a write-through 104911051Sandreas.hansson@arm.com pkt->makeAtomicResponse(); 105011051Sandreas.hansson@arm.com } 105111051Sandreas.hansson@arm.com } 105211051Sandreas.hansson@arm.com delete bus_pkt; 105311051Sandreas.hansson@arm.com } 105411051Sandreas.hansson@arm.com } 105511051Sandreas.hansson@arm.com 105611051Sandreas.hansson@arm.com // Note that we don't invoke the prefetcher at all in atomic mode. 105711051Sandreas.hansson@arm.com // It's not clear how to do it properly, particularly for 105811051Sandreas.hansson@arm.com // prefetchers that aggressively generate prefetch candidates and 105911051Sandreas.hansson@arm.com // rely on bandwidth contention to throttle them; these will tend 106011051Sandreas.hansson@arm.com // to pollute the cache in atomic mode since there is no bandwidth 106111051Sandreas.hansson@arm.com // contention. If we ever do want to enable prefetching in atomic 106211051Sandreas.hansson@arm.com // mode, though, this is the place to do it... see timingAccess() 106311051Sandreas.hansson@arm.com // for an example (though we'd want to issue the prefetch(es) 106411197Sandreas.hansson@arm.com // immediately rather than calling requestMemSideBus() as we do 106511197Sandreas.hansson@arm.com // there). 106611452Sandreas.hansson@arm.com 106711452Sandreas.hansson@arm.com // Handle writebacks (from the response handling) if needed 106811601Sandreas.hansson@arm.com while (!writebacks.empty()){ 106911051Sandreas.hansson@arm.com PacketPtr wbPkt = writebacks.front(); 107011051Sandreas.hansson@arm.com memSidePort->sendAtomic(wbPkt); 107111051Sandreas.hansson@arm.com writebacks.pop_front(); 107211051Sandreas.hansson@arm.com delete wbPkt; 107311197Sandreas.hansson@arm.com } 107411197Sandreas.hansson@arm.com 107511601Sandreas.hansson@arm.com if (pkt->needsResponse()) { 107611601Sandreas.hansson@arm.com pkt->makeAtomicResponse(); 107711051Sandreas.hansson@arm.com } 107811051Sandreas.hansson@arm.com 107911051Sandreas.hansson@arm.com return lat * clockPeriod(); 108011051Sandreas.hansson@arm.com} 108111051Sandreas.hansson@arm.com 108211051Sandreas.hansson@arm.com 108311051Sandreas.hansson@arm.comvoid 108411051Sandreas.hansson@arm.comCache::functionalAccess(PacketPtr pkt, bool fromCpuSide) 108511452Sandreas.hansson@arm.com{ 108611452Sandreas.hansson@arm.com if (system->bypassCaches()) { 108711452Sandreas.hansson@arm.com // Packets from the memory side are snoop request and 108811452Sandreas.hansson@arm.com // shouldn't happen in bypass mode. 108911051Sandreas.hansson@arm.com assert(fromCpuSide); 109011051Sandreas.hansson@arm.com 109111051Sandreas.hansson@arm.com // The cache should be flushed if we are in cache bypass mode, 109211051Sandreas.hansson@arm.com // so we don't need to check if we need to update anything. 109311051Sandreas.hansson@arm.com memSidePort->sendFunctional(pkt); 109411051Sandreas.hansson@arm.com return; 109511051Sandreas.hansson@arm.com } 109611051Sandreas.hansson@arm.com 109711051Sandreas.hansson@arm.com Addr blk_addr = blockAlign(pkt->getAddr()); 109811051Sandreas.hansson@arm.com bool is_secure = pkt->isSecure(); 109911051Sandreas.hansson@arm.com CacheBlk *blk = tags->findBlock(pkt->getAddr(), is_secure); 110011051Sandreas.hansson@arm.com MSHR *mshr = mshrQueue.findMatch(blk_addr, is_secure); 110111051Sandreas.hansson@arm.com 110211197Sandreas.hansson@arm.com pkt->pushLabel(name()); 110311130Sali.jafri@arm.com 110411051Sandreas.hansson@arm.com CacheBlkPrintWrapper cbpw(blk); 110511197Sandreas.hansson@arm.com 110611197Sandreas.hansson@arm.com // Note that just because an L2/L3 has valid data doesn't mean an 110711197Sandreas.hansson@arm.com // L1 doesn't have a more up-to-date modified copy that still 110811197Sandreas.hansson@arm.com // needs to be found. As a result we always update the request if 110911197Sandreas.hansson@arm.com // we have it, but only declare it satisfied if we are the owner. 111011197Sandreas.hansson@arm.com 111111197Sandreas.hansson@arm.com // see if we have data at all (owned or otherwise) 111211197Sandreas.hansson@arm.com bool have_data = blk && blk->isValid() 111311197Sandreas.hansson@arm.com && pkt->checkFunctional(&cbpw, blk_addr, is_secure, blkSize, 111411197Sandreas.hansson@arm.com blk->data); 111511197Sandreas.hansson@arm.com 111611197Sandreas.hansson@arm.com // data we have is dirty if marked as such or if valid & ownership 111711197Sandreas.hansson@arm.com // pending due to outstanding UpgradeReq 111811197Sandreas.hansson@arm.com bool have_dirty = 111911197Sandreas.hansson@arm.com have_data && (blk->isDirty() || 112011197Sandreas.hansson@arm.com (mshr && mshr->inService && mshr->isPendingDirty())); 112111197Sandreas.hansson@arm.com 112211197Sandreas.hansson@arm.com bool done = have_dirty 112311197Sandreas.hansson@arm.com || cpuSidePort->checkFunctional(pkt) 112411197Sandreas.hansson@arm.com || mshrQueue.checkFunctional(pkt, blk_addr) 112511199Sandreas.hansson@arm.com || writeBuffer.checkFunctional(pkt, blk_addr) 112611199Sandreas.hansson@arm.com || memSidePort->checkFunctional(pkt); 112711867Snikos.nikoleris@arm.com 112811197Sandreas.hansson@arm.com DPRINTF(Cache, "functional %s %#llx (%s) %s%s%s\n", 112911197Sandreas.hansson@arm.com pkt->cmdString(), pkt->getAddr(), is_secure ? "s" : "ns", 113011051Sandreas.hansson@arm.com (blk && blk->isValid()) ? "valid " : "", 113111051Sandreas.hansson@arm.com have_data ? "data " : "", done ? "done " : ""); 113211051Sandreas.hansson@arm.com 113311051Sandreas.hansson@arm.com // We're leaving the cache, so pop cache->name() label 113411051Sandreas.hansson@arm.com pkt->popLabel(); 113511051Sandreas.hansson@arm.com 113611051Sandreas.hansson@arm.com if (done) { 113711051Sandreas.hansson@arm.com pkt->makeResponse(); 113811051Sandreas.hansson@arm.com } else { 113911051Sandreas.hansson@arm.com // if it came as a request from the CPU side then make sure it 114011051Sandreas.hansson@arm.com // continues towards the memory side 114111051Sandreas.hansson@arm.com if (fromCpuSide) { 114211051Sandreas.hansson@arm.com memSidePort->sendFunctional(pkt); 114311051Sandreas.hansson@arm.com } else if (forwardSnoops && cpuSidePort->isSnooping()) { 114411051Sandreas.hansson@arm.com // if it came from the memory side, it must be a snoop request 114511051Sandreas.hansson@arm.com // and we should only forward it if we are forwarding snoops 114611051Sandreas.hansson@arm.com cpuSidePort->sendFunctionalSnoop(pkt); 114711051Sandreas.hansson@arm.com } 114811051Sandreas.hansson@arm.com } 114911051Sandreas.hansson@arm.com} 115011051Sandreas.hansson@arm.com 115111051Sandreas.hansson@arm.com 115211892Snikos.nikoleris@arm.com///////////////////////////////////////////////////// 115311051Sandreas.hansson@arm.com// 115411051Sandreas.hansson@arm.com// Response handling: responses from the memory side 115511051Sandreas.hansson@arm.com// 115611051Sandreas.hansson@arm.com///////////////////////////////////////////////////// 115711051Sandreas.hansson@arm.com 115811051Sandreas.hansson@arm.com 115911051Sandreas.hansson@arm.comvoid 116011051Sandreas.hansson@arm.comCache::recvTimingResp(PacketPtr pkt) 116111051Sandreas.hansson@arm.com{ 116211051Sandreas.hansson@arm.com assert(pkt->isResponse()); 116311051Sandreas.hansson@arm.com 116411051Sandreas.hansson@arm.com // all header delay should be paid for by the crossbar, unless 116511051Sandreas.hansson@arm.com // this is a prefetch response from above 116611051Sandreas.hansson@arm.com panic_if(pkt->headerDelay != 0 && pkt->cmd != MemCmd::HardPFResp, 116711051Sandreas.hansson@arm.com "%s saw a non-zero packet delay\n", name()); 116811051Sandreas.hansson@arm.com 116911051Sandreas.hansson@arm.com MSHR *mshr = dynamic_cast<MSHR*>(pkt->senderState); 117011051Sandreas.hansson@arm.com bool is_error = pkt->isError(); 117111284Sandreas.hansson@arm.com 117211284Sandreas.hansson@arm.com assert(mshr); 117311051Sandreas.hansson@arm.com 117411051Sandreas.hansson@arm.com if (is_error) { 117511284Sandreas.hansson@arm.com DPRINTF(Cache, "Cache received packet with error for addr %#llx (%s), " 117611051Sandreas.hansson@arm.com "cmd: %s\n", pkt->getAddr(), pkt->isSecure() ? "s" : "ns", 117711051Sandreas.hansson@arm.com pkt->cmdString()); 117811051Sandreas.hansson@arm.com } 117911051Sandreas.hansson@arm.com 118011051Sandreas.hansson@arm.com DPRINTF(Cache, "Handling response %s for addr %#llx size %d (%s)\n", 118111051Sandreas.hansson@arm.com pkt->cmdString(), pkt->getAddr(), pkt->getSize(), 118211051Sandreas.hansson@arm.com pkt->isSecure() ? "s" : "ns"); 118311744Snikos.nikoleris@arm.com 118411051Sandreas.hansson@arm.com MSHRQueue *mq = mshr->queue; 118511051Sandreas.hansson@arm.com bool wasFull = mq->isFull(); 118611051Sandreas.hansson@arm.com 118711051Sandreas.hansson@arm.com if (mshr == noTargetMSHR) { 118811051Sandreas.hansson@arm.com // we always clear at least one target 118911051Sandreas.hansson@arm.com clearBlocked(Blocked_NoTargets); 119011051Sandreas.hansson@arm.com noTargetMSHR = NULL; 119111051Sandreas.hansson@arm.com } 119211051Sandreas.hansson@arm.com 119311051Sandreas.hansson@arm.com // Initial target is used just for stats 119411051Sandreas.hansson@arm.com MSHR::Target *initial_tgt = mshr->getTarget(); 119511051Sandreas.hansson@arm.com CacheBlk *blk = tags->findBlock(pkt->getAddr(), pkt->isSecure()); 119611051Sandreas.hansson@arm.com int stats_cmd_idx = initial_tgt->pkt->cmdToIndex(); 119711485Snikos.nikoleris@arm.com Tick miss_latency = curTick() - initial_tgt->recvTime; 119811051Sandreas.hansson@arm.com PacketList writebacks; 119911051Sandreas.hansson@arm.com // We need forward_time here because we have a call of 120011051Sandreas.hansson@arm.com // allocateWriteBuffer() that need this parameter to specify the 120111051Sandreas.hansson@arm.com // time to request the bus. In this case we use forward latency 120211051Sandreas.hansson@arm.com // because there is a writeback. We pay also here for headerDelay 120311051Sandreas.hansson@arm.com // that is charged of bus latencies if the packet comes from the 120411051Sandreas.hansson@arm.com // bus. 120511051Sandreas.hansson@arm.com Tick forward_time = clockEdge(forwardLatency) + pkt->headerDelay; 120611051Sandreas.hansson@arm.com 120711051Sandreas.hansson@arm.com if (pkt->req->isUncacheable()) { 120811051Sandreas.hansson@arm.com assert(pkt->req->masterId() < system->maxMasters()); 120911051Sandreas.hansson@arm.com mshr_uncacheable_lat[stats_cmd_idx][pkt->req->masterId()] += 121011051Sandreas.hansson@arm.com miss_latency; 121111051Sandreas.hansson@arm.com } else { 121211051Sandreas.hansson@arm.com assert(pkt->req->masterId() < system->maxMasters()); 121311051Sandreas.hansson@arm.com mshr_miss_latency[stats_cmd_idx][pkt->req->masterId()] += 121411375Sandreas.hansson@arm.com miss_latency; 121511375Sandreas.hansson@arm.com } 121611375Sandreas.hansson@arm.com 121711375Sandreas.hansson@arm.com bool is_fill = !mshr->isForward && 121811375Sandreas.hansson@arm.com (pkt->isRead() || pkt->cmd == MemCmd::UpgradeResp); 121911453Sandreas.hansson@arm.com 122011453Sandreas.hansson@arm.com if (is_fill && !is_error) { 122111375Sandreas.hansson@arm.com DPRINTF(Cache, "Block for addr %#llx being updated in Cache\n", 122211453Sandreas.hansson@arm.com pkt->getAddr()); 122311375Sandreas.hansson@arm.com 122411375Sandreas.hansson@arm.com // give mshr a chance to do some dirty work 122511375Sandreas.hansson@arm.com mshr->handleFill(pkt, blk); 122611051Sandreas.hansson@arm.com 122711051Sandreas.hansson@arm.com blk = handleFill(pkt, blk, writebacks); 122811051Sandreas.hansson@arm.com assert(blk != NULL); 122911051Sandreas.hansson@arm.com } 123011051Sandreas.hansson@arm.com 123111051Sandreas.hansson@arm.com // allow invalidation responses originating from write-line 123211051Sandreas.hansson@arm.com // requests to be discarded 123311051Sandreas.hansson@arm.com bool discard_invalidate = false; 123411051Sandreas.hansson@arm.com 123511051Sandreas.hansson@arm.com // First offset for critical word first calculations 123611051Sandreas.hansson@arm.com int initial_offset = initial_tgt->pkt->getOffset(blkSize); 123711051Sandreas.hansson@arm.com 123811744Snikos.nikoleris@arm.com while (mshr->hasTargets()) { 123911744Snikos.nikoleris@arm.com MSHR::Target *target = mshr->getTarget(); 124011051Sandreas.hansson@arm.com Packet *tgt_pkt = target->pkt; 124111051Sandreas.hansson@arm.com 124211744Snikos.nikoleris@arm.com switch (target->source) { 124311744Snikos.nikoleris@arm.com case MSHR::Target::FromCPU: 124411051Sandreas.hansson@arm.com Tick completion_time; 124511375Sandreas.hansson@arm.com // Here we charge on completion_time the delay of the xbar if the 124611375Sandreas.hansson@arm.com // packet comes from it, charged on headerDelay. 124711375Sandreas.hansson@arm.com completion_time = pkt->headerDelay; 124811375Sandreas.hansson@arm.com 124911375Sandreas.hansson@arm.com // Software prefetch handling for cache closest to core 125011375Sandreas.hansson@arm.com if (tgt_pkt->cmd.isSWPrefetch()) { 125111375Sandreas.hansson@arm.com // a software prefetch would have already been ack'd immediately 125211375Sandreas.hansson@arm.com // with dummy data so the core would be able to retire it. 125311375Sandreas.hansson@arm.com // this request completes right here, so we deallocate it. 125411375Sandreas.hansson@arm.com delete tgt_pkt->req; 125511453Sandreas.hansson@arm.com delete tgt_pkt; 125611375Sandreas.hansson@arm.com break; // skip response 125711051Sandreas.hansson@arm.com } 125811051Sandreas.hansson@arm.com 125911051Sandreas.hansson@arm.com // unlike the other packet flows, where data is found in other 126011051Sandreas.hansson@arm.com // caches or memory and brought back, write-line requests always 126111484Snikos.nikoleris@arm.com // have the data right away, so the above check for "is fill?" 126211051Sandreas.hansson@arm.com // cannot actually be determined until examining the stored MSHR 126311051Sandreas.hansson@arm.com // state. We "catch up" with that logic here, which is duplicated 126411051Sandreas.hansson@arm.com // from above. 126511051Sandreas.hansson@arm.com if (tgt_pkt->cmd == MemCmd::WriteLineReq) { 126611051Sandreas.hansson@arm.com assert(!is_error); 126711051Sandreas.hansson@arm.com 126811051Sandreas.hansson@arm.com // NB: we use the original packet here and not the response! 126911051Sandreas.hansson@arm.com mshr->handleFill(tgt_pkt, blk); 127011051Sandreas.hansson@arm.com blk = handleFill(tgt_pkt, blk, writebacks); 127111051Sandreas.hansson@arm.com assert(blk != NULL); 127211051Sandreas.hansson@arm.com 127311051Sandreas.hansson@arm.com // treat as a fill, and discard the invalidation 127411051Sandreas.hansson@arm.com // response 127511051Sandreas.hansson@arm.com is_fill = true; 127611051Sandreas.hansson@arm.com discard_invalidate = true; 127711051Sandreas.hansson@arm.com } 127811051Sandreas.hansson@arm.com 127911375Sandreas.hansson@arm.com if (is_fill) { 128011375Sandreas.hansson@arm.com satisfyCpuSideRequest(tgt_pkt, blk, 128111375Sandreas.hansson@arm.com true, mshr->hasPostDowngrade()); 128211375Sandreas.hansson@arm.com 128311375Sandreas.hansson@arm.com // How many bytes past the first request is this one 128411375Sandreas.hansson@arm.com int transfer_offset = 128511284Sandreas.hansson@arm.com tgt_pkt->getOffset(blkSize) - initial_offset; 128611284Sandreas.hansson@arm.com if (transfer_offset < 0) { 128711284Sandreas.hansson@arm.com transfer_offset += blkSize; 128811284Sandreas.hansson@arm.com } 128911177Sandreas.hansson@arm.com 129011177Sandreas.hansson@arm.com // If not critical word (offset) return payloadDelay. 129111051Sandreas.hansson@arm.com // responseLatency is the latency of the return path 129211051Sandreas.hansson@arm.com // from lower level caches/memory to an upper level cache or 129311051Sandreas.hansson@arm.com // the core. 129411177Sandreas.hansson@arm.com completion_time += clockEdge(responseLatency) + 129511177Sandreas.hansson@arm.com (transfer_offset ? pkt->payloadDelay : 0); 129611051Sandreas.hansson@arm.com 129711051Sandreas.hansson@arm.com assert(!tgt_pkt->req->isUncacheable()); 129811051Sandreas.hansson@arm.com 129911051Sandreas.hansson@arm.com assert(tgt_pkt->req->masterId() < system->maxMasters()); 130011741Snikos.nikoleris@arm.com missLatency[tgt_pkt->cmdToIndex()][tgt_pkt->req->masterId()] += 130111484Snikos.nikoleris@arm.com completion_time - target->recvTime; 130211051Sandreas.hansson@arm.com } else if (pkt->cmd == MemCmd::UpgradeFailResp) { 130311051Sandreas.hansson@arm.com // failed StoreCond upgrade 130411051Sandreas.hansson@arm.com assert(tgt_pkt->cmd == MemCmd::StoreCondReq || 130511051Sandreas.hansson@arm.com tgt_pkt->cmd == MemCmd::StoreCondFailReq || 130611136Sandreas.hansson@arm.com tgt_pkt->cmd == MemCmd::SCUpgradeFailReq); 130711051Sandreas.hansson@arm.com // responseLatency is the latency of the return path 130811051Sandreas.hansson@arm.com // from lower level caches/memory to an upper level cache or 130911051Sandreas.hansson@arm.com // the core. 131011051Sandreas.hansson@arm.com completion_time += clockEdge(responseLatency) + 131111601Sandreas.hansson@arm.com pkt->payloadDelay; 131211742Snikos.nikoleris@arm.com tgt_pkt->req->setExtraData(0); 131311742Snikos.nikoleris@arm.com } else { 131411742Snikos.nikoleris@arm.com // not a cache fill, just forwarding response 131511742Snikos.nikoleris@arm.com // responseLatency is the latency of the return path 131611051Sandreas.hansson@arm.com // from lower level cahces/memory to the core. 131711051Sandreas.hansson@arm.com completion_time += clockEdge(responseLatency) + 131811051Sandreas.hansson@arm.com pkt->payloadDelay; 131911051Sandreas.hansson@arm.com if (pkt->isRead() && !is_error) { 132011051Sandreas.hansson@arm.com // sanity check 132111051Sandreas.hansson@arm.com assert(pkt->getAddr() == tgt_pkt->getAddr()); 132211051Sandreas.hansson@arm.com assert(pkt->getSize() >= tgt_pkt->getSize()); 132311051Sandreas.hansson@arm.com 132411483Snikos.nikoleris@arm.com tgt_pkt->setData(pkt->getConstPtr<uint8_t>()); 132511483Snikos.nikoleris@arm.com } 132611483Snikos.nikoleris@arm.com } 132711483Snikos.nikoleris@arm.com tgt_pkt->makeTimingResponse(); 132811051Sandreas.hansson@arm.com // if this packet is an error copy that to the new packet 132911051Sandreas.hansson@arm.com if (is_error) 133011051Sandreas.hansson@arm.com tgt_pkt->copyError(pkt); 133111051Sandreas.hansson@arm.com if (tgt_pkt->cmd == MemCmd::ReadResp && 133211051Sandreas.hansson@arm.com (pkt->isInvalidate() || mshr->hasPostInvalidate())) { 133311601Sandreas.hansson@arm.com // If intermediate cache got ReadRespWithInvalidate, 133411601Sandreas.hansson@arm.com // propagate that. Response should not have 133511601Sandreas.hansson@arm.com // isInvalidate() set otherwise. 133611601Sandreas.hansson@arm.com tgt_pkt->cmd = MemCmd::ReadRespWithInvalidate; 133711051Sandreas.hansson@arm.com DPRINTF(Cache, "%s updated cmd to %s for addr %#llx\n", 133811051Sandreas.hansson@arm.com __func__, tgt_pkt->cmdString(), tgt_pkt->getAddr()); 133911051Sandreas.hansson@arm.com } 134011051Sandreas.hansson@arm.com // Reset the bus additional time as it is now accounted for 134111051Sandreas.hansson@arm.com tgt_pkt->headerDelay = tgt_pkt->payloadDelay = 0; 134211051Sandreas.hansson@arm.com cpuSidePort->schedTimingResp(tgt_pkt, completion_time); 134311051Sandreas.hansson@arm.com break; 134411051Sandreas.hansson@arm.com 134511284Sandreas.hansson@arm.com case MSHR::Target::FromPrefetcher: 134611284Sandreas.hansson@arm.com assert(tgt_pkt->cmd == MemCmd::HardPFReq); 134711284Sandreas.hansson@arm.com if (blk) 134811051Sandreas.hansson@arm.com blk->status |= BlkHWPrefetched; 134911741Snikos.nikoleris@arm.com delete tgt_pkt->req; 135011742Snikos.nikoleris@arm.com delete tgt_pkt; 135111484Snikos.nikoleris@arm.com break; 135211051Sandreas.hansson@arm.com 135311051Sandreas.hansson@arm.com case MSHR::Target::FromSnoop: 135411051Sandreas.hansson@arm.com // I don't believe that a snoop can be in an error state 135511051Sandreas.hansson@arm.com assert(!is_error); 135611136Sandreas.hansson@arm.com // response to snoop request 135711051Sandreas.hansson@arm.com DPRINTF(Cache, "processing deferred snoop...\n"); 135811051Sandreas.hansson@arm.com assert(!(pkt->isInvalidate() && !mshr->hasPostInvalidate())); 135911051Sandreas.hansson@arm.com handleSnoop(tgt_pkt, blk, true, true, mshr->hasPostInvalidate()); 136011601Sandreas.hansson@arm.com break; 136111051Sandreas.hansson@arm.com 136211051Sandreas.hansson@arm.com default: 136311051Sandreas.hansson@arm.com panic("Illegal target->source enum %d\n", target->source); 136411051Sandreas.hansson@arm.com } 136511051Sandreas.hansson@arm.com 136611051Sandreas.hansson@arm.com mshr->popTarget(); 136711051Sandreas.hansson@arm.com } 136811051Sandreas.hansson@arm.com 136911051Sandreas.hansson@arm.com if (blk && blk->isValid()) { 137011051Sandreas.hansson@arm.com // an invalidate response stemming from a write line request 137111051Sandreas.hansson@arm.com // should not invalidate the block, so check if the 137211051Sandreas.hansson@arm.com // invalidation should be discarded 137311051Sandreas.hansson@arm.com if ((pkt->isInvalidate() || mshr->hasPostInvalidate()) && 137411051Sandreas.hansson@arm.com !discard_invalidate) { 137511051Sandreas.hansson@arm.com assert(blk != tempBlock); 137611051Sandreas.hansson@arm.com tags->invalidate(blk); 137711051Sandreas.hansson@arm.com blk->invalidate(); 137811051Sandreas.hansson@arm.com } else if (mshr->hasPostDowngrade()) { 137911051Sandreas.hansson@arm.com blk->status &= ~BlkWritable; 138011742Snikos.nikoleris@arm.com } 138111051Sandreas.hansson@arm.com } 138211051Sandreas.hansson@arm.com 138311051Sandreas.hansson@arm.com if (mshr->promoteDeferredTargets()) { 138411051Sandreas.hansson@arm.com // avoid later read getting stale data while write miss is 138511051Sandreas.hansson@arm.com // outstanding.. see comment in timingAccess() 138611051Sandreas.hansson@arm.com if (blk) { 138711051Sandreas.hansson@arm.com blk->status &= ~BlkReadable; 138811051Sandreas.hansson@arm.com } 138911051Sandreas.hansson@arm.com mq = mshr->queue; 139011051Sandreas.hansson@arm.com mq->markPending(mshr); 139111051Sandreas.hansson@arm.com schedMemSideSendEvent(clockEdge() + pkt->payloadDelay); 139211051Sandreas.hansson@arm.com } else { 139311750Snikos.nikoleris@arm.com mq->deallocate(mshr); 139411750Snikos.nikoleris@arm.com if (wasFull && !mq->isFull()) { 139511750Snikos.nikoleris@arm.com clearBlocked((BlockedCause)mq->index); 139611750Snikos.nikoleris@arm.com } 139711750Snikos.nikoleris@arm.com 139811750Snikos.nikoleris@arm.com // Request the bus for a prefetch if this deallocation freed enough 139911750Snikos.nikoleris@arm.com // MSHRs for a prefetch to take place 140011750Snikos.nikoleris@arm.com if (prefetcher && mq == &mshrQueue && mshrQueue.canPrefetch()) { 140111750Snikos.nikoleris@arm.com Tick next_pf_time = std::max(prefetcher->nextPrefetchReadyTime(), 140211750Snikos.nikoleris@arm.com clockEdge()); 140311750Snikos.nikoleris@arm.com if (next_pf_time != MaxTick) 140411051Sandreas.hansson@arm.com schedMemSideSendEvent(next_pf_time); 140511051Sandreas.hansson@arm.com } 140611051Sandreas.hansson@arm.com } 140711051Sandreas.hansson@arm.com // reset the xbar additional timinig as it is now accounted for 140811051Sandreas.hansson@arm.com pkt->headerDelay = pkt->payloadDelay = 0; 140911051Sandreas.hansson@arm.com 141011051Sandreas.hansson@arm.com // copy writebacks to write buffer 141111051Sandreas.hansson@arm.com doWritebacks(writebacks, forward_time); 141211051Sandreas.hansson@arm.com 141311051Sandreas.hansson@arm.com // if we used temp block, check to see if its valid and then clear it out 141411051Sandreas.hansson@arm.com if (blk == tempBlock && tempBlock->isValid()) { 141511051Sandreas.hansson@arm.com // We use forwardLatency here because we are copying 141611051Sandreas.hansson@arm.com // Writebacks/CleanEvicts to write buffer. It specifies the latency to 141711051Sandreas.hansson@arm.com // allocate an internal buffer and to schedule an event to the 141811051Sandreas.hansson@arm.com // queued port. 141911051Sandreas.hansson@arm.com if (blk->isDirty()) { 142011051Sandreas.hansson@arm.com PacketPtr wbPkt = writebackBlk(blk); 142111051Sandreas.hansson@arm.com allocateWriteBuffer(wbPkt, forward_time); 142211136Sandreas.hansson@arm.com // Set BLOCK_CACHED flag if cached above. 142311051Sandreas.hansson@arm.com if (isCachedAbove(wbPkt)) 142411051Sandreas.hansson@arm.com wbPkt->setBlockCached(); 142511051Sandreas.hansson@arm.com } else { 142611051Sandreas.hansson@arm.com PacketPtr wcPkt = cleanEvictBlk(blk); 142711744Snikos.nikoleris@arm.com // Check to see if block is cached above. If not allocate 142811744Snikos.nikoleris@arm.com // write buffer 142911051Sandreas.hansson@arm.com if (isCachedAbove(wcPkt)) 143011051Sandreas.hansson@arm.com delete wcPkt; 143111051Sandreas.hansson@arm.com else 143211194Sali.jafri@arm.com allocateWriteBuffer(wcPkt, forward_time); 143311051Sandreas.hansson@arm.com } 143411051Sandreas.hansson@arm.com blk->invalidate(); 143511051Sandreas.hansson@arm.com } 143611051Sandreas.hansson@arm.com 143711051Sandreas.hansson@arm.com DPRINTF(Cache, "Leaving %s with %s for addr %#llx\n", __func__, 143811051Sandreas.hansson@arm.com pkt->cmdString(), pkt->getAddr()); 143911051Sandreas.hansson@arm.com delete pkt; 144011051Sandreas.hansson@arm.com} 144111051Sandreas.hansson@arm.com 144211051Sandreas.hansson@arm.comPacketPtr 144311051Sandreas.hansson@arm.comCache::writebackBlk(CacheBlk *blk) 144411051Sandreas.hansson@arm.com{ 144511051Sandreas.hansson@arm.com chatty_assert(!isReadOnly, "Writeback from read-only cache"); 144611051Sandreas.hansson@arm.com assert(blk && blk->isValid() && blk->isDirty()); 144711051Sandreas.hansson@arm.com 144811749Snikos.nikoleris@arm.com writebacks[Request::wbMasterId]++; 144911749Snikos.nikoleris@arm.com 145011749Snikos.nikoleris@arm.com Request *writebackReq = 145111749Snikos.nikoleris@arm.com new Request(tags->regenerateBlkAddr(blk->tag, blk->set), blkSize, 0, 145211749Snikos.nikoleris@arm.com Request::wbMasterId); 145311749Snikos.nikoleris@arm.com if (blk->isSecure()) 145411749Snikos.nikoleris@arm.com writebackReq->setFlags(Request::SECURE); 145511749Snikos.nikoleris@arm.com 145611749Snikos.nikoleris@arm.com writebackReq->taskId(blk->task_id); 145711749Snikos.nikoleris@arm.com blk->task_id= ContextSwitchTaskId::Unknown; 145811749Snikos.nikoleris@arm.com blk->tickInserted = curTick(); 145911749Snikos.nikoleris@arm.com 146011051Sandreas.hansson@arm.com PacketPtr writeback = new Packet(writebackReq, MemCmd::Writeback); 146111051Sandreas.hansson@arm.com if (blk->isWritable()) { 146211051Sandreas.hansson@arm.com // not asserting shared means we pass the block in modified 146311051Sandreas.hansson@arm.com // state, mark our own block non-writeable 146411742Snikos.nikoleris@arm.com blk->status &= ~BlkWritable; 146511051Sandreas.hansson@arm.com } else { 146611051Sandreas.hansson@arm.com // we are in the owned state, tell the receiver 146711051Sandreas.hansson@arm.com writeback->assertShared(); 146811601Sandreas.hansson@arm.com } 146911601Sandreas.hansson@arm.com 147011051Sandreas.hansson@arm.com writeback->allocate(); 147111051Sandreas.hansson@arm.com std::memcpy(writeback->getPtr<uint8_t>(), blk->data, blkSize); 147211051Sandreas.hansson@arm.com 147311051Sandreas.hansson@arm.com blk->status &= ~BlkDirty; 147411136Sandreas.hansson@arm.com return writeback; 147511197Sandreas.hansson@arm.com} 147611051Sandreas.hansson@arm.com 147711051Sandreas.hansson@arm.comPacketPtr 147811051Sandreas.hansson@arm.comCache::cleanEvictBlk(CacheBlk *blk) 147911051Sandreas.hansson@arm.com{ 148011051Sandreas.hansson@arm.com assert(blk && blk->isValid() && !blk->isDirty()); 148111051Sandreas.hansson@arm.com // Creating a zero sized write, a message to the snoop filter 148211051Sandreas.hansson@arm.com Request *req = 148311051Sandreas.hansson@arm.com new Request(tags->regenerateBlkAddr(blk->tag, blk->set), blkSize, 0, 148411051Sandreas.hansson@arm.com Request::wbMasterId); 148511051Sandreas.hansson@arm.com if (blk->isSecure()) 148611051Sandreas.hansson@arm.com req->setFlags(Request::SECURE); 148711375Sandreas.hansson@arm.com 148811051Sandreas.hansson@arm.com req->taskId(blk->task_id); 148911051Sandreas.hansson@arm.com blk->task_id = ContextSwitchTaskId::Unknown; 149011375Sandreas.hansson@arm.com blk->tickInserted = curTick(); 149111375Sandreas.hansson@arm.com 149211375Sandreas.hansson@arm.com PacketPtr pkt = new Packet(req, MemCmd::CleanEvict); 149311051Sandreas.hansson@arm.com pkt->allocate(); 149411051Sandreas.hansson@arm.com DPRINTF(Cache, "%s%s %x Create CleanEvict\n", pkt->cmdString(), 149511051Sandreas.hansson@arm.com pkt->req->isInstFetch() ? " (ifetch)" : "", 149611051Sandreas.hansson@arm.com pkt->getAddr()); 149711375Sandreas.hansson@arm.com 149811051Sandreas.hansson@arm.com return pkt; 149911051Sandreas.hansson@arm.com} 150011051Sandreas.hansson@arm.com 150111051Sandreas.hansson@arm.comvoid 150211051Sandreas.hansson@arm.comCache::memWriteback() 150311051Sandreas.hansson@arm.com{ 150411051Sandreas.hansson@arm.com CacheBlkVisitorWrapper visitor(*this, &Cache::writebackVisitor); 150511051Sandreas.hansson@arm.com tags->forEachBlk(visitor); 150611051Sandreas.hansson@arm.com} 150711051Sandreas.hansson@arm.com 150811051Sandreas.hansson@arm.comvoid 150911051Sandreas.hansson@arm.comCache::memInvalidate() 151011051Sandreas.hansson@arm.com{ 151111051Sandreas.hansson@arm.com CacheBlkVisitorWrapper visitor(*this, &Cache::invalidateVisitor); 151211051Sandreas.hansson@arm.com tags->forEachBlk(visitor); 151311051Sandreas.hansson@arm.com} 151411051Sandreas.hansson@arm.com 151511051Sandreas.hansson@arm.combool 151611199Sandreas.hansson@arm.comCache::isDirty() const 151711051Sandreas.hansson@arm.com{ 151811051Sandreas.hansson@arm.com CacheBlkIsDirtyVisitor visitor; 151911051Sandreas.hansson@arm.com tags->forEachBlk(visitor); 152011051Sandreas.hansson@arm.com 152111051Sandreas.hansson@arm.com return visitor.isDirty(); 152211051Sandreas.hansson@arm.com} 152311051Sandreas.hansson@arm.com 152411051Sandreas.hansson@arm.combool 152511051Sandreas.hansson@arm.comCache::writebackVisitor(CacheBlk &blk) 152611051Sandreas.hansson@arm.com{ 152711051Sandreas.hansson@arm.com if (blk.isDirty()) { 152811051Sandreas.hansson@arm.com assert(blk.isValid()); 152911051Sandreas.hansson@arm.com 153011051Sandreas.hansson@arm.com Request request(tags->regenerateBlkAddr(blk.tag, blk.set), 153111867Snikos.nikoleris@arm.com blkSize, 0, Request::funcMasterId); 153211051Sandreas.hansson@arm.com request.taskId(blk.task_id); 153311051Sandreas.hansson@arm.com 153411744Snikos.nikoleris@arm.com Packet packet(&request, MemCmd::WriteReq); 153511051Sandreas.hansson@arm.com packet.dataStatic(blk.data); 153611051Sandreas.hansson@arm.com 153711051Sandreas.hansson@arm.com memSidePort->sendFunctional(&packet); 153811051Sandreas.hansson@arm.com 153911051Sandreas.hansson@arm.com blk.status &= ~BlkDirty; 154011051Sandreas.hansson@arm.com } 154111199Sandreas.hansson@arm.com 154211199Sandreas.hansson@arm.com return true; 154311199Sandreas.hansson@arm.com} 154411051Sandreas.hansson@arm.com 154511051Sandreas.hansson@arm.combool 154611051Sandreas.hansson@arm.comCache::invalidateVisitor(CacheBlk &blk) 154711199Sandreas.hansson@arm.com{ 154811199Sandreas.hansson@arm.com 154911051Sandreas.hansson@arm.com if (blk.isDirty()) 155011199Sandreas.hansson@arm.com warn_once("Invalidating dirty cache lines. Expect things to break.\n"); 155111051Sandreas.hansson@arm.com 155211199Sandreas.hansson@arm.com if (blk.isValid()) { 155311051Sandreas.hansson@arm.com assert(!blk.isDirty()); 155411051Sandreas.hansson@arm.com tags->invalidate(&blk); 155511051Sandreas.hansson@arm.com blk.invalidate(); 155611199Sandreas.hansson@arm.com } 155711199Sandreas.hansson@arm.com 155811199Sandreas.hansson@arm.com return true; 155911199Sandreas.hansson@arm.com} 156011744Snikos.nikoleris@arm.com 156111744Snikos.nikoleris@arm.comCacheBlk* 156211199Sandreas.hansson@arm.comCache::allocateBlock(Addr addr, bool is_secure, PacketList &writebacks) 156311051Sandreas.hansson@arm.com{ 156411051Sandreas.hansson@arm.com CacheBlk *blk = tags->findVictim(addr); 156511051Sandreas.hansson@arm.com 156611051Sandreas.hansson@arm.com // It is valid to return NULL if there is no victim 156711051Sandreas.hansson@arm.com if (!blk) 156811284Sandreas.hansson@arm.com return nullptr; 156911284Sandreas.hansson@arm.com 157011051Sandreas.hansson@arm.com if (blk->isValid()) { 157111051Sandreas.hansson@arm.com Addr repl_addr = tags->regenerateBlkAddr(blk->tag, blk->set); 157211199Sandreas.hansson@arm.com MSHR *repl_mshr = mshrQueue.findMatch(repl_addr, blk->isSecure()); 157311199Sandreas.hansson@arm.com if (repl_mshr) { 157411051Sandreas.hansson@arm.com // must be an outstanding upgrade request 157511199Sandreas.hansson@arm.com // on a block we're about to replace... 157611199Sandreas.hansson@arm.com assert(!blk->isWritable() || blk->isDirty()); 157711199Sandreas.hansson@arm.com assert(repl_mshr->needsExclusive()); 157811199Sandreas.hansson@arm.com // too hard to replace block with transient state 157911051Sandreas.hansson@arm.com // allocation failed, block not inserted 158011051Sandreas.hansson@arm.com return NULL; 158111051Sandreas.hansson@arm.com } else { 158211051Sandreas.hansson@arm.com DPRINTF(Cache, "replacement: replacing %#llx (%s) with %#llx (%s): %s\n", 158311051Sandreas.hansson@arm.com repl_addr, blk->isSecure() ? "s" : "ns", 158411199Sandreas.hansson@arm.com addr, is_secure ? "s" : "ns", 158511051Sandreas.hansson@arm.com blk->isDirty() ? "writeback" : "clean"); 158611051Sandreas.hansson@arm.com 158711051Sandreas.hansson@arm.com // Will send up Writeback/CleanEvict snoops via isCachedAbove 158811051Sandreas.hansson@arm.com // when pushing this writeback list into the write buffer. 158911051Sandreas.hansson@arm.com if (blk->isDirty()) { 159011051Sandreas.hansson@arm.com // Save writeback packet for handling by caller 159111051Sandreas.hansson@arm.com writebacks.push_back(writebackBlk(blk)); 159211051Sandreas.hansson@arm.com } else { 159311051Sandreas.hansson@arm.com writebacks.push_back(cleanEvictBlk(blk)); 159411051Sandreas.hansson@arm.com } 159511051Sandreas.hansson@arm.com } 159611051Sandreas.hansson@arm.com } 159711051Sandreas.hansson@arm.com 159811051Sandreas.hansson@arm.com return blk; 159911744Snikos.nikoleris@arm.com} 160011051Sandreas.hansson@arm.com 160111051Sandreas.hansson@arm.com 160211051Sandreas.hansson@arm.com// Note that the reason we return a list of writebacks rather than 160311051Sandreas.hansson@arm.com// inserting them directly in the write buffer is that this function 160411051Sandreas.hansson@arm.com// is called by both atomic and timing-mode accesses, and in atomic 160511051Sandreas.hansson@arm.com// mode we don't mess with the write buffer (we just perform the 160611051Sandreas.hansson@arm.com// writebacks atomically once the original request is complete). 160711051Sandreas.hansson@arm.comCacheBlk* 160811051Sandreas.hansson@arm.comCache::handleFill(PacketPtr pkt, CacheBlk *blk, PacketList &writebacks) 160911051Sandreas.hansson@arm.com{ 161011051Sandreas.hansson@arm.com assert(pkt->isResponse() || pkt->cmd == MemCmd::WriteLineReq); 161111051Sandreas.hansson@arm.com Addr addr = pkt->getAddr(); 161211051Sandreas.hansson@arm.com bool is_secure = pkt->isSecure(); 161311051Sandreas.hansson@arm.com#if TRACING_ON 161411051Sandreas.hansson@arm.com CacheBlk::State old_state = blk ? blk->status : 0; 161511051Sandreas.hansson@arm.com#endif 161611051Sandreas.hansson@arm.com 161711051Sandreas.hansson@arm.com // When handling a fill, discard any CleanEvicts for the 161811051Sandreas.hansson@arm.com // same address in write buffer. 161911051Sandreas.hansson@arm.com Addr M5_VAR_USED blk_addr = blockAlign(pkt->getAddr()); 162011051Sandreas.hansson@arm.com std::vector<MSHR *> M5_VAR_USED wbs; 162111051Sandreas.hansson@arm.com assert (!writeBuffer.findMatches(blk_addr, is_secure, wbs)); 162211051Sandreas.hansson@arm.com 162311051Sandreas.hansson@arm.com if (blk == NULL) { 162411051Sandreas.hansson@arm.com // better have read new data... 162511051Sandreas.hansson@arm.com assert(pkt->hasData()); 162611051Sandreas.hansson@arm.com 162711051Sandreas.hansson@arm.com // only read responses and write-line requests have data; 162811051Sandreas.hansson@arm.com // note that we don't write the data here for write-line - that 162911051Sandreas.hansson@arm.com // happens in the subsequent satisfyCpuSideRequest. 163011051Sandreas.hansson@arm.com assert(pkt->isRead() || pkt->cmd == MemCmd::WriteLineReq); 163111051Sandreas.hansson@arm.com 163211051Sandreas.hansson@arm.com // need to do a replacement 163311051Sandreas.hansson@arm.com blk = allocateBlock(addr, is_secure, writebacks); 163411051Sandreas.hansson@arm.com if (blk == NULL) { 163511051Sandreas.hansson@arm.com // No replaceable block... just use temporary storage to 163611865Snikos.nikoleris@arm.com // complete the current request and then get rid of it 163711865Snikos.nikoleris@arm.com assert(!tempBlock->isValid()); 163811865Snikos.nikoleris@arm.com blk = tempBlock; 163911051Sandreas.hansson@arm.com tempBlock->set = tags->extractSet(addr); 164011051Sandreas.hansson@arm.com tempBlock->tag = tags->extractTag(addr); 164111051Sandreas.hansson@arm.com // @todo: set security state as well... 164211051Sandreas.hansson@arm.com DPRINTF(Cache, "using temp block for %#llx (%s)\n", addr, 164311051Sandreas.hansson@arm.com is_secure ? "s" : "ns"); 164411051Sandreas.hansson@arm.com } else { 164511051Sandreas.hansson@arm.com tags->insertBlock(pkt, blk); 164611051Sandreas.hansson@arm.com } 164711051Sandreas.hansson@arm.com 164811051Sandreas.hansson@arm.com // we should never be overwriting a valid block 164911051Sandreas.hansson@arm.com assert(!blk->isValid()); 165011051Sandreas.hansson@arm.com } else { 165111051Sandreas.hansson@arm.com // existing block... probably an upgrade 165211051Sandreas.hansson@arm.com assert(blk->tag == tags->extractTag(addr)); 165311051Sandreas.hansson@arm.com // either we're getting new data or the block should already be valid 165411051Sandreas.hansson@arm.com assert(pkt->hasData() || blk->isValid()); 165511051Sandreas.hansson@arm.com // don't clear block status... if block is already dirty we 165611051Sandreas.hansson@arm.com // don't want to lose that 165711051Sandreas.hansson@arm.com } 165811051Sandreas.hansson@arm.com 165911051Sandreas.hansson@arm.com if (is_secure) 166011867Snikos.nikoleris@arm.com blk->status |= BlkSecure; 166111051Sandreas.hansson@arm.com blk->status |= BlkValid | BlkReadable; 166211051Sandreas.hansson@arm.com 166311051Sandreas.hansson@arm.com if (!pkt->sharedAsserted()) { 166411051Sandreas.hansson@arm.com // we could get non-shared responses from memory (rather than 166511051Sandreas.hansson@arm.com // a cache) even in a read-only cache, note that we set this 166611051Sandreas.hansson@arm.com // bit even for a read-only cache as we use it to represent 166711051Sandreas.hansson@arm.com // the exclusive state 166811051Sandreas.hansson@arm.com blk->status |= BlkWritable; 166911051Sandreas.hansson@arm.com 167011051Sandreas.hansson@arm.com // If we got this via cache-to-cache transfer (i.e., from a 167111484Snikos.nikoleris@arm.com // cache that was an owner) and took away that owner's copy, 167211051Sandreas.hansson@arm.com // then we need to write it back. Normally this happens 167311051Sandreas.hansson@arm.com // anyway as a side effect of getting a copy to write it, but 167411051Sandreas.hansson@arm.com // there are cases (such as failed store conditionals or 167511051Sandreas.hansson@arm.com // compare-and-swaps) where we'll demand an exclusive copy but 167611051Sandreas.hansson@arm.com // end up not writing it. 167711051Sandreas.hansson@arm.com if (pkt->memInhibitAsserted()) { 167811051Sandreas.hansson@arm.com blk->status |= BlkDirty; 167911051Sandreas.hansson@arm.com 168011051Sandreas.hansson@arm.com chatty_assert(!isReadOnly, "Should never see dirty snoop response " 168111051Sandreas.hansson@arm.com "in read-only cache %s\n", name()); 168211284Sandreas.hansson@arm.com } 168311051Sandreas.hansson@arm.com } 168411051Sandreas.hansson@arm.com 168511484Snikos.nikoleris@arm.com DPRINTF(Cache, "Block addr %#llx (%s) moving from state %x to %s\n", 168611051Sandreas.hansson@arm.com addr, is_secure ? "s" : "ns", old_state, blk->print()); 168711483Snikos.nikoleris@arm.com 168811483Snikos.nikoleris@arm.com // if we got new data, copy it in (checking for a read response 168911051Sandreas.hansson@arm.com // and a response that has data is the same in the end) 169011051Sandreas.hansson@arm.com if (pkt->isRead()) { 169111051Sandreas.hansson@arm.com // sanity checks 169211436SRekai.GonzalezAlberquilla@arm.com assert(pkt->hasData()); 169311436SRekai.GonzalezAlberquilla@arm.com assert(pkt->getSize() == blkSize); 169411436SRekai.GonzalezAlberquilla@arm.com 169511051Sandreas.hansson@arm.com std::memcpy(blk->data, pkt->getConstPtr<uint8_t>(), blkSize); 169611051Sandreas.hansson@arm.com } 169711199Sandreas.hansson@arm.com // We pay for fillLatency here. 169811051Sandreas.hansson@arm.com blk->whenReady = clockEdge() + fillLatency * clockPeriod() + 169911051Sandreas.hansson@arm.com pkt->payloadDelay; 170011051Sandreas.hansson@arm.com 170111051Sandreas.hansson@arm.com return blk; 170211051Sandreas.hansson@arm.com} 170311051Sandreas.hansson@arm.com 170411051Sandreas.hansson@arm.com 170511051Sandreas.hansson@arm.com///////////////////////////////////////////////////// 170611051Sandreas.hansson@arm.com// 170711051Sandreas.hansson@arm.com// Snoop path: requests coming in from the memory side 170811051Sandreas.hansson@arm.com// 170911197Sandreas.hansson@arm.com///////////////////////////////////////////////////// 171011197Sandreas.hansson@arm.com 171111197Sandreas.hansson@arm.comvoid 171211197Sandreas.hansson@arm.comCache::doTimingSupplyResponse(PacketPtr req_pkt, const uint8_t *blk_data, 171311197Sandreas.hansson@arm.com bool already_copied, bool pending_inval) 171411197Sandreas.hansson@arm.com{ 171511197Sandreas.hansson@arm.com // sanity check 171611051Sandreas.hansson@arm.com assert(req_pkt->isRequest()); 171711051Sandreas.hansson@arm.com assert(req_pkt->needsResponse()); 171811051Sandreas.hansson@arm.com 171911051Sandreas.hansson@arm.com DPRINTF(Cache, "%s for %s addr %#llx size %d\n", __func__, 172011051Sandreas.hansson@arm.com req_pkt->cmdString(), req_pkt->getAddr(), req_pkt->getSize()); 172111051Sandreas.hansson@arm.com // timing-mode snoop responses require a new packet, unless we 172211051Sandreas.hansson@arm.com // already made a copy... 172311197Sandreas.hansson@arm.com PacketPtr pkt = req_pkt; 172411197Sandreas.hansson@arm.com if (!already_copied) 172511051Sandreas.hansson@arm.com // do not clear flags, and allocate space for data if the 172611051Sandreas.hansson@arm.com // packet needs it (the only packets that carry data are read 172711051Sandreas.hansson@arm.com // responses) 172811051Sandreas.hansson@arm.com pkt = new Packet(req_pkt, false, req_pkt->isRead()); 172911051Sandreas.hansson@arm.com 173011051Sandreas.hansson@arm.com assert(req_pkt->req->isUncacheable() || req_pkt->isInvalidate() || 173111051Sandreas.hansson@arm.com pkt->sharedAsserted()); 173211051Sandreas.hansson@arm.com pkt->makeTimingResponse(); 173311375Sandreas.hansson@arm.com if (pkt->isRead()) { 173411892Snikos.nikoleris@arm.com pkt->setDataFromBlock(blk_data, blkSize); 173511375Sandreas.hansson@arm.com } 173611051Sandreas.hansson@arm.com if (pkt->cmd == MemCmd::ReadResp && pending_inval) { 173711484Snikos.nikoleris@arm.com // Assume we defer a response to a read from a far-away cache 173811051Sandreas.hansson@arm.com // A, then later defer a ReadExcl from a cache B on the same 173911051Sandreas.hansson@arm.com // bus as us. We'll assert MemInhibit in both cases, but in 174011051Sandreas.hansson@arm.com // the latter case MemInhibit will keep the invalidation from 174111051Sandreas.hansson@arm.com // reaching cache A. This special response tells cache A that 174211051Sandreas.hansson@arm.com // it gets the block to satisfy its read, but must immediately 174311601Sandreas.hansson@arm.com // invalidate it. 174411051Sandreas.hansson@arm.com pkt->cmd = MemCmd::ReadRespWithInvalidate; 174511051Sandreas.hansson@arm.com } 174611197Sandreas.hansson@arm.com // Here we consider forward_time, paying for just forward latency and 174711197Sandreas.hansson@arm.com // also charging the delay provided by the xbar. 174811484Snikos.nikoleris@arm.com // forward_time is used as send_time in next allocateWriteBuffer(). 174911197Sandreas.hansson@arm.com Tick forward_time = clockEdge(forwardLatency) + pkt->headerDelay; 175011484Snikos.nikoleris@arm.com // Here we reset the timing of the packet. 175111197Sandreas.hansson@arm.com pkt->headerDelay = pkt->payloadDelay = 0; 175211197Sandreas.hansson@arm.com DPRINTF(Cache, "%s created response: %s addr %#llx size %d tick: %lu\n", 175311197Sandreas.hansson@arm.com __func__, pkt->cmdString(), pkt->getAddr(), pkt->getSize(), 175411051Sandreas.hansson@arm.com forward_time); 175511051Sandreas.hansson@arm.com memSidePort->schedTimingSnoopResp(pkt, forward_time, true); 175611051Sandreas.hansson@arm.com} 175711051Sandreas.hansson@arm.com 175811051Sandreas.hansson@arm.comvoid 175911051Sandreas.hansson@arm.comCache::handleSnoop(PacketPtr pkt, CacheBlk *blk, bool is_timing, 176011051Sandreas.hansson@arm.com bool is_deferred, bool pending_inval) 176111051Sandreas.hansson@arm.com{ 176211051Sandreas.hansson@arm.com DPRINTF(Cache, "%s for %s addr %#llx size %d\n", __func__, 176311051Sandreas.hansson@arm.com pkt->cmdString(), pkt->getAddr(), pkt->getSize()); 176411051Sandreas.hansson@arm.com // deferred snoops can only happen in timing mode 176511051Sandreas.hansson@arm.com assert(!(is_deferred && !is_timing)); 176611051Sandreas.hansson@arm.com // pending_inval only makes sense on deferred snoops 176711051Sandreas.hansson@arm.com assert(!(pending_inval && !is_deferred)); 176811051Sandreas.hansson@arm.com assert(pkt->isRequest()); 176911051Sandreas.hansson@arm.com 177011051Sandreas.hansson@arm.com // the packet may get modified if we or a forwarded snooper 177111051Sandreas.hansson@arm.com // responds in atomic mode, so remember a few things about the 177211051Sandreas.hansson@arm.com // original packet up front 177311051Sandreas.hansson@arm.com bool invalidate = pkt->isInvalidate(); 177411051Sandreas.hansson@arm.com bool M5_VAR_USED needs_exclusive = pkt->needsExclusive(); 177511051Sandreas.hansson@arm.com 177611051Sandreas.hansson@arm.com if (forwardSnoops) { 177711051Sandreas.hansson@arm.com // first propagate snoop upward to see if anyone above us wants to 177811051Sandreas.hansson@arm.com // handle it. save & restore packet src since it will get 177911051Sandreas.hansson@arm.com // rewritten to be relative to cpu-side bus (if any) 178011137Sandreas.hansson@arm.com bool alreadyResponded = pkt->memInhibitAsserted(); 178111137Sandreas.hansson@arm.com if (is_timing) { 178211601Sandreas.hansson@arm.com // copy the packet so that we can clear any flags before 178311137Sandreas.hansson@arm.com // forwarding it upwards, we also allocate data (passing 178411284Sandreas.hansson@arm.com // the pointer along in case of static data), in case 178511137Sandreas.hansson@arm.com // there is a snoop hit in upper levels 178611137Sandreas.hansson@arm.com Packet snoopPkt(pkt, true, true); 178711284Sandreas.hansson@arm.com snoopPkt.setExpressSnoop(); 178811284Sandreas.hansson@arm.com snoopPkt.pushSenderState(new ForwardResponseRecord()); 178911284Sandreas.hansson@arm.com // the snoop packet does not need to wait any additional 179011284Sandreas.hansson@arm.com // time 179111284Sandreas.hansson@arm.com snoopPkt.headerDelay = snoopPkt.payloadDelay = 0; 179211284Sandreas.hansson@arm.com cpuSidePort->sendTimingSnoopReq(&snoopPkt); 179311284Sandreas.hansson@arm.com if (snoopPkt.memInhibitAsserted()) { 179411284Sandreas.hansson@arm.com // cache-to-cache response from some upper cache 179511284Sandreas.hansson@arm.com assert(!alreadyResponded); 179611284Sandreas.hansson@arm.com pkt->assertMemInhibit(); 179711284Sandreas.hansson@arm.com } else { 179811051Sandreas.hansson@arm.com // no cache (or anyone else for that matter) will 179911051Sandreas.hansson@arm.com // respond, so delete the ForwardResponseRecord here 180011284Sandreas.hansson@arm.com delete snoopPkt.popSenderState(); 180111284Sandreas.hansson@arm.com } 180211284Sandreas.hansson@arm.com if (snoopPkt.sharedAsserted()) { 180311284Sandreas.hansson@arm.com pkt->assertShared(); 180411284Sandreas.hansson@arm.com } 180511051Sandreas.hansson@arm.com // If this request is a prefetch or clean evict and an upper level 180611051Sandreas.hansson@arm.com // signals block present, make sure to propagate the block 180711051Sandreas.hansson@arm.com // presence to the requester. 180811051Sandreas.hansson@arm.com if (snoopPkt.isBlockCached()) { 180911051Sandreas.hansson@arm.com pkt->setBlockCached(); 181011051Sandreas.hansson@arm.com } 181111051Sandreas.hansson@arm.com } else { 181211051Sandreas.hansson@arm.com cpuSidePort->sendAtomicSnoop(pkt); 181311051Sandreas.hansson@arm.com if (!alreadyResponded && pkt->memInhibitAsserted()) { 181411051Sandreas.hansson@arm.com // cache-to-cache response from some upper cache: 181511051Sandreas.hansson@arm.com // forward response to original requester 181611051Sandreas.hansson@arm.com assert(pkt->isResponse()); 181711051Sandreas.hansson@arm.com } 181811051Sandreas.hansson@arm.com } 181911051Sandreas.hansson@arm.com } 182011051Sandreas.hansson@arm.com 182111051Sandreas.hansson@arm.com if (!blk || !blk->isValid()) { 182211051Sandreas.hansson@arm.com DPRINTF(Cache, "%s snoop miss for %s addr %#llx size %d\n", 182311051Sandreas.hansson@arm.com __func__, pkt->cmdString(), pkt->getAddr(), pkt->getSize()); 182411051Sandreas.hansson@arm.com return; 182511051Sandreas.hansson@arm.com } else { 182611051Sandreas.hansson@arm.com DPRINTF(Cache, "%s snoop hit for %s for addr %#llx size %d, " 182711051Sandreas.hansson@arm.com "old state is %s\n", __func__, pkt->cmdString(), 182811051Sandreas.hansson@arm.com pkt->getAddr(), pkt->getSize(), blk->print()); 182911051Sandreas.hansson@arm.com } 183011051Sandreas.hansson@arm.com 183111051Sandreas.hansson@arm.com chatty_assert(!(isReadOnly && blk->isDirty()), 183211051Sandreas.hansson@arm.com "Should never have a dirty block in a read-only cache %s\n", 183311051Sandreas.hansson@arm.com name()); 183411051Sandreas.hansson@arm.com 183511051Sandreas.hansson@arm.com // We may end up modifying both the block state and the packet (if 183611051Sandreas.hansson@arm.com // we respond in atomic mode), so just figure out what to do now 183711051Sandreas.hansson@arm.com // and then do it later. If we find dirty data while snooping for 183811051Sandreas.hansson@arm.com // an invalidate, we don't need to send a response. The 183911051Sandreas.hansson@arm.com // invalidation itself is taken care of below. 184011051Sandreas.hansson@arm.com bool respond = blk->isDirty() && pkt->needsResponse() && 184111051Sandreas.hansson@arm.com pkt->cmd != MemCmd::InvalidateReq; 184211051Sandreas.hansson@arm.com bool have_exclusive = blk->isWritable(); 184311051Sandreas.hansson@arm.com 184411051Sandreas.hansson@arm.com // Invalidate any prefetch's from below that would strip write permissions 184511051Sandreas.hansson@arm.com // MemCmd::HardPFReq is only observed by upstream caches. After missing 184611744Snikos.nikoleris@arm.com // above and in it's own cache, a new MemCmd::ReadReq is created that 184711051Sandreas.hansson@arm.com // downstream caches observe. 184811051Sandreas.hansson@arm.com if (pkt->mustCheckAbove()) { 184911051Sandreas.hansson@arm.com DPRINTF(Cache, "Found addr %#llx in upper level cache for snoop %s from" 185011051Sandreas.hansson@arm.com " lower cache\n", pkt->getAddr(), pkt->cmdString()); 185111051Sandreas.hansson@arm.com pkt->setBlockCached(); 185211051Sandreas.hansson@arm.com return; 185311051Sandreas.hansson@arm.com } 185411051Sandreas.hansson@arm.com 185511051Sandreas.hansson@arm.com if (!pkt->req->isUncacheable() && pkt->isRead() && !invalidate) { 185611051Sandreas.hansson@arm.com assert(!needs_exclusive); 185711284Sandreas.hansson@arm.com pkt->assertShared(); 185811051Sandreas.hansson@arm.com int bits_to_clear = BlkWritable; 185911051Sandreas.hansson@arm.com const bool haveOwnershipState = true; // for now 186011051Sandreas.hansson@arm.com if (!haveOwnershipState) { 186111051Sandreas.hansson@arm.com // if we don't support pure ownership (dirty && !writable), 186211051Sandreas.hansson@arm.com // have to clear dirty bit here, assume memory snarfs data 186311051Sandreas.hansson@arm.com // on cache-to-cache xfer 186411051Sandreas.hansson@arm.com bits_to_clear |= BlkDirty; 186511284Sandreas.hansson@arm.com } 186611284Sandreas.hansson@arm.com blk->status &= ~bits_to_clear; 186711284Sandreas.hansson@arm.com } 186811284Sandreas.hansson@arm.com 186911284Sandreas.hansson@arm.com if (respond) { 187011051Sandreas.hansson@arm.com // prevent anyone else from responding, cache as well as 187111051Sandreas.hansson@arm.com // memory, and also prevent any memory from even seeing the 187211051Sandreas.hansson@arm.com // request (with current inhibited semantics), note that this 187311051Sandreas.hansson@arm.com // applies both to reads and writes and that for writes it 187411051Sandreas.hansson@arm.com // works thanks to the fact that we still have dirty data and 187511051Sandreas.hansson@arm.com // will write it back at a later point 187611051Sandreas.hansson@arm.com pkt->assertMemInhibit(); 187711051Sandreas.hansson@arm.com if (have_exclusive) { 187811744Snikos.nikoleris@arm.com // in the case of an uncacheable request there is no need 187911744Snikos.nikoleris@arm.com // to set the exclusive flag, but since the recipient does 188011051Sandreas.hansson@arm.com // not care there is no harm in doing so 188111051Sandreas.hansson@arm.com pkt->setSupplyExclusive(); 188211051Sandreas.hansson@arm.com } 188311127Sandreas.hansson@arm.com if (is_timing) { 188411051Sandreas.hansson@arm.com doTimingSupplyResponse(pkt, blk->data, is_deferred, pending_inval); 188511051Sandreas.hansson@arm.com } else { 188611051Sandreas.hansson@arm.com pkt->makeAtomicResponse(); 188711744Snikos.nikoleris@arm.com pkt->setDataFromBlock(blk->data, blkSize); 188811051Sandreas.hansson@arm.com } 188911051Sandreas.hansson@arm.com } 189011051Sandreas.hansson@arm.com 189111051Sandreas.hansson@arm.com if (!respond && is_timing && is_deferred) { 189211051Sandreas.hansson@arm.com // if it's a deferred timing snoop then we've made a copy of 189311051Sandreas.hansson@arm.com // both the request and the packet, and so if we're not using 189411051Sandreas.hansson@arm.com // those copies to respond and delete them here 189511051Sandreas.hansson@arm.com DPRINTF(Cache, "Deleting pkt %p and request %p for cmd %s addr: %p\n", 189611051Sandreas.hansson@arm.com pkt, pkt->req, pkt->cmdString(), pkt->getAddr()); 189711051Sandreas.hansson@arm.com 189811284Sandreas.hansson@arm.com // the packets needs a response (just not from us), so we also 189911051Sandreas.hansson@arm.com // need to delete the request and not rely on the packet 190011285Sandreas.hansson@arm.com // destructor 190111285Sandreas.hansson@arm.com assert(pkt->needsResponse()); 190211285Sandreas.hansson@arm.com delete pkt->req; 190311285Sandreas.hansson@arm.com delete pkt; 190411744Snikos.nikoleris@arm.com } 190511744Snikos.nikoleris@arm.com 190611285Sandreas.hansson@arm.com // Do this last in case it deallocates block data or something 190711127Sandreas.hansson@arm.com // like that 190811127Sandreas.hansson@arm.com if (invalidate) { 190911051Sandreas.hansson@arm.com if (blk != tempBlock) 191011051Sandreas.hansson@arm.com tags->invalidate(blk); 191111051Sandreas.hansson@arm.com blk->invalidate(); 191211051Sandreas.hansson@arm.com } 191311284Sandreas.hansson@arm.com 191411051Sandreas.hansson@arm.com DPRINTF(Cache, "new state is %s\n", blk->print()); 191511051Sandreas.hansson@arm.com} 191611051Sandreas.hansson@arm.com 191711051Sandreas.hansson@arm.com 191811051Sandreas.hansson@arm.comvoid 191911051Sandreas.hansson@arm.comCache::recvTimingSnoopReq(PacketPtr pkt) 192011051Sandreas.hansson@arm.com{ 192111051Sandreas.hansson@arm.com DPRINTF(Cache, "%s for %s addr %#llx size %d\n", __func__, 192211051Sandreas.hansson@arm.com pkt->cmdString(), pkt->getAddr(), pkt->getSize()); 192311051Sandreas.hansson@arm.com 192411051Sandreas.hansson@arm.com // Snoops shouldn't happen when bypassing caches 192511127Sandreas.hansson@arm.com assert(!system->bypassCaches()); 192611127Sandreas.hansson@arm.com 192711127Sandreas.hansson@arm.com // no need to snoop writebacks or requests that are not in range 192811127Sandreas.hansson@arm.com if (!inRange(pkt->getAddr())) { 192911127Sandreas.hansson@arm.com return; 193011127Sandreas.hansson@arm.com } 193111284Sandreas.hansson@arm.com 193211051Sandreas.hansson@arm.com bool is_secure = pkt->isSecure(); 193311051Sandreas.hansson@arm.com CacheBlk *blk = tags->findBlock(pkt->getAddr(), is_secure); 193411284Sandreas.hansson@arm.com 193511051Sandreas.hansson@arm.com Addr blk_addr = blockAlign(pkt->getAddr()); 193611284Sandreas.hansson@arm.com MSHR *mshr = mshrQueue.findMatch(blk_addr, is_secure); 193711284Sandreas.hansson@arm.com 193811284Sandreas.hansson@arm.com // Inform request(Prefetch, CleanEvict or Writeback) from below of 193911284Sandreas.hansson@arm.com // MSHR hit, set setBlockCached. 194011051Sandreas.hansson@arm.com if (mshr && pkt->mustCheckAbove()) { 194111051Sandreas.hansson@arm.com DPRINTF(Cache, "Setting block cached for %s from" 194211051Sandreas.hansson@arm.com "lower cache on mshr hit %#x\n", 194311051Sandreas.hansson@arm.com pkt->cmdString(), pkt->getAddr()); 194411051Sandreas.hansson@arm.com pkt->setBlockCached(); 194511051Sandreas.hansson@arm.com return; 194611051Sandreas.hansson@arm.com } 194711051Sandreas.hansson@arm.com 194811051Sandreas.hansson@arm.com // Let the MSHR itself track the snoop and decide whether we want 194911284Sandreas.hansson@arm.com // to go ahead and do the regular cache snoop 195011051Sandreas.hansson@arm.com if (mshr && mshr->handleSnoop(pkt, order++)) { 195111051Sandreas.hansson@arm.com DPRINTF(Cache, "Deferring snoop on in-service MSHR to blk %#llx (%s)." 195211051Sandreas.hansson@arm.com "mshrs: %s\n", blk_addr, is_secure ? "s" : "ns", 195311051Sandreas.hansson@arm.com mshr->print()); 195411051Sandreas.hansson@arm.com 195511051Sandreas.hansson@arm.com if (mshr->getNumTargets() > numTarget) 195611051Sandreas.hansson@arm.com warn("allocating bonus target for snoop"); //handle later 195711051Sandreas.hansson@arm.com return; 195811744Snikos.nikoleris@arm.com } 195911744Snikos.nikoleris@arm.com 196011493Sandreas.hansson@arm.com //We also need to check the writeback buffers and handle those 196111493Sandreas.hansson@arm.com std::vector<MSHR *> writebacks; 196211493Sandreas.hansson@arm.com if (writeBuffer.findMatches(blk_addr, is_secure, writebacks)) { 196311493Sandreas.hansson@arm.com DPRINTF(Cache, "Snoop hit in writeback to addr %#llx (%s)\n", 196411493Sandreas.hansson@arm.com pkt->getAddr(), is_secure ? "s" : "ns"); 196511493Sandreas.hansson@arm.com 196611493Sandreas.hansson@arm.com // Look through writebacks for any cachable writes. 196711493Sandreas.hansson@arm.com // We should only ever find a single match 196811493Sandreas.hansson@arm.com assert(writebacks.size() == 1); 196911493Sandreas.hansson@arm.com MSHR *wb_entry = writebacks[0]; 197011493Sandreas.hansson@arm.com // Expect to see only Writebacks and/or CleanEvicts here, both of 197111493Sandreas.hansson@arm.com // which should not be generated for uncacheable data. 197211127Sandreas.hansson@arm.com assert(!wb_entry->isUncacheable()); 197311051Sandreas.hansson@arm.com // There should only be a single request responsible for generating 197411744Snikos.nikoleris@arm.com // Writebacks/CleanEvicts. 197511744Snikos.nikoleris@arm.com assert(wb_entry->getNumTargets() == 1); 197611051Sandreas.hansson@arm.com PacketPtr wb_pkt = wb_entry->getTarget()->pkt; 197711051Sandreas.hansson@arm.com assert(wb_pkt->evictingBlock()); 197811051Sandreas.hansson@arm.com 197911051Sandreas.hansson@arm.com if (pkt->evictingBlock()) { 198011051Sandreas.hansson@arm.com // if the block is found in the write queue, set the BLOCK_CACHED 198111051Sandreas.hansson@arm.com // flag for Writeback/CleanEvict snoop. On return the snoop will 198211051Sandreas.hansson@arm.com // propagate the BLOCK_CACHED flag in Writeback packets and prevent 198311051Sandreas.hansson@arm.com // any CleanEvicts from travelling down the memory hierarchy. 198411751Snikos.nikoleris@arm.com pkt->setBlockCached(); 198511751Snikos.nikoleris@arm.com DPRINTF(Cache, "Squashing %s from lower cache on writequeue hit" 198611051Sandreas.hansson@arm.com " %#x\n", pkt->cmdString(), pkt->getAddr()); 198711751Snikos.nikoleris@arm.com return; 198811284Sandreas.hansson@arm.com } 198911051Sandreas.hansson@arm.com 199011051Sandreas.hansson@arm.com if (wb_pkt->cmd == MemCmd::Writeback) { 199111051Sandreas.hansson@arm.com assert(!pkt->memInhibitAsserted()); 199211051Sandreas.hansson@arm.com pkt->assertMemInhibit(); 199311051Sandreas.hansson@arm.com if (!pkt->needsExclusive()) { 199411051Sandreas.hansson@arm.com pkt->assertShared(); 199511483Snikos.nikoleris@arm.com // the writeback is no longer passing exclusivity (the 199611744Snikos.nikoleris@arm.com // receiving cache should consider the block owned 199711051Sandreas.hansson@arm.com // rather than modified) 199811127Sandreas.hansson@arm.com wb_pkt->assertShared(); 199911051Sandreas.hansson@arm.com } else { 200011051Sandreas.hansson@arm.com // if we're not asserting the shared line, we need to 200111285Sandreas.hansson@arm.com // invalidate our copy. we'll do that below as long as 200211285Sandreas.hansson@arm.com // the packet's invalidate flag is set... 200311284Sandreas.hansson@arm.com assert(pkt->isInvalidate()); 200411284Sandreas.hansson@arm.com } 200511285Sandreas.hansson@arm.com doTimingSupplyResponse(pkt, wb_pkt->getConstPtr<uint8_t>(), 200611285Sandreas.hansson@arm.com false, false); 200711285Sandreas.hansson@arm.com } else { 200811285Sandreas.hansson@arm.com assert(wb_pkt->cmd == MemCmd::CleanEvict); 200911285Sandreas.hansson@arm.com // The cache technically holds the block until the 201011285Sandreas.hansson@arm.com // corresponding CleanEvict message reaches the crossbar 201111285Sandreas.hansson@arm.com // below. Therefore when a snoop encounters a CleanEvict 201211285Sandreas.hansson@arm.com // message we must set assertShared (just like when it 201311051Sandreas.hansson@arm.com // encounters a Writeback) to avoid the snoop filter 201411051Sandreas.hansson@arm.com // prematurely clearing the holder bit in the crossbar 201511051Sandreas.hansson@arm.com // below 201611051Sandreas.hansson@arm.com if (!pkt->needsExclusive()) 201711051Sandreas.hansson@arm.com pkt->assertShared(); 201811284Sandreas.hansson@arm.com else 201911284Sandreas.hansson@arm.com assert(pkt->isInvalidate()); 202011284Sandreas.hansson@arm.com } 202111284Sandreas.hansson@arm.com 202211284Sandreas.hansson@arm.com if (pkt->isInvalidate()) { 202311284Sandreas.hansson@arm.com // Invalidation trumps our writeback... discard here 202411284Sandreas.hansson@arm.com // Note: markInService will remove entry from writeback buffer. 202511284Sandreas.hansson@arm.com markInService(wb_entry, false); 202611081Sandreas.hansson@arm.com delete wb_pkt; 202711284Sandreas.hansson@arm.com } 202811284Sandreas.hansson@arm.com } 202911284Sandreas.hansson@arm.com 203011284Sandreas.hansson@arm.com // If this was a shared writeback, there may still be 203111284Sandreas.hansson@arm.com // other shared copies above that require invalidation. 203211284Sandreas.hansson@arm.com // We could be more selective and return here if the 203311284Sandreas.hansson@arm.com // request is non-exclusive or if the writeback is 203411051Sandreas.hansson@arm.com // exclusive. 203511284Sandreas.hansson@arm.com handleSnoop(pkt, blk, true, false, false); 203611285Sandreas.hansson@arm.com} 203711285Sandreas.hansson@arm.com 203811285Sandreas.hansson@arm.combool 203911744Snikos.nikoleris@arm.comCache::CpuSidePort::recvTimingSnoopResp(PacketPtr pkt) 204011744Snikos.nikoleris@arm.com{ 204111285Sandreas.hansson@arm.com // Express snoop responses from master to slave, e.g., from L1 to L2 204211051Sandreas.hansson@arm.com cache->recvTimingSnoopResp(pkt); 204311051Sandreas.hansson@arm.com return true; 204411051Sandreas.hansson@arm.com} 204511051Sandreas.hansson@arm.com 204611286Sandreas.hansson@arm.comTick 204711286Sandreas.hansson@arm.comCache::recvAtomicSnoop(PacketPtr pkt) 204811286Sandreas.hansson@arm.com{ 204911286Sandreas.hansson@arm.com // Snoops shouldn't happen when bypassing caches 205011051Sandreas.hansson@arm.com assert(!system->bypassCaches()); 205111051Sandreas.hansson@arm.com 205211051Sandreas.hansson@arm.com // no need to snoop writebacks or requests that are not in range. In 205311602Sandreas.hansson@arm.com // atomic we have no Writebacks/CleanEvicts queued and no prefetches, 205411051Sandreas.hansson@arm.com // hence there is no need to snoop upwards and determine if they are 205511602Sandreas.hansson@arm.com // present above. 205611602Sandreas.hansson@arm.com if (pkt->evictingBlock() || !inRange(pkt->getAddr())) { 205711602Sandreas.hansson@arm.com return 0; 205811602Sandreas.hansson@arm.com } 205911602Sandreas.hansson@arm.com 206011602Sandreas.hansson@arm.com CacheBlk *blk = tags->findBlock(pkt->getAddr(), pkt->isSecure()); 206111602Sandreas.hansson@arm.com handleSnoop(pkt, blk, false, false, false); 206211602Sandreas.hansson@arm.com // We consider forwardLatency here because a snoop occurs in atomic mode 206311602Sandreas.hansson@arm.com return forwardLatency * clockPeriod(); 206411051Sandreas.hansson@arm.com} 206511051Sandreas.hansson@arm.com 206611051Sandreas.hansson@arm.com 206711051Sandreas.hansson@arm.comMSHR * 206811051Sandreas.hansson@arm.comCache::getNextMSHR() 206911051Sandreas.hansson@arm.com{ 207011197Sandreas.hansson@arm.com // Check both MSHR queue and write buffer for potential requests, 207111051Sandreas.hansson@arm.com // note that null does not mean there is no request, it could 207211051Sandreas.hansson@arm.com // simply be that it is not ready 207311051Sandreas.hansson@arm.com MSHR *miss_mshr = mshrQueue.getNextMSHR(); 207411127Sandreas.hansson@arm.com MSHR *write_mshr = writeBuffer.getNextMSHR(); 207511127Sandreas.hansson@arm.com 207611051Sandreas.hansson@arm.com // If we got a write buffer request ready, first priority is a 207711051Sandreas.hansson@arm.com // full write buffer, otherwhise we favour the miss requests 207811051Sandreas.hansson@arm.com if (write_mshr && 207911051Sandreas.hansson@arm.com ((writeBuffer.isFull() && writeBuffer.inServiceEntries == 0) || 208011051Sandreas.hansson@arm.com !miss_mshr)) { 208111051Sandreas.hansson@arm.com // need to search MSHR queue for conflicting earlier miss. 208211744Snikos.nikoleris@arm.com MSHR *conflict_mshr = 208311051Sandreas.hansson@arm.com mshrQueue.findPending(write_mshr->blkAddr, 208411051Sandreas.hansson@arm.com write_mshr->isSecure); 208511051Sandreas.hansson@arm.com 208611051Sandreas.hansson@arm.com if (conflict_mshr && conflict_mshr->order < write_mshr->order) { 208711130Sali.jafri@arm.com // Service misses in order until conflict is cleared. 208811051Sandreas.hansson@arm.com return conflict_mshr; 208911051Sandreas.hansson@arm.com 209011051Sandreas.hansson@arm.com // @todo Note that we ignore the ready time of the conflict here 209111051Sandreas.hansson@arm.com } 209211051Sandreas.hansson@arm.com 209311051Sandreas.hansson@arm.com // No conflicts; issue write 209411051Sandreas.hansson@arm.com return write_mshr; 209511892Snikos.nikoleris@arm.com } else if (miss_mshr) { 209611051Sandreas.hansson@arm.com // need to check for conflicting earlier writeback 209711051Sandreas.hansson@arm.com MSHR *conflict_mshr = 209811127Sandreas.hansson@arm.com writeBuffer.findPending(miss_mshr->blkAddr, 209911127Sandreas.hansson@arm.com miss_mshr->isSecure); 210011127Sandreas.hansson@arm.com if (conflict_mshr) { 210111127Sandreas.hansson@arm.com // not sure why we don't check order here... it was in the 210211127Sandreas.hansson@arm.com // original code but commented out. 210311127Sandreas.hansson@arm.com 210411127Sandreas.hansson@arm.com // The only way this happens is if we are 210511127Sandreas.hansson@arm.com // doing a write and we didn't have permissions 210611051Sandreas.hansson@arm.com // then subsequently saw a writeback (owned got evicted) 210711051Sandreas.hansson@arm.com // We need to make sure to perform the writeback first 210811051Sandreas.hansson@arm.com // To preserve the dirty data, then we can issue the write 210911744Snikos.nikoleris@arm.com 211011744Snikos.nikoleris@arm.com // should we return write_mshr here instead? I.e. do we 211111051Sandreas.hansson@arm.com // have to flush writes in order? I don't think so... not 211211051Sandreas.hansson@arm.com // for Alpha anyway. Maybe for x86? 211311051Sandreas.hansson@arm.com return conflict_mshr; 211411051Sandreas.hansson@arm.com 211511051Sandreas.hansson@arm.com // @todo Note that we ignore the ready time of the conflict here 211611051Sandreas.hansson@arm.com } 211711051Sandreas.hansson@arm.com 211811051Sandreas.hansson@arm.com // No conflicts; issue read 211911051Sandreas.hansson@arm.com return miss_mshr; 212011051Sandreas.hansson@arm.com } 212111051Sandreas.hansson@arm.com 212211051Sandreas.hansson@arm.com // fall through... no pending requests. Try a prefetch. 212311051Sandreas.hansson@arm.com assert(!miss_mshr && !write_mshr); 212411051Sandreas.hansson@arm.com if (prefetcher && mshrQueue.canPrefetch()) { 212511051Sandreas.hansson@arm.com // If we have a miss queue slot, we can try a prefetch 212611051Sandreas.hansson@arm.com PacketPtr pkt = prefetcher->getPacket(); 212711051Sandreas.hansson@arm.com if (pkt) { 212811375Sandreas.hansson@arm.com Addr pf_addr = blockAlign(pkt->getAddr()); 212911375Sandreas.hansson@arm.com if (!tags->findBlock(pf_addr, pkt->isSecure()) && 213011051Sandreas.hansson@arm.com !mshrQueue.findMatch(pf_addr, pkt->isSecure()) && 213111051Sandreas.hansson@arm.com !writeBuffer.findMatch(pf_addr, pkt->isSecure())) { 213211051Sandreas.hansson@arm.com // Update statistic on number of prefetches issued 213311051Sandreas.hansson@arm.com // (hwpf_mshr_misses) 213411051Sandreas.hansson@arm.com assert(pkt->req->masterId() < system->maxMasters()); 213511051Sandreas.hansson@arm.com mshr_misses[pkt->cmdToIndex()][pkt->req->masterId()]++; 213611051Sandreas.hansson@arm.com 213711051Sandreas.hansson@arm.com // allocate an MSHR and return it, note 213811051Sandreas.hansson@arm.com // that we send the packet straight away, so do not 213911199Sandreas.hansson@arm.com // schedule the send 214011051Sandreas.hansson@arm.com return allocateMissBuffer(pkt, curTick(), false); 214111199Sandreas.hansson@arm.com } else { 214211051Sandreas.hansson@arm.com // free the request and packet 214311051Sandreas.hansson@arm.com delete pkt->req; 214411051Sandreas.hansson@arm.com delete pkt; 214511051Sandreas.hansson@arm.com } 214611051Sandreas.hansson@arm.com } 214711744Snikos.nikoleris@arm.com } 214811744Snikos.nikoleris@arm.com 214911051Sandreas.hansson@arm.com return NULL; 215011051Sandreas.hansson@arm.com} 215111051Sandreas.hansson@arm.com 215211332Sandreas.hansson@arm.combool 215311332Sandreas.hansson@arm.comCache::isCachedAbove(const PacketPtr pkt) const 215411332Sandreas.hansson@arm.com{ 215511332Sandreas.hansson@arm.com if (!forwardSnoops) 215611332Sandreas.hansson@arm.com return false; 215711332Sandreas.hansson@arm.com // Mirroring the flow of HardPFReqs, the cache sends CleanEvict and 215811751Snikos.nikoleris@arm.com // Writeback snoops into upper level caches to check for copies of the 215911332Sandreas.hansson@arm.com // same block. Using the BLOCK_CACHED flag with the Writeback/CleanEvict 216011332Sandreas.hansson@arm.com // packet, the cache can inform the crossbar below of presence or absence 216111332Sandreas.hansson@arm.com // of the block. 216211332Sandreas.hansson@arm.com 216311332Sandreas.hansson@arm.com Packet snoop_pkt(pkt, true, false); 216411332Sandreas.hansson@arm.com snoop_pkt.setExpressSnoop(); 216511332Sandreas.hansson@arm.com // Assert that packet is either Writeback or CleanEvict and not a prefetch 216611332Sandreas.hansson@arm.com // request because prefetch requests need an MSHR and may generate a snoop 216711332Sandreas.hansson@arm.com // response. 216811332Sandreas.hansson@arm.com assert(pkt->evictingBlock()); 216911284Sandreas.hansson@arm.com snoop_pkt.senderState = NULL; 217011332Sandreas.hansson@arm.com cpuSidePort->sendTimingSnoopReq(&snoop_pkt); 217111332Sandreas.hansson@arm.com // Writeback/CleanEvict snoops do not generate a separate snoop response. 217211332Sandreas.hansson@arm.com assert(!(snoop_pkt.memInhibitAsserted())); 217311051Sandreas.hansson@arm.com return snoop_pkt.isBlockCached(); 217411332Sandreas.hansson@arm.com} 217511051Sandreas.hansson@arm.com 217611051Sandreas.hansson@arm.comPacketPtr 217711051Sandreas.hansson@arm.comCache::getTimingPacket() 217811051Sandreas.hansson@arm.com{ 217911332Sandreas.hansson@arm.com MSHR *mshr = getNextMSHR(); 218011051Sandreas.hansson@arm.com 218111051Sandreas.hansson@arm.com if (mshr == NULL) { 218211375Sandreas.hansson@arm.com return NULL; 218311051Sandreas.hansson@arm.com } 218411051Sandreas.hansson@arm.com 218511051Sandreas.hansson@arm.com // use request from 1st target 218611051Sandreas.hansson@arm.com PacketPtr tgt_pkt = mshr->getTarget()->pkt; 218711051Sandreas.hansson@arm.com PacketPtr pkt = NULL; 218811051Sandreas.hansson@arm.com 218911051Sandreas.hansson@arm.com DPRINTF(CachePort, "%s %s for addr %#llx size %d\n", __func__, 219011051Sandreas.hansson@arm.com tgt_pkt->cmdString(), tgt_pkt->getAddr(), tgt_pkt->getSize()); 219111051Sandreas.hansson@arm.com 219211127Sandreas.hansson@arm.com CacheBlk *blk = tags->findBlock(mshr->blkAddr, mshr->isSecure); 219311127Sandreas.hansson@arm.com 219411127Sandreas.hansson@arm.com if (tgt_pkt->cmd == MemCmd::HardPFReq && forwardSnoops) { 219511127Sandreas.hansson@arm.com // We need to check the caches above us to verify that 219611127Sandreas.hansson@arm.com // they don't have a copy of this block in the dirty state 219711127Sandreas.hansson@arm.com // at the moment. Without this check we could get a stale 219811051Sandreas.hansson@arm.com // copy from memory that might get used in place of the 219911051Sandreas.hansson@arm.com // dirty one. 220011051Sandreas.hansson@arm.com Packet snoop_pkt(tgt_pkt, true, false); 220111051Sandreas.hansson@arm.com snoop_pkt.setExpressSnoop(); 220211051Sandreas.hansson@arm.com snoop_pkt.senderState = mshr; 220311051Sandreas.hansson@arm.com cpuSidePort->sendTimingSnoopReq(&snoop_pkt); 220411051Sandreas.hansson@arm.com 220511051Sandreas.hansson@arm.com // Check to see if the prefetch was squashed by an upper cache (to 220611051Sandreas.hansson@arm.com // prevent us from grabbing the line) or if a Check to see if a 220711051Sandreas.hansson@arm.com // writeback arrived between the time the prefetch was placed in 220811051Sandreas.hansson@arm.com // the MSHRs and when it was selected to be sent or if the 220911051Sandreas.hansson@arm.com // prefetch was squashed by an upper cache. 221011051Sandreas.hansson@arm.com 221111051Sandreas.hansson@arm.com // It is important to check memInhibitAsserted before 221211051Sandreas.hansson@arm.com // prefetchSquashed. If another cache has asserted MEM_INGIBIT, it 221311051Sandreas.hansson@arm.com // will be sending a response which will arrive at the MSHR 221411130Sali.jafri@arm.com // allocated ofr this request. Checking the prefetchSquash first 221511130Sali.jafri@arm.com // may result in the MSHR being prematurely deallocated. 221611051Sandreas.hansson@arm.com 221711051Sandreas.hansson@arm.com if (snoop_pkt.memInhibitAsserted()) { 221811051Sandreas.hansson@arm.com // If we are getting a non-shared response it is dirty 221911051Sandreas.hansson@arm.com bool pending_dirty_resp = !snoop_pkt.sharedAsserted(); 222011127Sandreas.hansson@arm.com markInService(mshr, pending_dirty_resp); 222111127Sandreas.hansson@arm.com DPRINTF(Cache, "Upward snoop of prefetch for addr" 222211051Sandreas.hansson@arm.com " %#x (%s) hit\n", 222311051Sandreas.hansson@arm.com tgt_pkt->getAddr(), tgt_pkt->isSecure()? "s": "ns"); 222411051Sandreas.hansson@arm.com return NULL; 222511375Sandreas.hansson@arm.com } 222611375Sandreas.hansson@arm.com 222711051Sandreas.hansson@arm.com if (snoop_pkt.isBlockCached() || blk != NULL) { 222811051Sandreas.hansson@arm.com DPRINTF(Cache, "Block present, prefetch squashed by cache. " 222911051Sandreas.hansson@arm.com "Deallocating mshr target %#x.\n", 223011051Sandreas.hansson@arm.com mshr->blkAddr); 223111375Sandreas.hansson@arm.com 223211375Sandreas.hansson@arm.com // Deallocate the mshr target 223311051Sandreas.hansson@arm.com if (tgt_pkt->cmd != MemCmd::Writeback) { 223411051Sandreas.hansson@arm.com if (mshr->queue->forceDeallocateTarget(mshr)) { 223511453Sandreas.hansson@arm.com // Clear block if this deallocation resulted freed an 223611453Sandreas.hansson@arm.com // mshr when all had previously been utilized 223711051Sandreas.hansson@arm.com clearBlocked((BlockedCause)(mshr->queue->index)); 223811051Sandreas.hansson@arm.com } 223911375Sandreas.hansson@arm.com return NULL; 224011375Sandreas.hansson@arm.com } else { 224111375Sandreas.hansson@arm.com // If this is a Writeback, and the snoops indicate that the blk 224211375Sandreas.hansson@arm.com // is cached above, set the BLOCK_CACHED flag in the Writeback 224311051Sandreas.hansson@arm.com // packet, so that it does not reset the bits corresponding to 224411051Sandreas.hansson@arm.com // this block in the snoop filter below. 224511051Sandreas.hansson@arm.com tgt_pkt->setBlockCached(); 224611051Sandreas.hansson@arm.com } 224711051Sandreas.hansson@arm.com } 224811051Sandreas.hansson@arm.com } 224911051Sandreas.hansson@arm.com 225011375Sandreas.hansson@arm.com if (mshr->isForwardNoResponse()) { 225111051Sandreas.hansson@arm.com // no response expected, just forward packet as it is 225211051Sandreas.hansson@arm.com assert(tags->findBlock(mshr->blkAddr, mshr->isSecure) == NULL); 225311375Sandreas.hansson@arm.com pkt = tgt_pkt; 225411051Sandreas.hansson@arm.com } else { 225511051Sandreas.hansson@arm.com pkt = getBusPacket(tgt_pkt, blk, mshr->needsExclusive()); 225611051Sandreas.hansson@arm.com 225711051Sandreas.hansson@arm.com mshr->isForward = (pkt == NULL); 225811051Sandreas.hansson@arm.com 225911051Sandreas.hansson@arm.com if (mshr->isForward) { 226011051Sandreas.hansson@arm.com // not a cache block request, but a response is expected 226111051Sandreas.hansson@arm.com // make copy of current packet to forward, keep current 226211051Sandreas.hansson@arm.com // copy for response handling 226311051Sandreas.hansson@arm.com pkt = new Packet(tgt_pkt, false, true); 226411051Sandreas.hansson@arm.com if (pkt->isWrite()) { 226511051Sandreas.hansson@arm.com pkt->setData(tgt_pkt->getConstPtr<uint8_t>()); 226611375Sandreas.hansson@arm.com } 226711051Sandreas.hansson@arm.com } 226811051Sandreas.hansson@arm.com } 226911051Sandreas.hansson@arm.com 227011051Sandreas.hansson@arm.com assert(pkt != NULL); 227111051Sandreas.hansson@arm.com pkt->senderState = mshr; 227211051Sandreas.hansson@arm.com return pkt; 227311051Sandreas.hansson@arm.com} 227411051Sandreas.hansson@arm.com 227511051Sandreas.hansson@arm.com 227611051Sandreas.hansson@arm.comTick 227711051Sandreas.hansson@arm.comCache::nextMSHRReadyTime() const 227811051Sandreas.hansson@arm.com{ 227911375Sandreas.hansson@arm.com Tick nextReady = std::min(mshrQueue.nextMSHRReadyTime(), 228011051Sandreas.hansson@arm.com writeBuffer.nextMSHRReadyTime()); 228111051Sandreas.hansson@arm.com 228211051Sandreas.hansson@arm.com // Don't signal prefetch ready time if no MSHRs available 228311051Sandreas.hansson@arm.com // Will signal once enoguh MSHRs are deallocated 228411892Snikos.nikoleris@arm.com if (prefetcher && mshrQueue.canPrefetch()) { 228511051Sandreas.hansson@arm.com nextReady = std::min(nextReady, 228611051Sandreas.hansson@arm.com prefetcher->nextPrefetchReadyTime()); 228711051Sandreas.hansson@arm.com } 228811051Sandreas.hansson@arm.com 228911051Sandreas.hansson@arm.com return nextReady; 229011051Sandreas.hansson@arm.com} 229111051Sandreas.hansson@arm.com 229211051Sandreas.hansson@arm.comvoid 229311051Sandreas.hansson@arm.comCache::serialize(CheckpointOut &cp) const 229411051Sandreas.hansson@arm.com{ 229511051Sandreas.hansson@arm.com bool dirty(isDirty()); 229611051Sandreas.hansson@arm.com 229711051Sandreas.hansson@arm.com if (dirty) { 229811051Sandreas.hansson@arm.com warn("*** The cache still contains dirty data. ***\n"); 229911051Sandreas.hansson@arm.com warn(" Make sure to drain the system using the correct flags.\n"); 230011051Sandreas.hansson@arm.com warn(" This checkpoint will not restore correctly and dirty data in " 230111051Sandreas.hansson@arm.com "the cache will be lost!\n"); 230211051Sandreas.hansson@arm.com } 230311051Sandreas.hansson@arm.com 230411051Sandreas.hansson@arm.com // Since we don't checkpoint the data in the cache, any dirty data 230511375Sandreas.hansson@arm.com // will be lost when restoring from a checkpoint of a system that 230611051Sandreas.hansson@arm.com // wasn't drained properly. Flag the checkpoint as invalid if the 230711051Sandreas.hansson@arm.com // cache contains dirty data. 230811051Sandreas.hansson@arm.com bool bad_checkpoint(dirty); 230911130Sali.jafri@arm.com SERIALIZE_SCALAR(bad_checkpoint); 231011051Sandreas.hansson@arm.com} 231111051Sandreas.hansson@arm.com 231211051Sandreas.hansson@arm.comvoid 231311051Sandreas.hansson@arm.comCache::unserialize(CheckpointIn &cp) 231411051Sandreas.hansson@arm.com{ 231511051Sandreas.hansson@arm.com bool bad_checkpoint; 231611051Sandreas.hansson@arm.com UNSERIALIZE_SCALAR(bad_checkpoint); 231711051Sandreas.hansson@arm.com if (bad_checkpoint) { 231811130Sali.jafri@arm.com fatal("Restoring from checkpoints with dirty caches is not supported " 231911130Sali.jafri@arm.com "in the classic memory system. Please remove any caches or " 232011130Sali.jafri@arm.com " drain them properly before taking checkpoints.\n"); 232111130Sali.jafri@arm.com } 232211130Sali.jafri@arm.com} 232311130Sali.jafri@arm.com 232411199Sandreas.hansson@arm.com/////////////// 232511484Snikos.nikoleris@arm.com// 232611130Sali.jafri@arm.com// CpuSidePort 232711130Sali.jafri@arm.com// 232811284Sandreas.hansson@arm.com/////////////// 232911130Sali.jafri@arm.com 233011130Sali.jafri@arm.comAddrRangeList 233111130Sali.jafri@arm.comCache::CpuSidePort::getAddrRanges() const 233211130Sali.jafri@arm.com{ 233311130Sali.jafri@arm.com return cache->getAddrRanges(); 233411051Sandreas.hansson@arm.com} 233511051Sandreas.hansson@arm.com 233611375Sandreas.hansson@arm.combool 233711375Sandreas.hansson@arm.comCache::CpuSidePort::recvTimingReq(PacketPtr pkt) 233811051Sandreas.hansson@arm.com{ 233911375Sandreas.hansson@arm.com assert(!cache->system->bypassCaches()); 234011375Sandreas.hansson@arm.com 234111375Sandreas.hansson@arm.com bool success = false; 234211375Sandreas.hansson@arm.com 234311375Sandreas.hansson@arm.com // always let inhibited requests through, even if blocked, 234411375Sandreas.hansson@arm.com // ultimately we should check if this is an express snoop, but at 234511375Sandreas.hansson@arm.com // the moment that flag is only set in the cache itself 234611375Sandreas.hansson@arm.com if (pkt->memInhibitAsserted()) { 234711051Sandreas.hansson@arm.com // do not change the current retry state 234811051Sandreas.hansson@arm.com bool M5_VAR_USED bypass_success = cache->recvTimingReq(pkt); 234911375Sandreas.hansson@arm.com assert(bypass_success); 235011375Sandreas.hansson@arm.com return true; 235111375Sandreas.hansson@arm.com } else if (blocked || mustSendRetry) { 235211375Sandreas.hansson@arm.com // either already committed to send a retry, or blocked 235311375Sandreas.hansson@arm.com success = false; 235411375Sandreas.hansson@arm.com } else { 235511375Sandreas.hansson@arm.com // pass it on to the cache, and let the cache decide if we 235611375Sandreas.hansson@arm.com // have to retry or not 235711051Sandreas.hansson@arm.com success = cache->recvTimingReq(pkt); 235811051Sandreas.hansson@arm.com } 235911375Sandreas.hansson@arm.com 236011744Snikos.nikoleris@arm.com // remember if we have to retry 236111051Sandreas.hansson@arm.com mustSendRetry = !success; 236211051Sandreas.hansson@arm.com return success; 236311051Sandreas.hansson@arm.com} 236411051Sandreas.hansson@arm.com 236511375Sandreas.hansson@arm.comTick 236611375Sandreas.hansson@arm.comCache::CpuSidePort::recvAtomic(PacketPtr pkt) 236711484Snikos.nikoleris@arm.com{ 236811375Sandreas.hansson@arm.com return cache->recvAtomic(pkt); 236911051Sandreas.hansson@arm.com} 237011051Sandreas.hansson@arm.com 237111051Sandreas.hansson@arm.comvoid 237211051Sandreas.hansson@arm.comCache::CpuSidePort::recvFunctional(PacketPtr pkt) 237311051Sandreas.hansson@arm.com{ 237411051Sandreas.hansson@arm.com // functional request 237511051Sandreas.hansson@arm.com cache->functionalAccess(pkt, true); 237611275Sandreas.hansson@arm.com} 237711275Sandreas.hansson@arm.com 237811275Sandreas.hansson@arm.comCache:: 237911275Sandreas.hansson@arm.comCpuSidePort::CpuSidePort(const std::string &_name, Cache *_cache, 238011051Sandreas.hansson@arm.com const std::string &_label) 238111051Sandreas.hansson@arm.com : BaseCache::CacheSlavePort(_name, _cache, _label), cache(_cache) 238211051Sandreas.hansson@arm.com{ 238311051Sandreas.hansson@arm.com} 238411051Sandreas.hansson@arm.com 238511051Sandreas.hansson@arm.comCache* 238611051Sandreas.hansson@arm.comCacheParams::create() 238711051Sandreas.hansson@arm.com{ 238811051Sandreas.hansson@arm.com assert(tags); 238911284Sandreas.hansson@arm.com 239011284Sandreas.hansson@arm.com return new Cache(this); 239111284Sandreas.hansson@arm.com} 239211284Sandreas.hansson@arm.com/////////////// 239311284Sandreas.hansson@arm.com// 239411284Sandreas.hansson@arm.com// MemSidePort 239511284Sandreas.hansson@arm.com// 239611276Sandreas.hansson@arm.com/////////////// 239711276Sandreas.hansson@arm.com 239811284Sandreas.hansson@arm.combool 239911284Sandreas.hansson@arm.comCache::MemSidePort::recvTimingResp(PacketPtr pkt) 240011284Sandreas.hansson@arm.com{ 240111284Sandreas.hansson@arm.com cache->recvTimingResp(pkt); 240211284Sandreas.hansson@arm.com return true; 240311284Sandreas.hansson@arm.com} 240411051Sandreas.hansson@arm.com 240511051Sandreas.hansson@arm.com// Express snooping requests to memside port 240611051Sandreas.hansson@arm.comvoid 240711375Sandreas.hansson@arm.comCache::MemSidePort::recvTimingSnoopReq(PacketPtr pkt) 240811051Sandreas.hansson@arm.com{ 240911051Sandreas.hansson@arm.com // handle snooping requests 241011375Sandreas.hansson@arm.com cache->recvTimingSnoopReq(pkt); 241111051Sandreas.hansson@arm.com} 241211051Sandreas.hansson@arm.com 241311051Sandreas.hansson@arm.comTick 241411375Sandreas.hansson@arm.comCache::MemSidePort::recvAtomicSnoop(PacketPtr pkt) 241511051Sandreas.hansson@arm.com{ 241611375Sandreas.hansson@arm.com return cache->recvAtomicSnoop(pkt); 241711277Sandreas.hansson@arm.com} 241811277Sandreas.hansson@arm.com 241911375Sandreas.hansson@arm.comvoid 242011051Sandreas.hansson@arm.comCache::MemSidePort::recvFunctionalSnoop(PacketPtr pkt) 242111375Sandreas.hansson@arm.com{ 242211051Sandreas.hansson@arm.com // functional snoop (note that in contrast to atomic we don't have 242311051Sandreas.hansson@arm.com // a specific functionalSnoop method, as they have the same 242411051Sandreas.hansson@arm.com // behaviour regardless) 242511375Sandreas.hansson@arm.com cache->functionalAccess(pkt, false); 242611375Sandreas.hansson@arm.com} 242711452Sandreas.hansson@arm.com 242811375Sandreas.hansson@arm.comvoid 242911484Snikos.nikoleris@arm.comCache::CacheReqPacketQueue::sendDeferredPacket() 243011375Sandreas.hansson@arm.com{ 243111375Sandreas.hansson@arm.com // sanity check 243211375Sandreas.hansson@arm.com assert(!waitingOnRetry); 243311375Sandreas.hansson@arm.com 243411375Sandreas.hansson@arm.com // there should never be any deferred request packets in the 243511375Sandreas.hansson@arm.com // queue, instead we resly on the cache to provide the packets 243611375Sandreas.hansson@arm.com // from the MSHR queue or write queue 243711375Sandreas.hansson@arm.com assert(deferredPacketReadyTime() == MaxTick); 243811375Sandreas.hansson@arm.com 243911375Sandreas.hansson@arm.com // check for request packets (requests & writebacks) 244011375Sandreas.hansson@arm.com PacketPtr pkt = cache.getTimingPacket(); 244111375Sandreas.hansson@arm.com if (pkt == NULL) { 244211375Sandreas.hansson@arm.com // can happen if e.g. we attempt a writeback and fail, but 244311375Sandreas.hansson@arm.com // before the retry, the writeback is eliminated because 244411375Sandreas.hansson@arm.com // we snoop another cache's ReadEx. 244511375Sandreas.hansson@arm.com } else { 244611375Sandreas.hansson@arm.com MSHR *mshr = dynamic_cast<MSHR*>(pkt->senderState); 244711375Sandreas.hansson@arm.com // in most cases getTimingPacket allocates a new packet, and 244811375Sandreas.hansson@arm.com // we must delete it unless it is successfully sent 244911375Sandreas.hansson@arm.com bool delete_pkt = !mshr->isForwardNoResponse(); 245011375Sandreas.hansson@arm.com 245111375Sandreas.hansson@arm.com // let our snoop responses go first if there are responses to 245211375Sandreas.hansson@arm.com // the same addresses we are about to writeback, note that 245311375Sandreas.hansson@arm.com // this creates a dependency between requests and snoop 245411375Sandreas.hansson@arm.com // responses, but that should not be a problem since there is 245511375Sandreas.hansson@arm.com // a chain already and the key is that the snoop responses can 245611375Sandreas.hansson@arm.com // sink unconditionally 245711375Sandreas.hansson@arm.com if (snoopRespQueue.hasAddr(pkt->getAddr())) { 245811375Sandreas.hansson@arm.com DPRINTF(CachePort, "Waiting for snoop response to be sent\n"); 245911375Sandreas.hansson@arm.com Tick when = snoopRespQueue.deferredPacketReadyTime(); 246011375Sandreas.hansson@arm.com schedSendEvent(when); 246111375Sandreas.hansson@arm.com 246211375Sandreas.hansson@arm.com if (delete_pkt) 246311375Sandreas.hansson@arm.com delete pkt; 246411375Sandreas.hansson@arm.com 246511375Sandreas.hansson@arm.com return; 246611375Sandreas.hansson@arm.com } 246711375Sandreas.hansson@arm.com 246811375Sandreas.hansson@arm.com 246911375Sandreas.hansson@arm.com waitingOnRetry = !masterPort.sendTimingReq(pkt); 247011375Sandreas.hansson@arm.com 247111375Sandreas.hansson@arm.com if (waitingOnRetry) { 247211375Sandreas.hansson@arm.com DPRINTF(CachePort, "now waiting on a retry\n"); 247311375Sandreas.hansson@arm.com if (delete_pkt) { 247411375Sandreas.hansson@arm.com // we are awaiting a retry, but we 247511375Sandreas.hansson@arm.com // delete the packet and will be creating a new packet 247611375Sandreas.hansson@arm.com // when we get the opportunity 247711375Sandreas.hansson@arm.com delete pkt; 247811744Snikos.nikoleris@arm.com } 247911375Sandreas.hansson@arm.com // note that we have now masked any requestBus and 248011453Sandreas.hansson@arm.com // schedSendEvent (we will wait for a retry before 248111453Sandreas.hansson@arm.com // doing anything), and this is so even if we do not 248211375Sandreas.hansson@arm.com // care about this packet and might override it before 248311375Sandreas.hansson@arm.com // it gets retried 248411375Sandreas.hansson@arm.com } else { 248511375Sandreas.hansson@arm.com // As part of the call to sendTimingReq the packet is 248611375Sandreas.hansson@arm.com // forwarded to all neighbouring caches (and any 248711375Sandreas.hansson@arm.com // caches above them) as a snoop. The packet is also 248811375Sandreas.hansson@arm.com // sent to any potential cache below as the 248911375Sandreas.hansson@arm.com // interconnect is not allowed to buffer the 249011375Sandreas.hansson@arm.com // packet. Thus at this point we know if any of the 249111051Sandreas.hansson@arm.com // neighbouring, or the downstream cache is 249211051Sandreas.hansson@arm.com // responding, and if so, if it is with a dirty line 249311051Sandreas.hansson@arm.com // or not. 249411051Sandreas.hansson@arm.com bool pending_dirty_resp = !pkt->sharedAsserted() && 249511051Sandreas.hansson@arm.com pkt->memInhibitAsserted(); 249611051Sandreas.hansson@arm.com 249711051Sandreas.hansson@arm.com cache.markInService(mshr, pending_dirty_resp); 249811051Sandreas.hansson@arm.com } 249911051Sandreas.hansson@arm.com } 250011051Sandreas.hansson@arm.com 250111051Sandreas.hansson@arm.com // if we succeeded and are not waiting for a retry, schedule the 250211483Snikos.nikoleris@arm.com // next send considering when the next MSHR is ready, note that 250311483Snikos.nikoleris@arm.com // snoop responses have their own packet queue and thus schedule 250411051Sandreas.hansson@arm.com // their own events 250511051Sandreas.hansson@arm.com if (!waitingOnRetry) { 250611051Sandreas.hansson@arm.com schedSendEvent(cache.nextMSHRReadyTime()); 250711051Sandreas.hansson@arm.com } 250811051Sandreas.hansson@arm.com} 250911051Sandreas.hansson@arm.com 251011051Sandreas.hansson@arm.comCache:: 251111051Sandreas.hansson@arm.comMemSidePort::MemSidePort(const std::string &_name, Cache *_cache, 251211051Sandreas.hansson@arm.com const std::string &_label) 251311051Sandreas.hansson@arm.com : BaseCache::CacheMasterPort(_name, _cache, _reqQueue, _snoopRespQueue), 251411051Sandreas.hansson@arm.com _reqQueue(*_cache, *this, _snoopRespQueue, _label), 251511051Sandreas.hansson@arm.com _snoopRespQueue(*_cache, *this, _label), cache(_cache) 251611051Sandreas.hansson@arm.com{ 251711051Sandreas.hansson@arm.com} 251811051Sandreas.hansson@arm.com