base.hh revision 10821
12810SN/A/* 210693SMarco.Balboni@ARM.com * Copyright (c) 2012-2013, 2015 ARM Limited 38856Sandreas.hansson@arm.com * All rights reserved. 48856Sandreas.hansson@arm.com * 58856Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall 68856Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual 78856Sandreas.hansson@arm.com * property including but not limited to intellectual property relating 88856Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software 98856Sandreas.hansson@arm.com * licensed hereunder. You may use the software subject to the license 108856Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated 118856Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software, 128856Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form. 138856Sandreas.hansson@arm.com * 142810SN/A * Copyright (c) 2003-2005 The Regents of The University of Michigan 152810SN/A * All rights reserved. 162810SN/A * 172810SN/A * Redistribution and use in source and binary forms, with or without 182810SN/A * modification, are permitted provided that the following conditions are 192810SN/A * met: redistributions of source code must retain the above copyright 202810SN/A * notice, this list of conditions and the following disclaimer; 212810SN/A * redistributions in binary form must reproduce the above copyright 222810SN/A * notice, this list of conditions and the following disclaimer in the 232810SN/A * documentation and/or other materials provided with the distribution; 242810SN/A * neither the name of the copyright holders nor the names of its 252810SN/A * contributors may be used to endorse or promote products derived from 262810SN/A * this software without specific prior written permission. 272810SN/A * 282810SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292810SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302810SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312810SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322810SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332810SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342810SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352810SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362810SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372810SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382810SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392810SN/A * 402810SN/A * Authors: Erik Hallnor 414458SN/A * Steve Reinhardt 424458SN/A * Ron Dreslinski 432810SN/A */ 442810SN/A 452810SN/A/** 462810SN/A * @file 472810SN/A * Declares a basic cache interface BaseCache. 482810SN/A */ 492810SN/A 502810SN/A#ifndef __BASE_CACHE_HH__ 512810SN/A#define __BASE_CACHE_HH__ 522810SN/A 537676Snate@binkert.org#include <algorithm> 547676Snate@binkert.org#include <list> 557676Snate@binkert.org#include <string> 562810SN/A#include <vector> 572810SN/A 582825SN/A#include "base/misc.hh" 592810SN/A#include "base/statistics.hh" 602810SN/A#include "base/trace.hh" 616215Snate@binkert.org#include "base/types.hh" 628232Snate@binkert.org#include "debug/Cache.hh" 638232Snate@binkert.org#include "debug/CachePort.hh" 645338Sstever@gmail.com#include "mem/cache/mshr_queue.hh" 652810SN/A#include "mem/mem_object.hh" 662810SN/A#include "mem/packet.hh" 678914Sandreas.hansson@arm.com#include "mem/qport.hh" 688229Snate@binkert.org#include "mem/request.hh" 695034SN/A#include "params/BaseCache.hh" 702811SN/A#include "sim/eventq.hh" 718786Sgblack@eecs.umich.edu#include "sim/full_system.hh" 724626SN/A#include "sim/sim_exit.hh" 738833Sdam.sunwoo@arm.com#include "sim/system.hh" 742810SN/A 753194SN/Aclass MSHR; 762810SN/A/** 772810SN/A * A basic cache interface. Implements some common functions for speed. 782810SN/A */ 792810SN/Aclass BaseCache : public MemObject 802810SN/A{ 814628SN/A /** 824628SN/A * Indexes to enumerate the MSHR queues. 834628SN/A */ 844628SN/A enum MSHRQueueIndex { 854628SN/A MSHRQueue_MSHRs, 864628SN/A MSHRQueue_WriteBuffer 874628SN/A }; 884628SN/A 898737Skoansin.tan@gmail.com public: 904628SN/A /** 914628SN/A * Reasons for caches to be blocked. 924628SN/A */ 934628SN/A enum BlockedCause { 944628SN/A Blocked_NoMSHRs = MSHRQueue_MSHRs, 954628SN/A Blocked_NoWBBuffers = MSHRQueue_WriteBuffer, 964628SN/A Blocked_NoTargets, 974628SN/A NUM_BLOCKED_CAUSES 984628SN/A }; 994628SN/A 1004628SN/A /** 1014628SN/A * Reasons for cache to request a bus. 1024628SN/A */ 1034628SN/A enum RequestCause { 1044628SN/A Request_MSHR = MSHRQueue_MSHRs, 1054628SN/A Request_WB = MSHRQueue_WriteBuffer, 1064628SN/A Request_PF, 1074628SN/A NUM_REQUEST_CAUSES 1084628SN/A }; 1094628SN/A 1108737Skoansin.tan@gmail.com protected: 1114628SN/A 1128856Sandreas.hansson@arm.com /** 1138856Sandreas.hansson@arm.com * A cache master port is used for the memory-side port of the 1148856Sandreas.hansson@arm.com * cache, and in addition to the basic timing port that only sends 1158856Sandreas.hansson@arm.com * response packets through a transmit list, it also offers the 1168856Sandreas.hansson@arm.com * ability to schedule and send request packets (requests & 1178856Sandreas.hansson@arm.com * writebacks). The send event is scheduled through requestBus, 1188856Sandreas.hansson@arm.com * and the sendDeferredPacket of the timing port is modified to 1198856Sandreas.hansson@arm.com * consider both the transmit list and the requests from the MSHR. 1208856Sandreas.hansson@arm.com */ 1218922Swilliam.wang@arm.com class CacheMasterPort : public QueuedMasterPort 1222810SN/A { 1238856Sandreas.hansson@arm.com 1242844SN/A public: 1258856Sandreas.hansson@arm.com 1268856Sandreas.hansson@arm.com /** 1278856Sandreas.hansson@arm.com * Schedule a send of a request packet (from the MSHR). Note 12810713Sandreas.hansson@arm.com * that we could already have a retry outstanding. 1298856Sandreas.hansson@arm.com */ 1308856Sandreas.hansson@arm.com void requestBus(RequestCause cause, Tick time) 1318856Sandreas.hansson@arm.com { 13210714Sandreas.hansson@arm.com DPRINTF(CachePort, "Scheduling request at %llu due to %d\n", 13310714Sandreas.hansson@arm.com time, cause); 13410713Sandreas.hansson@arm.com reqQueue.schedSendEvent(time); 1358856Sandreas.hansson@arm.com } 1368856Sandreas.hansson@arm.com 1373738SN/A protected: 1384458SN/A 1398856Sandreas.hansson@arm.com CacheMasterPort(const std::string &_name, BaseCache *_cache, 14010713Sandreas.hansson@arm.com ReqPacketQueue &_reqQueue, 14110713Sandreas.hansson@arm.com SnoopRespPacketQueue &_snoopRespQueue) : 14210713Sandreas.hansson@arm.com QueuedMasterPort(_name, _cache, _reqQueue, _snoopRespQueue) 1438914Sandreas.hansson@arm.com { } 1442810SN/A 1458856Sandreas.hansson@arm.com /** 1468856Sandreas.hansson@arm.com * Memory-side port always snoops. 1478856Sandreas.hansson@arm.com * 1488914Sandreas.hansson@arm.com * @return always true 1498856Sandreas.hansson@arm.com */ 1508922Swilliam.wang@arm.com virtual bool isSnooping() const { return true; } 1518856Sandreas.hansson@arm.com }; 1523013SN/A 1538856Sandreas.hansson@arm.com /** 1548856Sandreas.hansson@arm.com * A cache slave port is used for the CPU-side port of the cache, 1558856Sandreas.hansson@arm.com * and it is basically a simple timing port that uses a transmit 1568856Sandreas.hansson@arm.com * list for responses to the CPU (or connected master). In 1578856Sandreas.hansson@arm.com * addition, it has the functionality to block the port for 1588856Sandreas.hansson@arm.com * incoming requests. If blocked, the port will issue a retry once 1598856Sandreas.hansson@arm.com * unblocked. 1608856Sandreas.hansson@arm.com */ 1618922Swilliam.wang@arm.com class CacheSlavePort : public QueuedSlavePort 1628856Sandreas.hansson@arm.com { 1635314SN/A 1642811SN/A public: 1658856Sandreas.hansson@arm.com 1668856Sandreas.hansson@arm.com /** Do not accept any new requests. */ 1672810SN/A void setBlocked(); 1682810SN/A 1698856Sandreas.hansson@arm.com /** Return to normal operation and accept new requests. */ 1702810SN/A void clearBlocked(); 1712810SN/A 17210345SCurtis.Dunham@arm.com bool isBlocked() const { return blocked; } 17310345SCurtis.Dunham@arm.com 1748856Sandreas.hansson@arm.com protected: 1758856Sandreas.hansson@arm.com 1768856Sandreas.hansson@arm.com CacheSlavePort(const std::string &_name, BaseCache *_cache, 1778856Sandreas.hansson@arm.com const std::string &_label); 1783606SN/A 1798914Sandreas.hansson@arm.com /** A normal packet queue used to store responses. */ 18010713Sandreas.hansson@arm.com RespPacketQueue queue; 1818914Sandreas.hansson@arm.com 1822810SN/A bool blocked; 1832810SN/A 1842897SN/A bool mustSendRetry; 1852897SN/A 1868856Sandreas.hansson@arm.com private: 1874458SN/A 18810344Sandreas.hansson@arm.com void processSendRetry(); 18910344Sandreas.hansson@arm.com 19010344Sandreas.hansson@arm.com EventWrapper<CacheSlavePort, 19110344Sandreas.hansson@arm.com &CacheSlavePort::processSendRetry> sendRetryEvent; 1928856Sandreas.hansson@arm.com 1932811SN/A }; 1942810SN/A 1958856Sandreas.hansson@arm.com CacheSlavePort *cpuSidePort; 1968856Sandreas.hansson@arm.com CacheMasterPort *memSidePort; 1973338SN/A 1984626SN/A protected: 1994626SN/A 2004626SN/A /** Miss status registers */ 2014626SN/A MSHRQueue mshrQueue; 2024626SN/A 2034626SN/A /** Write/writeback buffer */ 2044626SN/A MSHRQueue writeBuffer; 2054626SN/A 20610693SMarco.Balboni@ARM.com /** 20710693SMarco.Balboni@ARM.com * Allocate a buffer, passing the time indicating when schedule an 20810693SMarco.Balboni@ARM.com * event to the queued port to go and ask the MSHR and write queue 20910693SMarco.Balboni@ARM.com * if they have packets to send. 21010693SMarco.Balboni@ARM.com * 21110693SMarco.Balboni@ARM.com * allocateBufferInternal() function is called in: 21210693SMarco.Balboni@ARM.com * - MSHR allocateWriteBuffer (unchached write forwarded to WriteBuffer); 21310767Sandreas.hansson@arm.com * - MSHR allocateMissBuffer (miss in MSHR queue); 21410693SMarco.Balboni@ARM.com */ 2154628SN/A MSHR *allocateBufferInternal(MSHRQueue *mq, Addr addr, int size, 2164628SN/A PacketPtr pkt, Tick time, bool requestBus) 2174628SN/A { 21810764Sandreas.hansson@arm.com // check that the address is block aligned since we rely on 21910764Sandreas.hansson@arm.com // this in a number of places when checking for matches and 22010764Sandreas.hansson@arm.com // overlap 22110764Sandreas.hansson@arm.com assert(addr == blockAlign(addr)); 22210764Sandreas.hansson@arm.com 2234666SN/A MSHR *mshr = mq->allocate(addr, size, pkt, time, order++); 2244628SN/A 2254628SN/A if (mq->isFull()) { 2264628SN/A setBlocked((BlockedCause)mq->index); 2274628SN/A } 2284628SN/A 2294628SN/A if (requestBus) { 2304628SN/A requestMemSideBus((RequestCause)mq->index, time); 2314628SN/A } 2324628SN/A 2334628SN/A return mshr; 2344628SN/A } 2354628SN/A 23610679Sandreas.hansson@arm.com void markInServiceInternal(MSHR *mshr, bool pending_dirty_resp) 2374628SN/A { 2384628SN/A MSHRQueue *mq = mshr->queue; 2394628SN/A bool wasFull = mq->isFull(); 24010679Sandreas.hansson@arm.com mq->markInService(mshr, pending_dirty_resp); 2414628SN/A if (wasFull && !mq->isFull()) { 2424628SN/A clearBlocked((BlockedCause)mq->index); 2434628SN/A } 2444628SN/A } 2454628SN/A 2469347SAndreas.Sandberg@arm.com /** 2479347SAndreas.Sandberg@arm.com * Write back dirty blocks in the cache using functional accesses. 2489347SAndreas.Sandberg@arm.com */ 2499347SAndreas.Sandberg@arm.com virtual void memWriteback() = 0; 2509347SAndreas.Sandberg@arm.com /** 2519347SAndreas.Sandberg@arm.com * Invalidates all blocks in the cache. 2529347SAndreas.Sandberg@arm.com * 2539347SAndreas.Sandberg@arm.com * @warn Dirty cache lines will not be written back to 2549347SAndreas.Sandberg@arm.com * memory. Make sure to call functionalWriteback() first if you 2559347SAndreas.Sandberg@arm.com * want the to write them to memory. 2569347SAndreas.Sandberg@arm.com */ 2579347SAndreas.Sandberg@arm.com virtual void memInvalidate() = 0; 2589347SAndreas.Sandberg@arm.com /** 2599347SAndreas.Sandberg@arm.com * Determine if there are any dirty blocks in the cache. 2609347SAndreas.Sandberg@arm.com * 2619347SAndreas.Sandberg@arm.com * \return true if at least one block is dirty, false otherwise. 2629347SAndreas.Sandberg@arm.com */ 2639347SAndreas.Sandberg@arm.com virtual bool isDirty() const = 0; 2649347SAndreas.Sandberg@arm.com 26510821Sandreas.hansson@arm.com /** 26610821Sandreas.hansson@arm.com * Determine if an address is in the ranges covered by this 26710821Sandreas.hansson@arm.com * cache. This is useful to filter snoops. 26810821Sandreas.hansson@arm.com * 26910821Sandreas.hansson@arm.com * @param addr Address to check against 27010821Sandreas.hansson@arm.com * 27110821Sandreas.hansson@arm.com * @return If the address in question is in range 27210821Sandreas.hansson@arm.com */ 27310821Sandreas.hansson@arm.com bool inRange(Addr addr) const; 27410821Sandreas.hansson@arm.com 2754626SN/A /** Block size of this cache */ 2766227Snate@binkert.org const unsigned blkSize; 2774626SN/A 2784630SN/A /** 27910693SMarco.Balboni@ARM.com * The latency of tag lookup of a cache. It occurs when there is 28010693SMarco.Balboni@ARM.com * an access to the cache. 2814630SN/A */ 28210693SMarco.Balboni@ARM.com const Cycles lookupLatency; 2839263Smrinmoy.ghosh@arm.com 2849263Smrinmoy.ghosh@arm.com /** 28510693SMarco.Balboni@ARM.com * This is the forward latency of the cache. It occurs when there 28610693SMarco.Balboni@ARM.com * is a cache miss and a request is forwarded downstream, in 28710693SMarco.Balboni@ARM.com * particular an outbound miss. 28810693SMarco.Balboni@ARM.com */ 28910693SMarco.Balboni@ARM.com const Cycles forwardLatency; 29010693SMarco.Balboni@ARM.com 29110693SMarco.Balboni@ARM.com /** The latency to fill a cache block */ 29210693SMarco.Balboni@ARM.com const Cycles fillLatency; 29310693SMarco.Balboni@ARM.com 29410693SMarco.Balboni@ARM.com /** 29510693SMarco.Balboni@ARM.com * The latency of sending reponse to its upper level cache/core on 29610693SMarco.Balboni@ARM.com * a linefill. The responseLatency parameter captures this 29710693SMarco.Balboni@ARM.com * latency. 2989263Smrinmoy.ghosh@arm.com */ 2999288Sandreas.hansson@arm.com const Cycles responseLatency; 3004630SN/A 3014626SN/A /** The number of targets for each MSHR. */ 3024626SN/A const int numTarget; 3034626SN/A 3046122SSteve.Reinhardt@amd.com /** Do we forward snoops from mem side port through to cpu side port? */ 3059529Sandreas.hansson@arm.com const bool forwardSnoops; 3064626SN/A 3078134SAli.Saidi@ARM.com /** Is this cache a toplevel cache (e.g. L1, I/O cache). If so we should 3088134SAli.Saidi@ARM.com * never try to forward ownership and similar optimizations to the cpu 3098134SAli.Saidi@ARM.com * side */ 3109529Sandreas.hansson@arm.com const bool isTopLevel; 3118134SAli.Saidi@ARM.com 3122810SN/A /** 3132810SN/A * Bit vector of the blocking reasons for the access path. 3142810SN/A * @sa #BlockedCause 3152810SN/A */ 3162810SN/A uint8_t blocked; 3172810SN/A 3186122SSteve.Reinhardt@amd.com /** Increasing order number assigned to each incoming request. */ 3196122SSteve.Reinhardt@amd.com uint64_t order; 3206122SSteve.Reinhardt@amd.com 3212810SN/A /** Stores time the cache blocked for statistics. */ 3229288Sandreas.hansson@arm.com Cycles blockedCycle; 3232810SN/A 3244626SN/A /** Pointer to the MSHR that has no targets. */ 3254626SN/A MSHR *noTargetMSHR; 3262810SN/A 3272810SN/A /** The number of misses to trigger an exit event. */ 3282810SN/A Counter missCount; 3292810SN/A 3306122SSteve.Reinhardt@amd.com /** 3316122SSteve.Reinhardt@amd.com * The address range to which the cache responds on the CPU side. 3326122SSteve.Reinhardt@amd.com * Normally this is all possible memory addresses. */ 3339529Sandreas.hansson@arm.com const AddrRangeList addrRanges; 3346122SSteve.Reinhardt@amd.com 3358833Sdam.sunwoo@arm.com public: 3368833Sdam.sunwoo@arm.com /** System we are currently operating in. */ 3378833Sdam.sunwoo@arm.com System *system; 3386978SLisa.Hsu@amd.com 3392810SN/A // Statistics 3402810SN/A /** 3412810SN/A * @addtogroup CacheStatistics 3422810SN/A * @{ 3432810SN/A */ 3442810SN/A 3452810SN/A /** Number of hits per thread for each type of command. @sa Packet::Command */ 3465999Snate@binkert.org Stats::Vector hits[MemCmd::NUM_MEM_CMDS]; 3472810SN/A /** Number of hits for demand accesses. */ 3482810SN/A Stats::Formula demandHits; 3492810SN/A /** Number of hit for all accesses. */ 3502810SN/A Stats::Formula overallHits; 3512810SN/A 3522810SN/A /** Number of misses per thread for each type of command. @sa Packet::Command */ 3535999Snate@binkert.org Stats::Vector misses[MemCmd::NUM_MEM_CMDS]; 3542810SN/A /** Number of misses for demand accesses. */ 3552810SN/A Stats::Formula demandMisses; 3562810SN/A /** Number of misses for all accesses. */ 3572810SN/A Stats::Formula overallMisses; 3582810SN/A 3592810SN/A /** 3602810SN/A * Total number of cycles per thread/command spent waiting for a miss. 3612810SN/A * Used to calculate the average miss latency. 3622810SN/A */ 3635999Snate@binkert.org Stats::Vector missLatency[MemCmd::NUM_MEM_CMDS]; 3642810SN/A /** Total number of cycles spent waiting for demand misses. */ 3652810SN/A Stats::Formula demandMissLatency; 3662810SN/A /** Total number of cycles spent waiting for all misses. */ 3672810SN/A Stats::Formula overallMissLatency; 3682810SN/A 3692810SN/A /** The number of accesses per command and thread. */ 3704022SN/A Stats::Formula accesses[MemCmd::NUM_MEM_CMDS]; 3712810SN/A /** The number of demand accesses. */ 3722810SN/A Stats::Formula demandAccesses; 3732810SN/A /** The number of overall accesses. */ 3742810SN/A Stats::Formula overallAccesses; 3752810SN/A 3762810SN/A /** The miss rate per command and thread. */ 3774022SN/A Stats::Formula missRate[MemCmd::NUM_MEM_CMDS]; 3782810SN/A /** The miss rate of all demand accesses. */ 3792810SN/A Stats::Formula demandMissRate; 3802810SN/A /** The miss rate for all accesses. */ 3812810SN/A Stats::Formula overallMissRate; 3822810SN/A 3832810SN/A /** The average miss latency per command and thread. */ 3844022SN/A Stats::Formula avgMissLatency[MemCmd::NUM_MEM_CMDS]; 3852810SN/A /** The average miss latency for demand misses. */ 3862810SN/A Stats::Formula demandAvgMissLatency; 3872810SN/A /** The average miss latency for all misses. */ 3882810SN/A Stats::Formula overallAvgMissLatency; 3892810SN/A 3902810SN/A /** The total number of cycles blocked for each blocked cause. */ 3915999Snate@binkert.org Stats::Vector blocked_cycles; 3922810SN/A /** The number of times this cache blocked for each blocked cause. */ 3935999Snate@binkert.org Stats::Vector blocked_causes; 3942810SN/A 3952810SN/A /** The average number of cycles blocked for each blocked cause. */ 3962810SN/A Stats::Formula avg_blocked; 3972810SN/A 3982810SN/A /** The number of fast writes (WH64) performed. */ 3995999Snate@binkert.org Stats::Scalar fastWrites; 4002810SN/A 4012810SN/A /** The number of cache copies performed. */ 4025999Snate@binkert.org Stats::Scalar cacheCopies; 4032810SN/A 4044626SN/A /** Number of blocks written back per thread. */ 4055999Snate@binkert.org Stats::Vector writebacks; 4064626SN/A 4074626SN/A /** Number of misses that hit in the MSHRs per command and thread. */ 4085999Snate@binkert.org Stats::Vector mshr_hits[MemCmd::NUM_MEM_CMDS]; 4094626SN/A /** Demand misses that hit in the MSHRs. */ 4104626SN/A Stats::Formula demandMshrHits; 4114626SN/A /** Total number of misses that hit in the MSHRs. */ 4124626SN/A Stats::Formula overallMshrHits; 4134626SN/A 4144626SN/A /** Number of misses that miss in the MSHRs, per command and thread. */ 4155999Snate@binkert.org Stats::Vector mshr_misses[MemCmd::NUM_MEM_CMDS]; 4164626SN/A /** Demand misses that miss in the MSHRs. */ 4174626SN/A Stats::Formula demandMshrMisses; 4184626SN/A /** Total number of misses that miss in the MSHRs. */ 4194626SN/A Stats::Formula overallMshrMisses; 4204626SN/A 4214626SN/A /** Number of misses that miss in the MSHRs, per command and thread. */ 4225999Snate@binkert.org Stats::Vector mshr_uncacheable[MemCmd::NUM_MEM_CMDS]; 4234626SN/A /** Total number of misses that miss in the MSHRs. */ 4244626SN/A Stats::Formula overallMshrUncacheable; 4254626SN/A 4264626SN/A /** Total cycle latency of each MSHR miss, per command and thread. */ 4275999Snate@binkert.org Stats::Vector mshr_miss_latency[MemCmd::NUM_MEM_CMDS]; 4284626SN/A /** Total cycle latency of demand MSHR misses. */ 4294626SN/A Stats::Formula demandMshrMissLatency; 4304626SN/A /** Total cycle latency of overall MSHR misses. */ 4314626SN/A Stats::Formula overallMshrMissLatency; 4324626SN/A 4334626SN/A /** Total cycle latency of each MSHR miss, per command and thread. */ 4345999Snate@binkert.org Stats::Vector mshr_uncacheable_lat[MemCmd::NUM_MEM_CMDS]; 4354626SN/A /** Total cycle latency of overall MSHR misses. */ 4364626SN/A Stats::Formula overallMshrUncacheableLatency; 4374626SN/A 4387461Snate@binkert.org#if 0 4394626SN/A /** The total number of MSHR accesses per command and thread. */ 4404626SN/A Stats::Formula mshrAccesses[MemCmd::NUM_MEM_CMDS]; 4414626SN/A /** The total number of demand MSHR accesses. */ 4424626SN/A Stats::Formula demandMshrAccesses; 4434626SN/A /** The total number of MSHR accesses. */ 4444626SN/A Stats::Formula overallMshrAccesses; 4457461Snate@binkert.org#endif 4464626SN/A 4474626SN/A /** The miss rate in the MSHRs pre command and thread. */ 4484626SN/A Stats::Formula mshrMissRate[MemCmd::NUM_MEM_CMDS]; 4494626SN/A /** The demand miss rate in the MSHRs. */ 4504626SN/A Stats::Formula demandMshrMissRate; 4514626SN/A /** The overall miss rate in the MSHRs. */ 4524626SN/A Stats::Formula overallMshrMissRate; 4534626SN/A 4544626SN/A /** The average latency of an MSHR miss, per command and thread. */ 4554626SN/A Stats::Formula avgMshrMissLatency[MemCmd::NUM_MEM_CMDS]; 4564626SN/A /** The average latency of a demand MSHR miss. */ 4574626SN/A Stats::Formula demandAvgMshrMissLatency; 4584626SN/A /** The average overall latency of an MSHR miss. */ 4594626SN/A Stats::Formula overallAvgMshrMissLatency; 4604626SN/A 4614626SN/A /** The average latency of an MSHR miss, per command and thread. */ 4624626SN/A Stats::Formula avgMshrUncacheableLatency[MemCmd::NUM_MEM_CMDS]; 4634626SN/A /** The average overall latency of an MSHR miss. */ 4644626SN/A Stats::Formula overallAvgMshrUncacheableLatency; 4654626SN/A 4664626SN/A /** The number of times a thread hit its MSHR cap. */ 4675999Snate@binkert.org Stats::Vector mshr_cap_events; 4684626SN/A /** The number of times software prefetches caused the MSHR to block. */ 4695999Snate@binkert.org Stats::Vector soft_prefetch_mshr_full; 4704626SN/A 4715999Snate@binkert.org Stats::Scalar mshr_no_allocate_misses; 4724626SN/A 4732810SN/A /** 4742810SN/A * @} 4752810SN/A */ 4762810SN/A 4772810SN/A /** 4782810SN/A * Register stats for this object. 4792810SN/A */ 4802810SN/A virtual void regStats(); 4812810SN/A 4822810SN/A public: 4835034SN/A typedef BaseCacheParams Params; 4845034SN/A BaseCache(const Params *p); 4855034SN/A ~BaseCache() {} 4863606SN/A 4872858SN/A virtual void init(); 4882858SN/A 4899294Sandreas.hansson@arm.com virtual BaseMasterPort &getMasterPort(const std::string &if_name, 4909294Sandreas.hansson@arm.com PortID idx = InvalidPortID); 4919294Sandreas.hansson@arm.com virtual BaseSlavePort &getSlavePort(const std::string &if_name, 4929294Sandreas.hansson@arm.com PortID idx = InvalidPortID); 4938922Swilliam.wang@arm.com 4942810SN/A /** 4952810SN/A * Query block size of a cache. 4962810SN/A * @return The block size 4972810SN/A */ 4986227Snate@binkert.org unsigned 4996227Snate@binkert.org getBlockSize() const 5002810SN/A { 5012810SN/A return blkSize; 5022810SN/A } 5032810SN/A 5044626SN/A 5056666Ssteve.reinhardt@amd.com Addr blockAlign(Addr addr) const { return (addr & ~(Addr(blkSize - 1))); } 5064626SN/A 5074626SN/A 5088883SAli.Saidi@ARM.com const AddrRangeList &getAddrRanges() const { return addrRanges; } 5096122SSteve.Reinhardt@amd.com 5104628SN/A MSHR *allocateMissBuffer(PacketPtr pkt, Tick time, bool requestBus) 5114628SN/A { 5124628SN/A return allocateBufferInternal(&mshrQueue, 5134628SN/A blockAlign(pkt->getAddr()), blkSize, 5144628SN/A pkt, time, requestBus); 5154628SN/A } 5164628SN/A 5174902SN/A MSHR *allocateWriteBuffer(PacketPtr pkt, Tick time, bool requestBus) 5184628SN/A { 5194902SN/A assert(pkt->isWrite() && !pkt->isRead()); 5204902SN/A return allocateBufferInternal(&writeBuffer, 52110764Sandreas.hansson@arm.com blockAlign(pkt->getAddr()), blkSize, 5224628SN/A pkt, time, requestBus); 5234628SN/A } 5244628SN/A 5252810SN/A /** 5262810SN/A * Returns true if the cache is blocked for accesses. 5272810SN/A */ 5289529Sandreas.hansson@arm.com bool isBlocked() const 5292810SN/A { 5302810SN/A return blocked != 0; 5312810SN/A } 5322810SN/A 5332810SN/A /** 5342810SN/A * Marks the access path of the cache as blocked for the given cause. This 5352810SN/A * also sets the blocked flag in the slave interface. 5362810SN/A * @param cause The reason for the cache blocking. 5372810SN/A */ 5382810SN/A void setBlocked(BlockedCause cause) 5392810SN/A { 5402810SN/A uint8_t flag = 1 << cause; 5412810SN/A if (blocked == 0) { 5422810SN/A blocked_causes[cause]++; 5439288Sandreas.hansson@arm.com blockedCycle = curCycle(); 5444630SN/A cpuSidePort->setBlocked(); 5452810SN/A } 5464630SN/A blocked |= flag; 5474630SN/A DPRINTF(Cache,"Blocking for cause %d, mask=%d\n", cause, blocked); 5482810SN/A } 5492810SN/A 5502810SN/A /** 5512810SN/A * Marks the cache as unblocked for the given cause. This also clears the 5522810SN/A * blocked flags in the appropriate interfaces. 5532810SN/A * @param cause The newly unblocked cause. 5542810SN/A * @warning Calling this function can cause a blocked request on the bus to 5552810SN/A * access the cache. The cache must be in a state to handle that request. 5562810SN/A */ 5572810SN/A void clearBlocked(BlockedCause cause) 5582810SN/A { 5592810SN/A uint8_t flag = 1 << cause; 5604630SN/A blocked &= ~flag; 5614630SN/A DPRINTF(Cache,"Unblocking for cause %d, mask=%d\n", cause, blocked); 5624630SN/A if (blocked == 0) { 5639288Sandreas.hansson@arm.com blocked_cycles[cause] += curCycle() - blockedCycle; 5644630SN/A cpuSidePort->clearBlocked(); 5652810SN/A } 5662810SN/A } 5672810SN/A 5682810SN/A /** 5692810SN/A * Request the master bus for the given cause and time. 5702810SN/A * @param cause The reason for the request. 5712810SN/A * @param time The time to make the request. 5722810SN/A */ 5734458SN/A void requestMemSideBus(RequestCause cause, Tick time) 5742810SN/A { 5754458SN/A memSidePort->requestBus(cause, time); 5762810SN/A } 5772810SN/A 5782810SN/A /** 5792810SN/A * Clear the master bus request for the given cause. 5802810SN/A * @param cause The request reason to clear. 5812810SN/A */ 5824458SN/A void deassertMemSideBusRequest(RequestCause cause) 5832810SN/A { 5845875Ssteve.reinhardt@amd.com // Obsolete... we no longer signal bus requests explicitly so 5855875Ssteve.reinhardt@amd.com // we can't deassert them. Leaving this in as a no-op since 5865875Ssteve.reinhardt@amd.com // the prefetcher calls it to indicate that it no longer wants 5875875Ssteve.reinhardt@amd.com // to request a prefetch, and someday that might be 5885875Ssteve.reinhardt@amd.com // interesting again. 5892811SN/A } 5903503SN/A 5919342SAndreas.Sandberg@arm.com virtual unsigned int drain(DrainManager *dm); 5923503SN/A 59310028SGiacomo.Gabrielli@arm.com virtual bool inCache(Addr addr, bool is_secure) const = 0; 5944626SN/A 59510028SGiacomo.Gabrielli@arm.com virtual bool inMissQueue(Addr addr, bool is_secure) const = 0; 5964626SN/A 5978833Sdam.sunwoo@arm.com void incMissCount(PacketPtr pkt) 5983503SN/A { 5998833Sdam.sunwoo@arm.com assert(pkt->req->masterId() < system->maxMasters()); 6008833Sdam.sunwoo@arm.com misses[pkt->cmdToIndex()][pkt->req->masterId()]++; 60110020Smatt.horsnell@ARM.com pkt->req->incAccessDepth(); 6024626SN/A if (missCount) { 6034626SN/A --missCount; 6044626SN/A if (missCount == 0) 6054626SN/A exitSimLoop("A cache reached the maximum miss count"); 6063503SN/A } 6073503SN/A } 6088833Sdam.sunwoo@arm.com void incHitCount(PacketPtr pkt) 6096978SLisa.Hsu@amd.com { 6108833Sdam.sunwoo@arm.com assert(pkt->req->masterId() < system->maxMasters()); 6118833Sdam.sunwoo@arm.com hits[pkt->cmdToIndex()][pkt->req->masterId()]++; 6126978SLisa.Hsu@amd.com 6136978SLisa.Hsu@amd.com } 6143503SN/A 6152810SN/A}; 6162810SN/A 6172810SN/A#endif //__BASE_CACHE_HH__ 618