base.cc revision 13416
12810SN/A/* 212724Snikos.nikoleris@arm.com * Copyright (c) 2012-2013, 2018 ARM Limited 38856Sandreas.hansson@arm.com * All rights reserved. 48856Sandreas.hansson@arm.com * 58856Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall 68856Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual 78856Sandreas.hansson@arm.com * property including but not limited to intellectual property relating 88856Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software 98856Sandreas.hansson@arm.com * licensed hereunder. You may use the software subject to the license 108856Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated 118856Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software, 128856Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form. 138856Sandreas.hansson@arm.com * 142810SN/A * Copyright (c) 2003-2005 The Regents of The University of Michigan 152810SN/A * All rights reserved. 162810SN/A * 172810SN/A * Redistribution and use in source and binary forms, with or without 182810SN/A * modification, are permitted provided that the following conditions are 192810SN/A * met: redistributions of source code must retain the above copyright 202810SN/A * notice, this list of conditions and the following disclaimer; 212810SN/A * redistributions in binary form must reproduce the above copyright 222810SN/A * notice, this list of conditions and the following disclaimer in the 232810SN/A * documentation and/or other materials provided with the distribution; 242810SN/A * neither the name of the copyright holders nor the names of its 252810SN/A * contributors may be used to endorse or promote products derived from 262810SN/A * this software without specific prior written permission. 272810SN/A * 282810SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292810SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302810SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312810SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322810SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332810SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342810SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352810SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362810SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372810SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382810SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392810SN/A * 402810SN/A * Authors: Erik Hallnor 4112724Snikos.nikoleris@arm.com * Nikos Nikoleris 422810SN/A */ 432810SN/A 442810SN/A/** 452810SN/A * @file 462810SN/A * Definition of BaseCache functions. 472810SN/A */ 482810SN/A 4911486Snikos.nikoleris@arm.com#include "mem/cache/base.hh" 5011486Snikos.nikoleris@arm.com 5112724Snikos.nikoleris@arm.com#include "base/compiler.hh" 5212724Snikos.nikoleris@arm.com#include "base/logging.hh" 538232Snate@binkert.org#include "debug/Cache.hh" 5412724Snikos.nikoleris@arm.com#include "debug/CachePort.hh" 5513222Sodanrc@yahoo.com.br#include "debug/CacheRepl.hh" 5612724Snikos.nikoleris@arm.com#include "debug/CacheVerbose.hh" 5711486Snikos.nikoleris@arm.com#include "mem/cache/mshr.hh" 5812724Snikos.nikoleris@arm.com#include "mem/cache/prefetch/base.hh" 5912724Snikos.nikoleris@arm.com#include "mem/cache/queue_entry.hh" 6012724Snikos.nikoleris@arm.com#include "params/BaseCache.hh" 6113352Snikos.nikoleris@arm.com#include "params/WriteAllocator.hh" 6212724Snikos.nikoleris@arm.com#include "sim/core.hh" 6312724Snikos.nikoleris@arm.com 6412724Snikos.nikoleris@arm.comclass BaseMasterPort; 6512724Snikos.nikoleris@arm.comclass BaseSlavePort; 662810SN/A 672810SN/Ausing namespace std; 682810SN/A 698856Sandreas.hansson@arm.comBaseCache::CacheSlavePort::CacheSlavePort(const std::string &_name, 708856Sandreas.hansson@arm.com BaseCache *_cache, 718856Sandreas.hansson@arm.com const std::string &_label) 728922Swilliam.wang@arm.com : QueuedSlavePort(_name, _cache, queue), queue(*_cache, *this, _label), 7312084Sspwilson2@wisc.edu blocked(false), mustSendRetry(false), 7412084Sspwilson2@wisc.edu sendRetryEvent([this]{ processSendRetry(); }, _name) 758856Sandreas.hansson@arm.com{ 768856Sandreas.hansson@arm.com} 774475SN/A 7811053Sandreas.hansson@arm.comBaseCache::BaseCache(const BaseCacheParams *p, unsigned blk_size) 795034SN/A : MemObject(p), 8012724Snikos.nikoleris@arm.com cpuSidePort (p->name + ".cpu_side", this, "CpuSidePort"), 8112724Snikos.nikoleris@arm.com memSidePort(p->name + ".mem_side", this, "MemSidePort"), 8211377Sandreas.hansson@arm.com mshrQueue("MSHRs", p->mshrs, 0, p->demand_mshr_reserve), // see below 8311377Sandreas.hansson@arm.com writeBuffer("write buffer", p->write_buffers, p->mshrs), // see below 8412724Snikos.nikoleris@arm.com tags(p->tags), 8512724Snikos.nikoleris@arm.com prefetcher(p->prefetcher), 8613352Snikos.nikoleris@arm.com writeAllocator(p->write_allocator), 8712724Snikos.nikoleris@arm.com writebackClean(p->writeback_clean), 8812724Snikos.nikoleris@arm.com tempBlockWriteback(nullptr), 8912724Snikos.nikoleris@arm.com writebackTempBlockAtomicEvent([this]{ writebackTempBlockAtomic(); }, 9012724Snikos.nikoleris@arm.com name(), false, 9112724Snikos.nikoleris@arm.com EventBase::Delayed_Writeback_Pri), 9211053Sandreas.hansson@arm.com blkSize(blk_size), 9311722Ssophiane.senni@gmail.com lookupLatency(p->tag_latency), 9411722Ssophiane.senni@gmail.com dataLatency(p->data_latency), 9511722Ssophiane.senni@gmail.com forwardLatency(p->tag_latency), 9611722Ssophiane.senni@gmail.com fillLatency(p->data_latency), 979263Smrinmoy.ghosh@arm.com responseLatency(p->response_latency), 985034SN/A numTarget(p->tgts_per_mshr), 9911331Sandreas.hansson@arm.com forwardSnoops(true), 10012724Snikos.nikoleris@arm.com clusivity(p->clusivity), 10110884Sandreas.hansson@arm.com isReadOnly(p->is_read_only), 1024626SN/A blocked(0), 10310360Sandreas.hansson@arm.com order(0), 10411484Snikos.nikoleris@arm.com noTargetMSHR(nullptr), 1055034SN/A missCount(p->max_miss_count), 1068883SAli.Saidi@ARM.com addrRanges(p->addr_ranges.begin(), p->addr_ranges.end()), 1078833Sdam.sunwoo@arm.com system(p->system) 1084458SN/A{ 10911377Sandreas.hansson@arm.com // the MSHR queue has no reserve entries as we check the MSHR 11011377Sandreas.hansson@arm.com // queue on every single allocation, whereas the write queue has 11111377Sandreas.hansson@arm.com // as many reserve entries as we have MSHRs, since every MSHR may 11211377Sandreas.hansson@arm.com // eventually require a writeback, and we do not check the write 11311377Sandreas.hansson@arm.com // buffer before committing to an MSHR 11411377Sandreas.hansson@arm.com 11511331Sandreas.hansson@arm.com // forward snoops is overridden in init() once we can query 11611331Sandreas.hansson@arm.com // whether the connected master is actually snooping or not 11712724Snikos.nikoleris@arm.com 11812843Srmk35@cl.cam.ac.uk tempBlock = new TempCacheBlk(blkSize); 11912724Snikos.nikoleris@arm.com 12013378Sgabeblack@google.com tags->tagsInit(this); 12112724Snikos.nikoleris@arm.com if (prefetcher) 12212724Snikos.nikoleris@arm.com prefetcher->setCache(this); 12312724Snikos.nikoleris@arm.com} 12412724Snikos.nikoleris@arm.com 12512724Snikos.nikoleris@arm.comBaseCache::~BaseCache() 12612724Snikos.nikoleris@arm.com{ 12712724Snikos.nikoleris@arm.com delete tempBlock; 1282810SN/A} 1292810SN/A 1303013SN/Avoid 1318856Sandreas.hansson@arm.comBaseCache::CacheSlavePort::setBlocked() 1322810SN/A{ 1333013SN/A assert(!blocked); 13410714Sandreas.hansson@arm.com DPRINTF(CachePort, "Port is blocking new requests\n"); 1352810SN/A blocked = true; 1369614Srene.dejong@arm.com // if we already scheduled a retry in this cycle, but it has not yet 1379614Srene.dejong@arm.com // happened, cancel it 1389614Srene.dejong@arm.com if (sendRetryEvent.scheduled()) { 13910345SCurtis.Dunham@arm.com owner.deschedule(sendRetryEvent); 14010714Sandreas.hansson@arm.com DPRINTF(CachePort, "Port descheduled retry\n"); 14110345SCurtis.Dunham@arm.com mustSendRetry = true; 1429614Srene.dejong@arm.com } 1432810SN/A} 1442810SN/A 1452810SN/Avoid 1468856Sandreas.hansson@arm.comBaseCache::CacheSlavePort::clearBlocked() 1472810SN/A{ 1483013SN/A assert(blocked); 14910714Sandreas.hansson@arm.com DPRINTF(CachePort, "Port is accepting new requests\n"); 1503013SN/A blocked = false; 1518856Sandreas.hansson@arm.com if (mustSendRetry) { 15210714Sandreas.hansson@arm.com // @TODO: need to find a better time (next cycle?) 1538922Swilliam.wang@arm.com owner.schedule(sendRetryEvent, curTick() + 1); 1542897SN/A } 1552810SN/A} 1562810SN/A 15710344Sandreas.hansson@arm.comvoid 15810344Sandreas.hansson@arm.comBaseCache::CacheSlavePort::processSendRetry() 15910344Sandreas.hansson@arm.com{ 16010714Sandreas.hansson@arm.com DPRINTF(CachePort, "Port is sending retry\n"); 16110344Sandreas.hansson@arm.com 16210344Sandreas.hansson@arm.com // reset the flag and call retry 16310344Sandreas.hansson@arm.com mustSendRetry = false; 16410713Sandreas.hansson@arm.com sendRetryReq(); 16510344Sandreas.hansson@arm.com} 1662844SN/A 16712730Sodanrc@yahoo.com.brAddr 16812730Sodanrc@yahoo.com.brBaseCache::regenerateBlkAddr(CacheBlk* blk) 16912730Sodanrc@yahoo.com.br{ 17012730Sodanrc@yahoo.com.br if (blk != tempBlock) { 17112730Sodanrc@yahoo.com.br return tags->regenerateBlkAddr(blk); 17212730Sodanrc@yahoo.com.br } else { 17312730Sodanrc@yahoo.com.br return tempBlock->getAddr(); 17412730Sodanrc@yahoo.com.br } 17512730Sodanrc@yahoo.com.br} 17612730Sodanrc@yahoo.com.br 1772810SN/Avoid 1782858SN/ABaseCache::init() 1792858SN/A{ 18012724Snikos.nikoleris@arm.com if (!cpuSidePort.isConnected() || !memSidePort.isConnected()) 1818922Swilliam.wang@arm.com fatal("Cache ports on %s are not connected\n", name()); 18212724Snikos.nikoleris@arm.com cpuSidePort.sendRangeChange(); 18312724Snikos.nikoleris@arm.com forwardSnoops = cpuSidePort.isSnooping(); 1842858SN/A} 1852858SN/A 1869294Sandreas.hansson@arm.comBaseMasterPort & 1879294Sandreas.hansson@arm.comBaseCache::getMasterPort(const std::string &if_name, PortID idx) 1888922Swilliam.wang@arm.com{ 1898922Swilliam.wang@arm.com if (if_name == "mem_side") { 19012724Snikos.nikoleris@arm.com return memSidePort; 1918922Swilliam.wang@arm.com } else { 1928922Swilliam.wang@arm.com return MemObject::getMasterPort(if_name, idx); 1938922Swilliam.wang@arm.com } 1948922Swilliam.wang@arm.com} 1958922Swilliam.wang@arm.com 1969294Sandreas.hansson@arm.comBaseSlavePort & 1979294Sandreas.hansson@arm.comBaseCache::getSlavePort(const std::string &if_name, PortID idx) 1988922Swilliam.wang@arm.com{ 1998922Swilliam.wang@arm.com if (if_name == "cpu_side") { 20012724Snikos.nikoleris@arm.com return cpuSidePort; 2018922Swilliam.wang@arm.com } else { 2028922Swilliam.wang@arm.com return MemObject::getSlavePort(if_name, idx); 2038922Swilliam.wang@arm.com } 2048922Swilliam.wang@arm.com} 2054628SN/A 20610821Sandreas.hansson@arm.combool 20710821Sandreas.hansson@arm.comBaseCache::inRange(Addr addr) const 20810821Sandreas.hansson@arm.com{ 20910821Sandreas.hansson@arm.com for (const auto& r : addrRanges) { 21010821Sandreas.hansson@arm.com if (r.contains(addr)) { 21110821Sandreas.hansson@arm.com return true; 21210821Sandreas.hansson@arm.com } 21310821Sandreas.hansson@arm.com } 21410821Sandreas.hansson@arm.com return false; 21510821Sandreas.hansson@arm.com} 21610821Sandreas.hansson@arm.com 2172858SN/Avoid 21812724Snikos.nikoleris@arm.comBaseCache::handleTimingReqHit(PacketPtr pkt, CacheBlk *blk, Tick request_time) 21912724Snikos.nikoleris@arm.com{ 22012724Snikos.nikoleris@arm.com if (pkt->needsResponse()) { 22112724Snikos.nikoleris@arm.com pkt->makeTimingResponse(); 22212724Snikos.nikoleris@arm.com // @todo: Make someone pay for this 22312724Snikos.nikoleris@arm.com pkt->headerDelay = pkt->payloadDelay = 0; 22412724Snikos.nikoleris@arm.com 22512724Snikos.nikoleris@arm.com // In this case we are considering request_time that takes 22612724Snikos.nikoleris@arm.com // into account the delay of the xbar, if any, and just 22712724Snikos.nikoleris@arm.com // lat, neglecting responseLatency, modelling hit latency 22812724Snikos.nikoleris@arm.com // just as lookupLatency or or the value of lat overriden 22912724Snikos.nikoleris@arm.com // by access(), that calls accessBlock() function. 23012724Snikos.nikoleris@arm.com cpuSidePort.schedTimingResp(pkt, request_time, true); 23112724Snikos.nikoleris@arm.com } else { 23212724Snikos.nikoleris@arm.com DPRINTF(Cache, "%s satisfied %s, no response needed\n", __func__, 23312724Snikos.nikoleris@arm.com pkt->print()); 23412724Snikos.nikoleris@arm.com 23512724Snikos.nikoleris@arm.com // queue the packet for deletion, as the sending cache is 23612724Snikos.nikoleris@arm.com // still relying on it; if the block is found in access(), 23712724Snikos.nikoleris@arm.com // CleanEvict and Writeback messages will be deleted 23812724Snikos.nikoleris@arm.com // here as well 23912724Snikos.nikoleris@arm.com pendingDelete.reset(pkt); 24012724Snikos.nikoleris@arm.com } 24112724Snikos.nikoleris@arm.com} 24212724Snikos.nikoleris@arm.com 24312724Snikos.nikoleris@arm.comvoid 24412724Snikos.nikoleris@arm.comBaseCache::handleTimingReqMiss(PacketPtr pkt, MSHR *mshr, CacheBlk *blk, 24512724Snikos.nikoleris@arm.com Tick forward_time, Tick request_time) 24612724Snikos.nikoleris@arm.com{ 24713352Snikos.nikoleris@arm.com if (writeAllocator && 24813352Snikos.nikoleris@arm.com pkt && pkt->isWrite() && !pkt->req->isUncacheable()) { 24913352Snikos.nikoleris@arm.com writeAllocator->updateMode(pkt->getAddr(), pkt->getSize(), 25013352Snikos.nikoleris@arm.com pkt->getBlockAddr(blkSize)); 25113352Snikos.nikoleris@arm.com } 25213352Snikos.nikoleris@arm.com 25312724Snikos.nikoleris@arm.com if (mshr) { 25412724Snikos.nikoleris@arm.com /// MSHR hit 25512724Snikos.nikoleris@arm.com /// @note writebacks will be checked in getNextMSHR() 25612724Snikos.nikoleris@arm.com /// for any conflicting requests to the same block 25712724Snikos.nikoleris@arm.com 25812724Snikos.nikoleris@arm.com //@todo remove hw_pf here 25912724Snikos.nikoleris@arm.com 26012724Snikos.nikoleris@arm.com // Coalesce unless it was a software prefetch (see above). 26112724Snikos.nikoleris@arm.com if (pkt) { 26212724Snikos.nikoleris@arm.com assert(!pkt->isWriteback()); 26312724Snikos.nikoleris@arm.com // CleanEvicts corresponding to blocks which have 26412724Snikos.nikoleris@arm.com // outstanding requests in MSHRs are simply sunk here 26512724Snikos.nikoleris@arm.com if (pkt->cmd == MemCmd::CleanEvict) { 26612724Snikos.nikoleris@arm.com pendingDelete.reset(pkt); 26712724Snikos.nikoleris@arm.com } else if (pkt->cmd == MemCmd::WriteClean) { 26812724Snikos.nikoleris@arm.com // A WriteClean should never coalesce with any 26912724Snikos.nikoleris@arm.com // outstanding cache maintenance requests. 27012724Snikos.nikoleris@arm.com 27112724Snikos.nikoleris@arm.com // We use forward_time here because there is an 27212724Snikos.nikoleris@arm.com // uncached memory write, forwarded to WriteBuffer. 27312724Snikos.nikoleris@arm.com allocateWriteBuffer(pkt, forward_time); 27412724Snikos.nikoleris@arm.com } else { 27512724Snikos.nikoleris@arm.com DPRINTF(Cache, "%s coalescing MSHR for %s\n", __func__, 27612724Snikos.nikoleris@arm.com pkt->print()); 27712724Snikos.nikoleris@arm.com 27812724Snikos.nikoleris@arm.com assert(pkt->req->masterId() < system->maxMasters()); 27912724Snikos.nikoleris@arm.com mshr_hits[pkt->cmdToIndex()][pkt->req->masterId()]++; 28012724Snikos.nikoleris@arm.com 28112724Snikos.nikoleris@arm.com // We use forward_time here because it is the same 28212724Snikos.nikoleris@arm.com // considering new targets. We have multiple 28312724Snikos.nikoleris@arm.com // requests for the same address here. It 28412724Snikos.nikoleris@arm.com // specifies the latency to allocate an internal 28512724Snikos.nikoleris@arm.com // buffer and to schedule an event to the queued 28612724Snikos.nikoleris@arm.com // port and also takes into account the additional 28712724Snikos.nikoleris@arm.com // delay of the xbar. 28812724Snikos.nikoleris@arm.com mshr->allocateTarget(pkt, forward_time, order++, 28912724Snikos.nikoleris@arm.com allocOnFill(pkt->cmd)); 29012724Snikos.nikoleris@arm.com if (mshr->getNumTargets() == numTarget) { 29112724Snikos.nikoleris@arm.com noTargetMSHR = mshr; 29212724Snikos.nikoleris@arm.com setBlocked(Blocked_NoTargets); 29312724Snikos.nikoleris@arm.com // need to be careful with this... if this mshr isn't 29412724Snikos.nikoleris@arm.com // ready yet (i.e. time > curTick()), we don't want to 29512724Snikos.nikoleris@arm.com // move it ahead of mshrs that are ready 29612724Snikos.nikoleris@arm.com // mshrQueue.moveToFront(mshr); 29712724Snikos.nikoleris@arm.com } 29812724Snikos.nikoleris@arm.com } 29912724Snikos.nikoleris@arm.com } 30012724Snikos.nikoleris@arm.com } else { 30112724Snikos.nikoleris@arm.com // no MSHR 30212724Snikos.nikoleris@arm.com assert(pkt->req->masterId() < system->maxMasters()); 30312724Snikos.nikoleris@arm.com mshr_misses[pkt->cmdToIndex()][pkt->req->masterId()]++; 30412724Snikos.nikoleris@arm.com 30512724Snikos.nikoleris@arm.com if (pkt->isEviction() || pkt->cmd == MemCmd::WriteClean) { 30612724Snikos.nikoleris@arm.com // We use forward_time here because there is an 30712724Snikos.nikoleris@arm.com // writeback or writeclean, forwarded to WriteBuffer. 30812724Snikos.nikoleris@arm.com allocateWriteBuffer(pkt, forward_time); 30912724Snikos.nikoleris@arm.com } else { 31012724Snikos.nikoleris@arm.com if (blk && blk->isValid()) { 31112724Snikos.nikoleris@arm.com // If we have a write miss to a valid block, we 31212724Snikos.nikoleris@arm.com // need to mark the block non-readable. Otherwise 31312724Snikos.nikoleris@arm.com // if we allow reads while there's an outstanding 31412724Snikos.nikoleris@arm.com // write miss, the read could return stale data 31512724Snikos.nikoleris@arm.com // out of the cache block... a more aggressive 31612724Snikos.nikoleris@arm.com // system could detect the overlap (if any) and 31712724Snikos.nikoleris@arm.com // forward data out of the MSHRs, but we don't do 31812724Snikos.nikoleris@arm.com // that yet. Note that we do need to leave the 31912724Snikos.nikoleris@arm.com // block valid so that it stays in the cache, in 32012724Snikos.nikoleris@arm.com // case we get an upgrade response (and hence no 32112724Snikos.nikoleris@arm.com // new data) when the write miss completes. 32212724Snikos.nikoleris@arm.com // As long as CPUs do proper store/load forwarding 32312724Snikos.nikoleris@arm.com // internally, and have a sufficiently weak memory 32412724Snikos.nikoleris@arm.com // model, this is probably unnecessary, but at some 32512724Snikos.nikoleris@arm.com // point it must have seemed like we needed it... 32612724Snikos.nikoleris@arm.com assert((pkt->needsWritable() && !blk->isWritable()) || 32712724Snikos.nikoleris@arm.com pkt->req->isCacheMaintenance()); 32812724Snikos.nikoleris@arm.com blk->status &= ~BlkReadable; 32912724Snikos.nikoleris@arm.com } 33012724Snikos.nikoleris@arm.com // Here we are using forward_time, modelling the latency of 33112724Snikos.nikoleris@arm.com // a miss (outbound) just as forwardLatency, neglecting the 33212724Snikos.nikoleris@arm.com // lookupLatency component. 33312724Snikos.nikoleris@arm.com allocateMissBuffer(pkt, forward_time); 33412724Snikos.nikoleris@arm.com } 33512724Snikos.nikoleris@arm.com } 33612724Snikos.nikoleris@arm.com} 33712724Snikos.nikoleris@arm.com 33812724Snikos.nikoleris@arm.comvoid 33912724Snikos.nikoleris@arm.comBaseCache::recvTimingReq(PacketPtr pkt) 34012724Snikos.nikoleris@arm.com{ 34112724Snikos.nikoleris@arm.com // anything that is merely forwarded pays for the forward latency and 34212724Snikos.nikoleris@arm.com // the delay provided by the crossbar 34312724Snikos.nikoleris@arm.com Tick forward_time = clockEdge(forwardLatency) + pkt->headerDelay; 34412724Snikos.nikoleris@arm.com 34512724Snikos.nikoleris@arm.com // We use lookupLatency here because it is used to specify the latency 34612724Snikos.nikoleris@arm.com // to access. 34712724Snikos.nikoleris@arm.com Cycles lat = lookupLatency; 34812724Snikos.nikoleris@arm.com CacheBlk *blk = nullptr; 34912724Snikos.nikoleris@arm.com bool satisfied = false; 35012724Snikos.nikoleris@arm.com { 35112724Snikos.nikoleris@arm.com PacketList writebacks; 35212724Snikos.nikoleris@arm.com // Note that lat is passed by reference here. The function 35312724Snikos.nikoleris@arm.com // access() calls accessBlock() which can modify lat value. 35412724Snikos.nikoleris@arm.com satisfied = access(pkt, blk, lat, writebacks); 35512724Snikos.nikoleris@arm.com 35612724Snikos.nikoleris@arm.com // copy writebacks to write buffer here to ensure they logically 35712820Srmk35@cl.cam.ac.uk // precede anything happening below 35812724Snikos.nikoleris@arm.com doWritebacks(writebacks, forward_time); 35912724Snikos.nikoleris@arm.com } 36012724Snikos.nikoleris@arm.com 36112724Snikos.nikoleris@arm.com // Here we charge the headerDelay that takes into account the latencies 36212724Snikos.nikoleris@arm.com // of the bus, if the packet comes from it. 36312724Snikos.nikoleris@arm.com // The latency charged it is just lat that is the value of lookupLatency 36412724Snikos.nikoleris@arm.com // modified by access() function, or if not just lookupLatency. 36512724Snikos.nikoleris@arm.com // In case of a hit we are neglecting response latency. 36612724Snikos.nikoleris@arm.com // In case of a miss we are neglecting forward latency. 36712724Snikos.nikoleris@arm.com Tick request_time = clockEdge(lat) + pkt->headerDelay; 36812724Snikos.nikoleris@arm.com // Here we reset the timing of the packet. 36912724Snikos.nikoleris@arm.com pkt->headerDelay = pkt->payloadDelay = 0; 37012724Snikos.nikoleris@arm.com 37112724Snikos.nikoleris@arm.com if (satisfied) { 37213416Sjavier.bueno@metempsy.com // notify before anything else as later handleTimingReqHit might turn 37313416Sjavier.bueno@metempsy.com // the packet in a response 37413416Sjavier.bueno@metempsy.com ppHit->notify(pkt); 37512724Snikos.nikoleris@arm.com 37613416Sjavier.bueno@metempsy.com if (prefetcher && blk && blk->wasPrefetched()) { 37713416Sjavier.bueno@metempsy.com blk->status &= ~BlkHWPrefetched; 37812724Snikos.nikoleris@arm.com } 37912724Snikos.nikoleris@arm.com 38012724Snikos.nikoleris@arm.com handleTimingReqHit(pkt, blk, request_time); 38112724Snikos.nikoleris@arm.com } else { 38212724Snikos.nikoleris@arm.com handleTimingReqMiss(pkt, blk, forward_time, request_time); 38312724Snikos.nikoleris@arm.com 38413416Sjavier.bueno@metempsy.com ppMiss->notify(pkt); 38512724Snikos.nikoleris@arm.com } 38612724Snikos.nikoleris@arm.com 38713416Sjavier.bueno@metempsy.com if (prefetcher) { 38813416Sjavier.bueno@metempsy.com // track time of availability of next prefetch, if any 38913416Sjavier.bueno@metempsy.com Tick next_pf_time = prefetcher->nextPrefetchReadyTime(); 39013416Sjavier.bueno@metempsy.com if (next_pf_time != MaxTick) { 39113416Sjavier.bueno@metempsy.com schedMemSideSendEvent(next_pf_time); 39213416Sjavier.bueno@metempsy.com } 39312724Snikos.nikoleris@arm.com } 39412724Snikos.nikoleris@arm.com} 39512724Snikos.nikoleris@arm.com 39612724Snikos.nikoleris@arm.comvoid 39712724Snikos.nikoleris@arm.comBaseCache::handleUncacheableWriteResp(PacketPtr pkt) 39812724Snikos.nikoleris@arm.com{ 39912724Snikos.nikoleris@arm.com Tick completion_time = clockEdge(responseLatency) + 40012724Snikos.nikoleris@arm.com pkt->headerDelay + pkt->payloadDelay; 40112724Snikos.nikoleris@arm.com 40212724Snikos.nikoleris@arm.com // Reset the bus additional time as it is now accounted for 40312724Snikos.nikoleris@arm.com pkt->headerDelay = pkt->payloadDelay = 0; 40412724Snikos.nikoleris@arm.com 40512724Snikos.nikoleris@arm.com cpuSidePort.schedTimingResp(pkt, completion_time, true); 40612724Snikos.nikoleris@arm.com} 40712724Snikos.nikoleris@arm.com 40812724Snikos.nikoleris@arm.comvoid 40912724Snikos.nikoleris@arm.comBaseCache::recvTimingResp(PacketPtr pkt) 41012724Snikos.nikoleris@arm.com{ 41112724Snikos.nikoleris@arm.com assert(pkt->isResponse()); 41212724Snikos.nikoleris@arm.com 41312724Snikos.nikoleris@arm.com // all header delay should be paid for by the crossbar, unless 41412724Snikos.nikoleris@arm.com // this is a prefetch response from above 41512724Snikos.nikoleris@arm.com panic_if(pkt->headerDelay != 0 && pkt->cmd != MemCmd::HardPFResp, 41612724Snikos.nikoleris@arm.com "%s saw a non-zero packet delay\n", name()); 41712724Snikos.nikoleris@arm.com 41812724Snikos.nikoleris@arm.com const bool is_error = pkt->isError(); 41912724Snikos.nikoleris@arm.com 42012724Snikos.nikoleris@arm.com if (is_error) { 42112724Snikos.nikoleris@arm.com DPRINTF(Cache, "%s: Cache received %s with error\n", __func__, 42212724Snikos.nikoleris@arm.com pkt->print()); 42312724Snikos.nikoleris@arm.com } 42412724Snikos.nikoleris@arm.com 42512724Snikos.nikoleris@arm.com DPRINTF(Cache, "%s: Handling response %s\n", __func__, 42612724Snikos.nikoleris@arm.com pkt->print()); 42712724Snikos.nikoleris@arm.com 42812724Snikos.nikoleris@arm.com // if this is a write, we should be looking at an uncacheable 42912724Snikos.nikoleris@arm.com // write 43012724Snikos.nikoleris@arm.com if (pkt->isWrite()) { 43112724Snikos.nikoleris@arm.com assert(pkt->req->isUncacheable()); 43212724Snikos.nikoleris@arm.com handleUncacheableWriteResp(pkt); 43312724Snikos.nikoleris@arm.com return; 43412724Snikos.nikoleris@arm.com } 43512724Snikos.nikoleris@arm.com 43612724Snikos.nikoleris@arm.com // we have dealt with any (uncacheable) writes above, from here on 43712724Snikos.nikoleris@arm.com // we know we are dealing with an MSHR due to a miss or a prefetch 43812724Snikos.nikoleris@arm.com MSHR *mshr = dynamic_cast<MSHR*>(pkt->popSenderState()); 43912724Snikos.nikoleris@arm.com assert(mshr); 44012724Snikos.nikoleris@arm.com 44112724Snikos.nikoleris@arm.com if (mshr == noTargetMSHR) { 44212724Snikos.nikoleris@arm.com // we always clear at least one target 44312724Snikos.nikoleris@arm.com clearBlocked(Blocked_NoTargets); 44412724Snikos.nikoleris@arm.com noTargetMSHR = nullptr; 44512724Snikos.nikoleris@arm.com } 44612724Snikos.nikoleris@arm.com 44712724Snikos.nikoleris@arm.com // Initial target is used just for stats 44812724Snikos.nikoleris@arm.com MSHR::Target *initial_tgt = mshr->getTarget(); 44912724Snikos.nikoleris@arm.com int stats_cmd_idx = initial_tgt->pkt->cmdToIndex(); 45012724Snikos.nikoleris@arm.com Tick miss_latency = curTick() - initial_tgt->recvTime; 45112724Snikos.nikoleris@arm.com 45212724Snikos.nikoleris@arm.com if (pkt->req->isUncacheable()) { 45312724Snikos.nikoleris@arm.com assert(pkt->req->masterId() < system->maxMasters()); 45412724Snikos.nikoleris@arm.com mshr_uncacheable_lat[stats_cmd_idx][pkt->req->masterId()] += 45512724Snikos.nikoleris@arm.com miss_latency; 45612724Snikos.nikoleris@arm.com } else { 45712724Snikos.nikoleris@arm.com assert(pkt->req->masterId() < system->maxMasters()); 45812724Snikos.nikoleris@arm.com mshr_miss_latency[stats_cmd_idx][pkt->req->masterId()] += 45912724Snikos.nikoleris@arm.com miss_latency; 46012724Snikos.nikoleris@arm.com } 46112724Snikos.nikoleris@arm.com 46212724Snikos.nikoleris@arm.com PacketList writebacks; 46312724Snikos.nikoleris@arm.com 46412724Snikos.nikoleris@arm.com bool is_fill = !mshr->isForward && 46513350Snikos.nikoleris@arm.com (pkt->isRead() || pkt->cmd == MemCmd::UpgradeResp || 46613350Snikos.nikoleris@arm.com mshr->wasWholeLineWrite); 46713350Snikos.nikoleris@arm.com 46813350Snikos.nikoleris@arm.com // make sure that if the mshr was due to a whole line write then 46913350Snikos.nikoleris@arm.com // the response is an invalidation 47013350Snikos.nikoleris@arm.com assert(!mshr->wasWholeLineWrite || pkt->isInvalidate()); 47112724Snikos.nikoleris@arm.com 47212724Snikos.nikoleris@arm.com CacheBlk *blk = tags->findBlock(pkt->getAddr(), pkt->isSecure()); 47312724Snikos.nikoleris@arm.com 47412724Snikos.nikoleris@arm.com if (is_fill && !is_error) { 47512724Snikos.nikoleris@arm.com DPRINTF(Cache, "Block for addr %#llx being updated in Cache\n", 47612724Snikos.nikoleris@arm.com pkt->getAddr()); 47712724Snikos.nikoleris@arm.com 47813352Snikos.nikoleris@arm.com const bool allocate = (writeAllocator && mshr->wasWholeLineWrite) ? 47913352Snikos.nikoleris@arm.com writeAllocator->allocate() : mshr->allocOnFill(); 48013352Snikos.nikoleris@arm.com blk = handleFill(pkt, blk, writebacks, allocate); 48112724Snikos.nikoleris@arm.com assert(blk != nullptr); 48212724Snikos.nikoleris@arm.com } 48312724Snikos.nikoleris@arm.com 48412724Snikos.nikoleris@arm.com if (blk && blk->isValid() && pkt->isClean() && !pkt->isInvalidate()) { 48512724Snikos.nikoleris@arm.com // The block was marked not readable while there was a pending 48612724Snikos.nikoleris@arm.com // cache maintenance operation, restore its flag. 48712724Snikos.nikoleris@arm.com blk->status |= BlkReadable; 48812794Snikos.nikoleris@arm.com 48912794Snikos.nikoleris@arm.com // This was a cache clean operation (without invalidate) 49012794Snikos.nikoleris@arm.com // and we have a copy of the block already. Since there 49112794Snikos.nikoleris@arm.com // is no invalidation, we can promote targets that don't 49212794Snikos.nikoleris@arm.com // require a writable copy 49312794Snikos.nikoleris@arm.com mshr->promoteReadable(); 49412724Snikos.nikoleris@arm.com } 49512724Snikos.nikoleris@arm.com 49612724Snikos.nikoleris@arm.com if (blk && blk->isWritable() && !pkt->req->isCacheInvalidate()) { 49712724Snikos.nikoleris@arm.com // If at this point the referenced block is writable and the 49812724Snikos.nikoleris@arm.com // response is not a cache invalidate, we promote targets that 49912724Snikos.nikoleris@arm.com // were deferred as we couldn't guarrantee a writable copy 50012724Snikos.nikoleris@arm.com mshr->promoteWritable(); 50112724Snikos.nikoleris@arm.com } 50212724Snikos.nikoleris@arm.com 50312724Snikos.nikoleris@arm.com serviceMSHRTargets(mshr, pkt, blk, writebacks); 50412724Snikos.nikoleris@arm.com 50512724Snikos.nikoleris@arm.com if (mshr->promoteDeferredTargets()) { 50612724Snikos.nikoleris@arm.com // avoid later read getting stale data while write miss is 50712724Snikos.nikoleris@arm.com // outstanding.. see comment in timingAccess() 50812724Snikos.nikoleris@arm.com if (blk) { 50912724Snikos.nikoleris@arm.com blk->status &= ~BlkReadable; 51012724Snikos.nikoleris@arm.com } 51112724Snikos.nikoleris@arm.com mshrQueue.markPending(mshr); 51212724Snikos.nikoleris@arm.com schedMemSideSendEvent(clockEdge() + pkt->payloadDelay); 51312724Snikos.nikoleris@arm.com } else { 51412724Snikos.nikoleris@arm.com // while we deallocate an mshr from the queue we still have to 51512724Snikos.nikoleris@arm.com // check the isFull condition before and after as we might 51612724Snikos.nikoleris@arm.com // have been using the reserved entries already 51712724Snikos.nikoleris@arm.com const bool was_full = mshrQueue.isFull(); 51812724Snikos.nikoleris@arm.com mshrQueue.deallocate(mshr); 51912724Snikos.nikoleris@arm.com if (was_full && !mshrQueue.isFull()) { 52012724Snikos.nikoleris@arm.com clearBlocked(Blocked_NoMSHRs); 52112724Snikos.nikoleris@arm.com } 52212724Snikos.nikoleris@arm.com 52312724Snikos.nikoleris@arm.com // Request the bus for a prefetch if this deallocation freed enough 52412724Snikos.nikoleris@arm.com // MSHRs for a prefetch to take place 52512724Snikos.nikoleris@arm.com if (prefetcher && mshrQueue.canPrefetch()) { 52612724Snikos.nikoleris@arm.com Tick next_pf_time = std::max(prefetcher->nextPrefetchReadyTime(), 52712724Snikos.nikoleris@arm.com clockEdge()); 52812724Snikos.nikoleris@arm.com if (next_pf_time != MaxTick) 52912724Snikos.nikoleris@arm.com schedMemSideSendEvent(next_pf_time); 53012724Snikos.nikoleris@arm.com } 53112724Snikos.nikoleris@arm.com } 53212724Snikos.nikoleris@arm.com 53312724Snikos.nikoleris@arm.com // if we used temp block, check to see if its valid and then clear it out 53412724Snikos.nikoleris@arm.com if (blk == tempBlock && tempBlock->isValid()) { 53512724Snikos.nikoleris@arm.com evictBlock(blk, writebacks); 53612724Snikos.nikoleris@arm.com } 53712724Snikos.nikoleris@arm.com 53812724Snikos.nikoleris@arm.com const Tick forward_time = clockEdge(forwardLatency) + pkt->headerDelay; 53912724Snikos.nikoleris@arm.com // copy writebacks to write buffer 54012724Snikos.nikoleris@arm.com doWritebacks(writebacks, forward_time); 54112724Snikos.nikoleris@arm.com 54212724Snikos.nikoleris@arm.com DPRINTF(CacheVerbose, "%s: Leaving with %s\n", __func__, pkt->print()); 54312724Snikos.nikoleris@arm.com delete pkt; 54412724Snikos.nikoleris@arm.com} 54512724Snikos.nikoleris@arm.com 54612724Snikos.nikoleris@arm.com 54712724Snikos.nikoleris@arm.comTick 54812724Snikos.nikoleris@arm.comBaseCache::recvAtomic(PacketPtr pkt) 54912724Snikos.nikoleris@arm.com{ 55012724Snikos.nikoleris@arm.com // should assert here that there are no outstanding MSHRs or 55112724Snikos.nikoleris@arm.com // writebacks... that would mean that someone used an atomic 55212724Snikos.nikoleris@arm.com // access in timing mode 55312724Snikos.nikoleris@arm.com 55413412Snikos.nikoleris@arm.com // We use lookupLatency here because it is used to specify the latency 55513412Snikos.nikoleris@arm.com // to access. 55613412Snikos.nikoleris@arm.com Cycles lat = lookupLatency; 55713412Snikos.nikoleris@arm.com 55812724Snikos.nikoleris@arm.com CacheBlk *blk = nullptr; 55912724Snikos.nikoleris@arm.com PacketList writebacks; 56012724Snikos.nikoleris@arm.com bool satisfied = access(pkt, blk, lat, writebacks); 56112724Snikos.nikoleris@arm.com 56212724Snikos.nikoleris@arm.com if (pkt->isClean() && blk && blk->isDirty()) { 56312724Snikos.nikoleris@arm.com // A cache clean opearation is looking for a dirty 56412724Snikos.nikoleris@arm.com // block. If a dirty block is encountered a WriteClean 56512724Snikos.nikoleris@arm.com // will update any copies to the path to the memory 56612724Snikos.nikoleris@arm.com // until the point of reference. 56712724Snikos.nikoleris@arm.com DPRINTF(CacheVerbose, "%s: packet %s found block: %s\n", 56812724Snikos.nikoleris@arm.com __func__, pkt->print(), blk->print()); 56912724Snikos.nikoleris@arm.com PacketPtr wb_pkt = writecleanBlk(blk, pkt->req->getDest(), pkt->id); 57012724Snikos.nikoleris@arm.com writebacks.push_back(wb_pkt); 57112724Snikos.nikoleris@arm.com pkt->setSatisfied(); 57212724Snikos.nikoleris@arm.com } 57312724Snikos.nikoleris@arm.com 57412724Snikos.nikoleris@arm.com // handle writebacks resulting from the access here to ensure they 57512820Srmk35@cl.cam.ac.uk // logically precede anything happening below 57612724Snikos.nikoleris@arm.com doWritebacksAtomic(writebacks); 57712724Snikos.nikoleris@arm.com assert(writebacks.empty()); 57812724Snikos.nikoleris@arm.com 57912724Snikos.nikoleris@arm.com if (!satisfied) { 58012724Snikos.nikoleris@arm.com lat += handleAtomicReqMiss(pkt, blk, writebacks); 58112724Snikos.nikoleris@arm.com } 58212724Snikos.nikoleris@arm.com 58312724Snikos.nikoleris@arm.com // Note that we don't invoke the prefetcher at all in atomic mode. 58412724Snikos.nikoleris@arm.com // It's not clear how to do it properly, particularly for 58512724Snikos.nikoleris@arm.com // prefetchers that aggressively generate prefetch candidates and 58612724Snikos.nikoleris@arm.com // rely on bandwidth contention to throttle them; these will tend 58712724Snikos.nikoleris@arm.com // to pollute the cache in atomic mode since there is no bandwidth 58812724Snikos.nikoleris@arm.com // contention. If we ever do want to enable prefetching in atomic 58912724Snikos.nikoleris@arm.com // mode, though, this is the place to do it... see timingAccess() 59012724Snikos.nikoleris@arm.com // for an example (though we'd want to issue the prefetch(es) 59112724Snikos.nikoleris@arm.com // immediately rather than calling requestMemSideBus() as we do 59212724Snikos.nikoleris@arm.com // there). 59312724Snikos.nikoleris@arm.com 59412724Snikos.nikoleris@arm.com // do any writebacks resulting from the response handling 59512724Snikos.nikoleris@arm.com doWritebacksAtomic(writebacks); 59612724Snikos.nikoleris@arm.com 59712724Snikos.nikoleris@arm.com // if we used temp block, check to see if its valid and if so 59812724Snikos.nikoleris@arm.com // clear it out, but only do so after the call to recvAtomic is 59912724Snikos.nikoleris@arm.com // finished so that any downstream observers (such as a snoop 60012724Snikos.nikoleris@arm.com // filter), first see the fill, and only then see the eviction 60112724Snikos.nikoleris@arm.com if (blk == tempBlock && tempBlock->isValid()) { 60212724Snikos.nikoleris@arm.com // the atomic CPU calls recvAtomic for fetch and load/store 60312724Snikos.nikoleris@arm.com // sequentuially, and we may already have a tempBlock 60412724Snikos.nikoleris@arm.com // writeback from the fetch that we have not yet sent 60512724Snikos.nikoleris@arm.com if (tempBlockWriteback) { 60612724Snikos.nikoleris@arm.com // if that is the case, write the prevoius one back, and 60712724Snikos.nikoleris@arm.com // do not schedule any new event 60812724Snikos.nikoleris@arm.com writebackTempBlockAtomic(); 60912724Snikos.nikoleris@arm.com } else { 61012724Snikos.nikoleris@arm.com // the writeback/clean eviction happens after the call to 61112724Snikos.nikoleris@arm.com // recvAtomic has finished (but before any successive 61212724Snikos.nikoleris@arm.com // calls), so that the response handling from the fill is 61312724Snikos.nikoleris@arm.com // allowed to happen first 61412724Snikos.nikoleris@arm.com schedule(writebackTempBlockAtomicEvent, curTick()); 61512724Snikos.nikoleris@arm.com } 61612724Snikos.nikoleris@arm.com 61712724Snikos.nikoleris@arm.com tempBlockWriteback = evictBlock(blk); 61812724Snikos.nikoleris@arm.com } 61912724Snikos.nikoleris@arm.com 62012724Snikos.nikoleris@arm.com if (pkt->needsResponse()) { 62112724Snikos.nikoleris@arm.com pkt->makeAtomicResponse(); 62212724Snikos.nikoleris@arm.com } 62312724Snikos.nikoleris@arm.com 62412724Snikos.nikoleris@arm.com return lat * clockPeriod(); 62512724Snikos.nikoleris@arm.com} 62612724Snikos.nikoleris@arm.com 62712724Snikos.nikoleris@arm.comvoid 62812724Snikos.nikoleris@arm.comBaseCache::functionalAccess(PacketPtr pkt, bool from_cpu_side) 62912724Snikos.nikoleris@arm.com{ 63012724Snikos.nikoleris@arm.com Addr blk_addr = pkt->getBlockAddr(blkSize); 63112724Snikos.nikoleris@arm.com bool is_secure = pkt->isSecure(); 63212724Snikos.nikoleris@arm.com CacheBlk *blk = tags->findBlock(pkt->getAddr(), is_secure); 63312724Snikos.nikoleris@arm.com MSHR *mshr = mshrQueue.findMatch(blk_addr, is_secure); 63412724Snikos.nikoleris@arm.com 63512724Snikos.nikoleris@arm.com pkt->pushLabel(name()); 63612724Snikos.nikoleris@arm.com 63712724Snikos.nikoleris@arm.com CacheBlkPrintWrapper cbpw(blk); 63812724Snikos.nikoleris@arm.com 63912724Snikos.nikoleris@arm.com // Note that just because an L2/L3 has valid data doesn't mean an 64012724Snikos.nikoleris@arm.com // L1 doesn't have a more up-to-date modified copy that still 64112724Snikos.nikoleris@arm.com // needs to be found. As a result we always update the request if 64212724Snikos.nikoleris@arm.com // we have it, but only declare it satisfied if we are the owner. 64312724Snikos.nikoleris@arm.com 64412724Snikos.nikoleris@arm.com // see if we have data at all (owned or otherwise) 64512724Snikos.nikoleris@arm.com bool have_data = blk && blk->isValid() 64612823Srmk35@cl.cam.ac.uk && pkt->trySatisfyFunctional(&cbpw, blk_addr, is_secure, blkSize, 64712823Srmk35@cl.cam.ac.uk blk->data); 64812724Snikos.nikoleris@arm.com 64912724Snikos.nikoleris@arm.com // data we have is dirty if marked as such or if we have an 65012724Snikos.nikoleris@arm.com // in-service MSHR that is pending a modified line 65112724Snikos.nikoleris@arm.com bool have_dirty = 65212724Snikos.nikoleris@arm.com have_data && (blk->isDirty() || 65312724Snikos.nikoleris@arm.com (mshr && mshr->inService && mshr->isPendingModified())); 65412724Snikos.nikoleris@arm.com 65512724Snikos.nikoleris@arm.com bool done = have_dirty || 65612823Srmk35@cl.cam.ac.uk cpuSidePort.trySatisfyFunctional(pkt) || 65712823Srmk35@cl.cam.ac.uk mshrQueue.trySatisfyFunctional(pkt, blk_addr) || 65812823Srmk35@cl.cam.ac.uk writeBuffer.trySatisfyFunctional(pkt, blk_addr) || 65912823Srmk35@cl.cam.ac.uk memSidePort.trySatisfyFunctional(pkt); 66012724Snikos.nikoleris@arm.com 66112724Snikos.nikoleris@arm.com DPRINTF(CacheVerbose, "%s: %s %s%s%s\n", __func__, pkt->print(), 66212724Snikos.nikoleris@arm.com (blk && blk->isValid()) ? "valid " : "", 66312724Snikos.nikoleris@arm.com have_data ? "data " : "", done ? "done " : ""); 66412724Snikos.nikoleris@arm.com 66512724Snikos.nikoleris@arm.com // We're leaving the cache, so pop cache->name() label 66612724Snikos.nikoleris@arm.com pkt->popLabel(); 66712724Snikos.nikoleris@arm.com 66812724Snikos.nikoleris@arm.com if (done) { 66912724Snikos.nikoleris@arm.com pkt->makeResponse(); 67012724Snikos.nikoleris@arm.com } else { 67112724Snikos.nikoleris@arm.com // if it came as a request from the CPU side then make sure it 67212724Snikos.nikoleris@arm.com // continues towards the memory side 67312724Snikos.nikoleris@arm.com if (from_cpu_side) { 67412724Snikos.nikoleris@arm.com memSidePort.sendFunctional(pkt); 67512724Snikos.nikoleris@arm.com } else if (cpuSidePort.isSnooping()) { 67612724Snikos.nikoleris@arm.com // if it came from the memory side, it must be a snoop request 67712724Snikos.nikoleris@arm.com // and we should only forward it if we are forwarding snoops 67812724Snikos.nikoleris@arm.com cpuSidePort.sendFunctionalSnoop(pkt); 67912724Snikos.nikoleris@arm.com } 68012724Snikos.nikoleris@arm.com } 68112724Snikos.nikoleris@arm.com} 68212724Snikos.nikoleris@arm.com 68312724Snikos.nikoleris@arm.com 68412724Snikos.nikoleris@arm.comvoid 68512724Snikos.nikoleris@arm.comBaseCache::cmpAndSwap(CacheBlk *blk, PacketPtr pkt) 68612724Snikos.nikoleris@arm.com{ 68712724Snikos.nikoleris@arm.com assert(pkt->isRequest()); 68812724Snikos.nikoleris@arm.com 68912724Snikos.nikoleris@arm.com uint64_t overwrite_val; 69012724Snikos.nikoleris@arm.com bool overwrite_mem; 69112724Snikos.nikoleris@arm.com uint64_t condition_val64; 69212724Snikos.nikoleris@arm.com uint32_t condition_val32; 69312724Snikos.nikoleris@arm.com 69412724Snikos.nikoleris@arm.com int offset = pkt->getOffset(blkSize); 69512724Snikos.nikoleris@arm.com uint8_t *blk_data = blk->data + offset; 69612724Snikos.nikoleris@arm.com 69712724Snikos.nikoleris@arm.com assert(sizeof(uint64_t) >= pkt->getSize()); 69812724Snikos.nikoleris@arm.com 69912724Snikos.nikoleris@arm.com overwrite_mem = true; 70012724Snikos.nikoleris@arm.com // keep a copy of our possible write value, and copy what is at the 70112724Snikos.nikoleris@arm.com // memory address into the packet 70212724Snikos.nikoleris@arm.com pkt->writeData((uint8_t *)&overwrite_val); 70312724Snikos.nikoleris@arm.com pkt->setData(blk_data); 70412724Snikos.nikoleris@arm.com 70512724Snikos.nikoleris@arm.com if (pkt->req->isCondSwap()) { 70612724Snikos.nikoleris@arm.com if (pkt->getSize() == sizeof(uint64_t)) { 70712724Snikos.nikoleris@arm.com condition_val64 = pkt->req->getExtraData(); 70812724Snikos.nikoleris@arm.com overwrite_mem = !std::memcmp(&condition_val64, blk_data, 70912724Snikos.nikoleris@arm.com sizeof(uint64_t)); 71012724Snikos.nikoleris@arm.com } else if (pkt->getSize() == sizeof(uint32_t)) { 71112724Snikos.nikoleris@arm.com condition_val32 = (uint32_t)pkt->req->getExtraData(); 71212724Snikos.nikoleris@arm.com overwrite_mem = !std::memcmp(&condition_val32, blk_data, 71312724Snikos.nikoleris@arm.com sizeof(uint32_t)); 71412724Snikos.nikoleris@arm.com } else 71512724Snikos.nikoleris@arm.com panic("Invalid size for conditional read/write\n"); 71612724Snikos.nikoleris@arm.com } 71712724Snikos.nikoleris@arm.com 71812724Snikos.nikoleris@arm.com if (overwrite_mem) { 71912724Snikos.nikoleris@arm.com std::memcpy(blk_data, &overwrite_val, pkt->getSize()); 72012724Snikos.nikoleris@arm.com blk->status |= BlkDirty; 72112724Snikos.nikoleris@arm.com } 72212724Snikos.nikoleris@arm.com} 72312724Snikos.nikoleris@arm.com 72412724Snikos.nikoleris@arm.comQueueEntry* 72512724Snikos.nikoleris@arm.comBaseCache::getNextQueueEntry() 72612724Snikos.nikoleris@arm.com{ 72712724Snikos.nikoleris@arm.com // Check both MSHR queue and write buffer for potential requests, 72812724Snikos.nikoleris@arm.com // note that null does not mean there is no request, it could 72912724Snikos.nikoleris@arm.com // simply be that it is not ready 73012724Snikos.nikoleris@arm.com MSHR *miss_mshr = mshrQueue.getNext(); 73112724Snikos.nikoleris@arm.com WriteQueueEntry *wq_entry = writeBuffer.getNext(); 73212724Snikos.nikoleris@arm.com 73312724Snikos.nikoleris@arm.com // If we got a write buffer request ready, first priority is a 73412724Snikos.nikoleris@arm.com // full write buffer, otherwise we favour the miss requests 73512724Snikos.nikoleris@arm.com if (wq_entry && (writeBuffer.isFull() || !miss_mshr)) { 73612724Snikos.nikoleris@arm.com // need to search MSHR queue for conflicting earlier miss. 73712724Snikos.nikoleris@arm.com MSHR *conflict_mshr = 73812724Snikos.nikoleris@arm.com mshrQueue.findPending(wq_entry->blkAddr, 73912724Snikos.nikoleris@arm.com wq_entry->isSecure); 74012724Snikos.nikoleris@arm.com 74112724Snikos.nikoleris@arm.com if (conflict_mshr && conflict_mshr->order < wq_entry->order) { 74212724Snikos.nikoleris@arm.com // Service misses in order until conflict is cleared. 74312724Snikos.nikoleris@arm.com return conflict_mshr; 74412724Snikos.nikoleris@arm.com 74512724Snikos.nikoleris@arm.com // @todo Note that we ignore the ready time of the conflict here 74612724Snikos.nikoleris@arm.com } 74712724Snikos.nikoleris@arm.com 74812724Snikos.nikoleris@arm.com // No conflicts; issue write 74912724Snikos.nikoleris@arm.com return wq_entry; 75012724Snikos.nikoleris@arm.com } else if (miss_mshr) { 75112724Snikos.nikoleris@arm.com // need to check for conflicting earlier writeback 75212724Snikos.nikoleris@arm.com WriteQueueEntry *conflict_mshr = 75312724Snikos.nikoleris@arm.com writeBuffer.findPending(miss_mshr->blkAddr, 75412724Snikos.nikoleris@arm.com miss_mshr->isSecure); 75512724Snikos.nikoleris@arm.com if (conflict_mshr) { 75612724Snikos.nikoleris@arm.com // not sure why we don't check order here... it was in the 75712724Snikos.nikoleris@arm.com // original code but commented out. 75812724Snikos.nikoleris@arm.com 75912724Snikos.nikoleris@arm.com // The only way this happens is if we are 76012724Snikos.nikoleris@arm.com // doing a write and we didn't have permissions 76112724Snikos.nikoleris@arm.com // then subsequently saw a writeback (owned got evicted) 76212724Snikos.nikoleris@arm.com // We need to make sure to perform the writeback first 76312724Snikos.nikoleris@arm.com // To preserve the dirty data, then we can issue the write 76412724Snikos.nikoleris@arm.com 76512724Snikos.nikoleris@arm.com // should we return wq_entry here instead? I.e. do we 76612724Snikos.nikoleris@arm.com // have to flush writes in order? I don't think so... not 76712724Snikos.nikoleris@arm.com // for Alpha anyway. Maybe for x86? 76812724Snikos.nikoleris@arm.com return conflict_mshr; 76912724Snikos.nikoleris@arm.com 77012724Snikos.nikoleris@arm.com // @todo Note that we ignore the ready time of the conflict here 77112724Snikos.nikoleris@arm.com } 77212724Snikos.nikoleris@arm.com 77312724Snikos.nikoleris@arm.com // No conflicts; issue read 77412724Snikos.nikoleris@arm.com return miss_mshr; 77512724Snikos.nikoleris@arm.com } 77612724Snikos.nikoleris@arm.com 77712724Snikos.nikoleris@arm.com // fall through... no pending requests. Try a prefetch. 77812724Snikos.nikoleris@arm.com assert(!miss_mshr && !wq_entry); 77912724Snikos.nikoleris@arm.com if (prefetcher && mshrQueue.canPrefetch()) { 78012724Snikos.nikoleris@arm.com // If we have a miss queue slot, we can try a prefetch 78112724Snikos.nikoleris@arm.com PacketPtr pkt = prefetcher->getPacket(); 78212724Snikos.nikoleris@arm.com if (pkt) { 78312724Snikos.nikoleris@arm.com Addr pf_addr = pkt->getBlockAddr(blkSize); 78412724Snikos.nikoleris@arm.com if (!tags->findBlock(pf_addr, pkt->isSecure()) && 78512724Snikos.nikoleris@arm.com !mshrQueue.findMatch(pf_addr, pkt->isSecure()) && 78612724Snikos.nikoleris@arm.com !writeBuffer.findMatch(pf_addr, pkt->isSecure())) { 78712724Snikos.nikoleris@arm.com // Update statistic on number of prefetches issued 78812724Snikos.nikoleris@arm.com // (hwpf_mshr_misses) 78912724Snikos.nikoleris@arm.com assert(pkt->req->masterId() < system->maxMasters()); 79012724Snikos.nikoleris@arm.com mshr_misses[pkt->cmdToIndex()][pkt->req->masterId()]++; 79112724Snikos.nikoleris@arm.com 79212724Snikos.nikoleris@arm.com // allocate an MSHR and return it, note 79312724Snikos.nikoleris@arm.com // that we send the packet straight away, so do not 79412724Snikos.nikoleris@arm.com // schedule the send 79512724Snikos.nikoleris@arm.com return allocateMissBuffer(pkt, curTick(), false); 79612724Snikos.nikoleris@arm.com } else { 79712724Snikos.nikoleris@arm.com // free the request and packet 79812724Snikos.nikoleris@arm.com delete pkt; 79912724Snikos.nikoleris@arm.com } 80012724Snikos.nikoleris@arm.com } 80112724Snikos.nikoleris@arm.com } 80212724Snikos.nikoleris@arm.com 80312724Snikos.nikoleris@arm.com return nullptr; 80412724Snikos.nikoleris@arm.com} 80512724Snikos.nikoleris@arm.com 80612724Snikos.nikoleris@arm.comvoid 80712724Snikos.nikoleris@arm.comBaseCache::satisfyRequest(PacketPtr pkt, CacheBlk *blk, bool, bool) 80812724Snikos.nikoleris@arm.com{ 80912724Snikos.nikoleris@arm.com assert(pkt->isRequest()); 81012724Snikos.nikoleris@arm.com 81112724Snikos.nikoleris@arm.com assert(blk && blk->isValid()); 81212724Snikos.nikoleris@arm.com // Occasionally this is not true... if we are a lower-level cache 81312724Snikos.nikoleris@arm.com // satisfying a string of Read and ReadEx requests from 81412724Snikos.nikoleris@arm.com // upper-level caches, a Read will mark the block as shared but we 81512724Snikos.nikoleris@arm.com // can satisfy a following ReadEx anyway since we can rely on the 81612724Snikos.nikoleris@arm.com // Read requester(s) to have buffered the ReadEx snoop and to 81712724Snikos.nikoleris@arm.com // invalidate their blocks after receiving them. 81812724Snikos.nikoleris@arm.com // assert(!pkt->needsWritable() || blk->isWritable()); 81912724Snikos.nikoleris@arm.com assert(pkt->getOffset(blkSize) + pkt->getSize() <= blkSize); 82012724Snikos.nikoleris@arm.com 82112724Snikos.nikoleris@arm.com // Check RMW operations first since both isRead() and 82212724Snikos.nikoleris@arm.com // isWrite() will be true for them 82312724Snikos.nikoleris@arm.com if (pkt->cmd == MemCmd::SwapReq) { 82412766Sqtt2@cornell.edu if (pkt->isAtomicOp()) { 82512766Sqtt2@cornell.edu // extract data from cache and save it into the data field in 82612766Sqtt2@cornell.edu // the packet as a return value from this atomic op 82712766Sqtt2@cornell.edu int offset = tags->extractBlkOffset(pkt->getAddr()); 82812766Sqtt2@cornell.edu uint8_t *blk_data = blk->data + offset; 82913377Sodanrc@yahoo.com.br pkt->setData(blk_data); 83012766Sqtt2@cornell.edu 83112766Sqtt2@cornell.edu // execute AMO operation 83212766Sqtt2@cornell.edu (*(pkt->getAtomicOp()))(blk_data); 83312766Sqtt2@cornell.edu 83412766Sqtt2@cornell.edu // set block status to dirty 83512766Sqtt2@cornell.edu blk->status |= BlkDirty; 83612766Sqtt2@cornell.edu } else { 83712766Sqtt2@cornell.edu cmpAndSwap(blk, pkt); 83812766Sqtt2@cornell.edu } 83912724Snikos.nikoleris@arm.com } else if (pkt->isWrite()) { 84012724Snikos.nikoleris@arm.com // we have the block in a writable state and can go ahead, 84112724Snikos.nikoleris@arm.com // note that the line may be also be considered writable in 84212724Snikos.nikoleris@arm.com // downstream caches along the path to memory, but always 84312724Snikos.nikoleris@arm.com // Exclusive, and never Modified 84412724Snikos.nikoleris@arm.com assert(blk->isWritable()); 84512724Snikos.nikoleris@arm.com // Write or WriteLine at the first cache with block in writable state 84612724Snikos.nikoleris@arm.com if (blk->checkWrite(pkt)) { 84712724Snikos.nikoleris@arm.com pkt->writeDataToBlock(blk->data, blkSize); 84812724Snikos.nikoleris@arm.com } 84912724Snikos.nikoleris@arm.com // Always mark the line as dirty (and thus transition to the 85012724Snikos.nikoleris@arm.com // Modified state) even if we are a failed StoreCond so we 85112724Snikos.nikoleris@arm.com // supply data to any snoops that have appended themselves to 85212724Snikos.nikoleris@arm.com // this cache before knowing the store will fail. 85312724Snikos.nikoleris@arm.com blk->status |= BlkDirty; 85412724Snikos.nikoleris@arm.com DPRINTF(CacheVerbose, "%s for %s (write)\n", __func__, pkt->print()); 85512724Snikos.nikoleris@arm.com } else if (pkt->isRead()) { 85612724Snikos.nikoleris@arm.com if (pkt->isLLSC()) { 85712724Snikos.nikoleris@arm.com blk->trackLoadLocked(pkt); 85812724Snikos.nikoleris@arm.com } 85912724Snikos.nikoleris@arm.com 86012724Snikos.nikoleris@arm.com // all read responses have a data payload 86112724Snikos.nikoleris@arm.com assert(pkt->hasRespData()); 86212724Snikos.nikoleris@arm.com pkt->setDataFromBlock(blk->data, blkSize); 86312724Snikos.nikoleris@arm.com } else if (pkt->isUpgrade()) { 86412724Snikos.nikoleris@arm.com // sanity check 86512724Snikos.nikoleris@arm.com assert(!pkt->hasSharers()); 86612724Snikos.nikoleris@arm.com 86712724Snikos.nikoleris@arm.com if (blk->isDirty()) { 86812724Snikos.nikoleris@arm.com // we were in the Owned state, and a cache above us that 86912724Snikos.nikoleris@arm.com // has the line in Shared state needs to be made aware 87012724Snikos.nikoleris@arm.com // that the data it already has is in fact dirty 87112724Snikos.nikoleris@arm.com pkt->setCacheResponding(); 87212724Snikos.nikoleris@arm.com blk->status &= ~BlkDirty; 87312724Snikos.nikoleris@arm.com } 87412794Snikos.nikoleris@arm.com } else if (pkt->isClean()) { 87512794Snikos.nikoleris@arm.com blk->status &= ~BlkDirty; 87612724Snikos.nikoleris@arm.com } else { 87712724Snikos.nikoleris@arm.com assert(pkt->isInvalidate()); 87812724Snikos.nikoleris@arm.com invalidateBlock(blk); 87912724Snikos.nikoleris@arm.com DPRINTF(CacheVerbose, "%s for %s (invalidation)\n", __func__, 88012724Snikos.nikoleris@arm.com pkt->print()); 88112724Snikos.nikoleris@arm.com } 88212724Snikos.nikoleris@arm.com} 88312724Snikos.nikoleris@arm.com 88412724Snikos.nikoleris@arm.com///////////////////////////////////////////////////// 88512724Snikos.nikoleris@arm.com// 88612724Snikos.nikoleris@arm.com// Access path: requests coming in from the CPU side 88712724Snikos.nikoleris@arm.com// 88812724Snikos.nikoleris@arm.com///////////////////////////////////////////////////// 88912724Snikos.nikoleris@arm.com 89012724Snikos.nikoleris@arm.combool 89112724Snikos.nikoleris@arm.comBaseCache::access(PacketPtr pkt, CacheBlk *&blk, Cycles &lat, 89212724Snikos.nikoleris@arm.com PacketList &writebacks) 89312724Snikos.nikoleris@arm.com{ 89412724Snikos.nikoleris@arm.com // sanity check 89512724Snikos.nikoleris@arm.com assert(pkt->isRequest()); 89612724Snikos.nikoleris@arm.com 89712724Snikos.nikoleris@arm.com chatty_assert(!(isReadOnly && pkt->isWrite()), 89812724Snikos.nikoleris@arm.com "Should never see a write in a read-only cache %s\n", 89912724Snikos.nikoleris@arm.com name()); 90012724Snikos.nikoleris@arm.com 90112724Snikos.nikoleris@arm.com // Here lat is the value passed as parameter to accessBlock() function 90212724Snikos.nikoleris@arm.com // that can modify its value. 90312724Snikos.nikoleris@arm.com blk = tags->accessBlock(pkt->getAddr(), pkt->isSecure(), lat); 90412724Snikos.nikoleris@arm.com 90512724Snikos.nikoleris@arm.com DPRINTF(Cache, "%s for %s %s\n", __func__, pkt->print(), 90612724Snikos.nikoleris@arm.com blk ? "hit " + blk->print() : "miss"); 90712724Snikos.nikoleris@arm.com 90812724Snikos.nikoleris@arm.com if (pkt->req->isCacheMaintenance()) { 90912724Snikos.nikoleris@arm.com // A cache maintenance operation is always forwarded to the 91012724Snikos.nikoleris@arm.com // memory below even if the block is found in dirty state. 91112724Snikos.nikoleris@arm.com 91212724Snikos.nikoleris@arm.com // We defer any changes to the state of the block until we 91312724Snikos.nikoleris@arm.com // create and mark as in service the mshr for the downstream 91412724Snikos.nikoleris@arm.com // packet. 91512724Snikos.nikoleris@arm.com return false; 91612724Snikos.nikoleris@arm.com } 91712724Snikos.nikoleris@arm.com 91812724Snikos.nikoleris@arm.com if (pkt->isEviction()) { 91912724Snikos.nikoleris@arm.com // We check for presence of block in above caches before issuing 92012724Snikos.nikoleris@arm.com // Writeback or CleanEvict to write buffer. Therefore the only 92112724Snikos.nikoleris@arm.com // possible cases can be of a CleanEvict packet coming from above 92212724Snikos.nikoleris@arm.com // encountering a Writeback generated in this cache peer cache and 92312724Snikos.nikoleris@arm.com // waiting in the write buffer. Cases of upper level peer caches 92412724Snikos.nikoleris@arm.com // generating CleanEvict and Writeback or simply CleanEvict and 92512724Snikos.nikoleris@arm.com // CleanEvict almost simultaneously will be caught by snoops sent out 92612724Snikos.nikoleris@arm.com // by crossbar. 92712724Snikos.nikoleris@arm.com WriteQueueEntry *wb_entry = writeBuffer.findMatch(pkt->getAddr(), 92812724Snikos.nikoleris@arm.com pkt->isSecure()); 92912724Snikos.nikoleris@arm.com if (wb_entry) { 93012724Snikos.nikoleris@arm.com assert(wb_entry->getNumTargets() == 1); 93112724Snikos.nikoleris@arm.com PacketPtr wbPkt = wb_entry->getTarget()->pkt; 93212724Snikos.nikoleris@arm.com assert(wbPkt->isWriteback()); 93312724Snikos.nikoleris@arm.com 93412724Snikos.nikoleris@arm.com if (pkt->isCleanEviction()) { 93512724Snikos.nikoleris@arm.com // The CleanEvict and WritebackClean snoops into other 93612724Snikos.nikoleris@arm.com // peer caches of the same level while traversing the 93712724Snikos.nikoleris@arm.com // crossbar. If a copy of the block is found, the 93812724Snikos.nikoleris@arm.com // packet is deleted in the crossbar. Hence, none of 93912724Snikos.nikoleris@arm.com // the other upper level caches connected to this 94012724Snikos.nikoleris@arm.com // cache have the block, so we can clear the 94112724Snikos.nikoleris@arm.com // BLOCK_CACHED flag in the Writeback if set and 94212724Snikos.nikoleris@arm.com // discard the CleanEvict by returning true. 94312724Snikos.nikoleris@arm.com wbPkt->clearBlockCached(); 94412724Snikos.nikoleris@arm.com return true; 94512724Snikos.nikoleris@arm.com } else { 94612724Snikos.nikoleris@arm.com assert(pkt->cmd == MemCmd::WritebackDirty); 94712724Snikos.nikoleris@arm.com // Dirty writeback from above trumps our clean 94812724Snikos.nikoleris@arm.com // writeback... discard here 94912724Snikos.nikoleris@arm.com // Note: markInService will remove entry from writeback buffer. 95012724Snikos.nikoleris@arm.com markInService(wb_entry); 95112724Snikos.nikoleris@arm.com delete wbPkt; 95212724Snikos.nikoleris@arm.com } 95312724Snikos.nikoleris@arm.com } 95412724Snikos.nikoleris@arm.com } 95512724Snikos.nikoleris@arm.com 95612724Snikos.nikoleris@arm.com // Writeback handling is special case. We can write the block into 95712724Snikos.nikoleris@arm.com // the cache without having a writeable copy (or any copy at all). 95812724Snikos.nikoleris@arm.com if (pkt->isWriteback()) { 95912724Snikos.nikoleris@arm.com assert(blkSize == pkt->getSize()); 96012724Snikos.nikoleris@arm.com 96112724Snikos.nikoleris@arm.com // we could get a clean writeback while we are having 96212724Snikos.nikoleris@arm.com // outstanding accesses to a block, do the simple thing for 96312724Snikos.nikoleris@arm.com // now and drop the clean writeback so that we do not upset 96412724Snikos.nikoleris@arm.com // any ordering/decisions about ownership already taken 96512724Snikos.nikoleris@arm.com if (pkt->cmd == MemCmd::WritebackClean && 96612724Snikos.nikoleris@arm.com mshrQueue.findMatch(pkt->getAddr(), pkt->isSecure())) { 96712724Snikos.nikoleris@arm.com DPRINTF(Cache, "Clean writeback %#llx to block with MSHR, " 96812724Snikos.nikoleris@arm.com "dropping\n", pkt->getAddr()); 96912724Snikos.nikoleris@arm.com return true; 97012724Snikos.nikoleris@arm.com } 97112724Snikos.nikoleris@arm.com 97212724Snikos.nikoleris@arm.com if (!blk) { 97312724Snikos.nikoleris@arm.com // need to do a replacement 97412754Sodanrc@yahoo.com.br blk = allocateBlock(pkt, writebacks); 97512724Snikos.nikoleris@arm.com if (!blk) { 97612724Snikos.nikoleris@arm.com // no replaceable block available: give up, fwd to next level. 97712724Snikos.nikoleris@arm.com incMissCount(pkt); 97812724Snikos.nikoleris@arm.com return false; 97912724Snikos.nikoleris@arm.com } 98012724Snikos.nikoleris@arm.com 98112724Snikos.nikoleris@arm.com blk->status |= (BlkValid | BlkReadable); 98212724Snikos.nikoleris@arm.com } 98312724Snikos.nikoleris@arm.com // only mark the block dirty if we got a writeback command, 98412724Snikos.nikoleris@arm.com // and leave it as is for a clean writeback 98512724Snikos.nikoleris@arm.com if (pkt->cmd == MemCmd::WritebackDirty) { 98612724Snikos.nikoleris@arm.com // TODO: the coherent cache can assert(!blk->isDirty()); 98712724Snikos.nikoleris@arm.com blk->status |= BlkDirty; 98812724Snikos.nikoleris@arm.com } 98912724Snikos.nikoleris@arm.com // if the packet does not have sharers, it is passing 99012724Snikos.nikoleris@arm.com // writable, and we got the writeback in Modified or Exclusive 99112724Snikos.nikoleris@arm.com // state, if not we are in the Owned or Shared state 99212724Snikos.nikoleris@arm.com if (!pkt->hasSharers()) { 99312724Snikos.nikoleris@arm.com blk->status |= BlkWritable; 99412724Snikos.nikoleris@arm.com } 99512724Snikos.nikoleris@arm.com // nothing else to do; writeback doesn't expect response 99612724Snikos.nikoleris@arm.com assert(!pkt->needsResponse()); 99712724Snikos.nikoleris@arm.com pkt->writeDataToBlock(blk->data, blkSize); 99812724Snikos.nikoleris@arm.com DPRINTF(Cache, "%s new state is %s\n", __func__, blk->print()); 99912724Snikos.nikoleris@arm.com incHitCount(pkt); 100012724Snikos.nikoleris@arm.com // populate the time when the block will be ready to access. 100112724Snikos.nikoleris@arm.com blk->whenReady = clockEdge(fillLatency) + pkt->headerDelay + 100212724Snikos.nikoleris@arm.com pkt->payloadDelay; 100312724Snikos.nikoleris@arm.com return true; 100412724Snikos.nikoleris@arm.com } else if (pkt->cmd == MemCmd::CleanEvict) { 100512724Snikos.nikoleris@arm.com if (blk) { 100612724Snikos.nikoleris@arm.com // Found the block in the tags, need to stop CleanEvict from 100712724Snikos.nikoleris@arm.com // propagating further down the hierarchy. Returning true will 100812724Snikos.nikoleris@arm.com // treat the CleanEvict like a satisfied write request and delete 100912724Snikos.nikoleris@arm.com // it. 101012724Snikos.nikoleris@arm.com return true; 101112724Snikos.nikoleris@arm.com } 101212724Snikos.nikoleris@arm.com // We didn't find the block here, propagate the CleanEvict further 101312724Snikos.nikoleris@arm.com // down the memory hierarchy. Returning false will treat the CleanEvict 101412724Snikos.nikoleris@arm.com // like a Writeback which could not find a replaceable block so has to 101512724Snikos.nikoleris@arm.com // go to next level. 101612724Snikos.nikoleris@arm.com return false; 101712724Snikos.nikoleris@arm.com } else if (pkt->cmd == MemCmd::WriteClean) { 101812724Snikos.nikoleris@arm.com // WriteClean handling is a special case. We can allocate a 101912724Snikos.nikoleris@arm.com // block directly if it doesn't exist and we can update the 102012724Snikos.nikoleris@arm.com // block immediately. The WriteClean transfers the ownership 102112724Snikos.nikoleris@arm.com // of the block as well. 102212724Snikos.nikoleris@arm.com assert(blkSize == pkt->getSize()); 102312724Snikos.nikoleris@arm.com 102412724Snikos.nikoleris@arm.com if (!blk) { 102512724Snikos.nikoleris@arm.com if (pkt->writeThrough()) { 102612724Snikos.nikoleris@arm.com // if this is a write through packet, we don't try to 102712724Snikos.nikoleris@arm.com // allocate if the block is not present 102812724Snikos.nikoleris@arm.com return false; 102912724Snikos.nikoleris@arm.com } else { 103012724Snikos.nikoleris@arm.com // a writeback that misses needs to allocate a new block 103112754Sodanrc@yahoo.com.br blk = allocateBlock(pkt, writebacks); 103212724Snikos.nikoleris@arm.com if (!blk) { 103312724Snikos.nikoleris@arm.com // no replaceable block available: give up, fwd to 103412724Snikos.nikoleris@arm.com // next level. 103512724Snikos.nikoleris@arm.com incMissCount(pkt); 103612724Snikos.nikoleris@arm.com return false; 103712724Snikos.nikoleris@arm.com } 103812724Snikos.nikoleris@arm.com 103912724Snikos.nikoleris@arm.com blk->status |= (BlkValid | BlkReadable); 104012724Snikos.nikoleris@arm.com } 104112724Snikos.nikoleris@arm.com } 104212724Snikos.nikoleris@arm.com 104312724Snikos.nikoleris@arm.com // at this point either this is a writeback or a write-through 104412724Snikos.nikoleris@arm.com // write clean operation and the block is already in this 104512724Snikos.nikoleris@arm.com // cache, we need to update the data and the block flags 104612724Snikos.nikoleris@arm.com assert(blk); 104712724Snikos.nikoleris@arm.com // TODO: the coherent cache can assert(!blk->isDirty()); 104812724Snikos.nikoleris@arm.com if (!pkt->writeThrough()) { 104912724Snikos.nikoleris@arm.com blk->status |= BlkDirty; 105012724Snikos.nikoleris@arm.com } 105112724Snikos.nikoleris@arm.com // nothing else to do; writeback doesn't expect response 105212724Snikos.nikoleris@arm.com assert(!pkt->needsResponse()); 105312724Snikos.nikoleris@arm.com pkt->writeDataToBlock(blk->data, blkSize); 105412724Snikos.nikoleris@arm.com DPRINTF(Cache, "%s new state is %s\n", __func__, blk->print()); 105512724Snikos.nikoleris@arm.com 105612724Snikos.nikoleris@arm.com incHitCount(pkt); 105712724Snikos.nikoleris@arm.com // populate the time when the block will be ready to access. 105812724Snikos.nikoleris@arm.com blk->whenReady = clockEdge(fillLatency) + pkt->headerDelay + 105912724Snikos.nikoleris@arm.com pkt->payloadDelay; 106012724Snikos.nikoleris@arm.com // if this a write-through packet it will be sent to cache 106112724Snikos.nikoleris@arm.com // below 106212724Snikos.nikoleris@arm.com return !pkt->writeThrough(); 106312724Snikos.nikoleris@arm.com } else if (blk && (pkt->needsWritable() ? blk->isWritable() : 106412724Snikos.nikoleris@arm.com blk->isReadable())) { 106512724Snikos.nikoleris@arm.com // OK to satisfy access 106612724Snikos.nikoleris@arm.com incHitCount(pkt); 106712724Snikos.nikoleris@arm.com satisfyRequest(pkt, blk); 106812724Snikos.nikoleris@arm.com maintainClusivity(pkt->fromCache(), blk); 106912724Snikos.nikoleris@arm.com 107012724Snikos.nikoleris@arm.com return true; 107112724Snikos.nikoleris@arm.com } 107212724Snikos.nikoleris@arm.com 107312724Snikos.nikoleris@arm.com // Can't satisfy access normally... either no block (blk == nullptr) 107412724Snikos.nikoleris@arm.com // or have block but need writable 107512724Snikos.nikoleris@arm.com 107612724Snikos.nikoleris@arm.com incMissCount(pkt); 107712724Snikos.nikoleris@arm.com 107812724Snikos.nikoleris@arm.com if (!blk && pkt->isLLSC() && pkt->isWrite()) { 107912724Snikos.nikoleris@arm.com // complete miss on store conditional... just give up now 108012724Snikos.nikoleris@arm.com pkt->req->setExtraData(0); 108112724Snikos.nikoleris@arm.com return true; 108212724Snikos.nikoleris@arm.com } 108312724Snikos.nikoleris@arm.com 108412724Snikos.nikoleris@arm.com return false; 108512724Snikos.nikoleris@arm.com} 108612724Snikos.nikoleris@arm.com 108712724Snikos.nikoleris@arm.comvoid 108812724Snikos.nikoleris@arm.comBaseCache::maintainClusivity(bool from_cache, CacheBlk *blk) 108912724Snikos.nikoleris@arm.com{ 109012724Snikos.nikoleris@arm.com if (from_cache && blk && blk->isValid() && !blk->isDirty() && 109112724Snikos.nikoleris@arm.com clusivity == Enums::mostly_excl) { 109212724Snikos.nikoleris@arm.com // if we have responded to a cache, and our block is still 109312724Snikos.nikoleris@arm.com // valid, but not dirty, and this cache is mostly exclusive 109412724Snikos.nikoleris@arm.com // with respect to the cache above, drop the block 109512724Snikos.nikoleris@arm.com invalidateBlock(blk); 109612724Snikos.nikoleris@arm.com } 109712724Snikos.nikoleris@arm.com} 109812724Snikos.nikoleris@arm.com 109912724Snikos.nikoleris@arm.comCacheBlk* 110012724Snikos.nikoleris@arm.comBaseCache::handleFill(PacketPtr pkt, CacheBlk *blk, PacketList &writebacks, 110112724Snikos.nikoleris@arm.com bool allocate) 110212724Snikos.nikoleris@arm.com{ 110313350Snikos.nikoleris@arm.com assert(pkt->isResponse()); 110412724Snikos.nikoleris@arm.com Addr addr = pkt->getAddr(); 110512724Snikos.nikoleris@arm.com bool is_secure = pkt->isSecure(); 110612724Snikos.nikoleris@arm.com#if TRACING_ON 110712724Snikos.nikoleris@arm.com CacheBlk::State old_state = blk ? blk->status : 0; 110812724Snikos.nikoleris@arm.com#endif 110912724Snikos.nikoleris@arm.com 111012724Snikos.nikoleris@arm.com // When handling a fill, we should have no writes to this line. 111112724Snikos.nikoleris@arm.com assert(addr == pkt->getBlockAddr(blkSize)); 111212724Snikos.nikoleris@arm.com assert(!writeBuffer.findMatch(addr, is_secure)); 111312724Snikos.nikoleris@arm.com 111412724Snikos.nikoleris@arm.com if (!blk) { 111512724Snikos.nikoleris@arm.com // better have read new data... 111613350Snikos.nikoleris@arm.com assert(pkt->hasData() || pkt->cmd == MemCmd::InvalidateResp); 111712724Snikos.nikoleris@arm.com 111812724Snikos.nikoleris@arm.com // need to do a replacement if allocating, otherwise we stick 111912724Snikos.nikoleris@arm.com // with the temporary storage 112012754Sodanrc@yahoo.com.br blk = allocate ? allocateBlock(pkt, writebacks) : nullptr; 112112724Snikos.nikoleris@arm.com 112212724Snikos.nikoleris@arm.com if (!blk) { 112312724Snikos.nikoleris@arm.com // No replaceable block or a mostly exclusive 112412724Snikos.nikoleris@arm.com // cache... just use temporary storage to complete the 112512724Snikos.nikoleris@arm.com // current request and then get rid of it 112612724Snikos.nikoleris@arm.com assert(!tempBlock->isValid()); 112712724Snikos.nikoleris@arm.com blk = tempBlock; 112812730Sodanrc@yahoo.com.br tempBlock->insert(addr, is_secure); 112912724Snikos.nikoleris@arm.com DPRINTF(Cache, "using temp block for %#llx (%s)\n", addr, 113012724Snikos.nikoleris@arm.com is_secure ? "s" : "ns"); 113112724Snikos.nikoleris@arm.com } 113212724Snikos.nikoleris@arm.com 113312724Snikos.nikoleris@arm.com // we should never be overwriting a valid block 113412724Snikos.nikoleris@arm.com assert(!blk->isValid()); 113512724Snikos.nikoleris@arm.com } else { 113612724Snikos.nikoleris@arm.com // existing block... probably an upgrade 113712747Sodanrc@yahoo.com.br assert(regenerateBlkAddr(blk) == addr); 113812729Sodanrc@yahoo.com.br assert(blk->isSecure() == is_secure); 113912724Snikos.nikoleris@arm.com // either we're getting new data or the block should already be valid 114012724Snikos.nikoleris@arm.com assert(pkt->hasData() || blk->isValid()); 114112724Snikos.nikoleris@arm.com // don't clear block status... if block is already dirty we 114212724Snikos.nikoleris@arm.com // don't want to lose that 114312724Snikos.nikoleris@arm.com } 114412724Snikos.nikoleris@arm.com 114512724Snikos.nikoleris@arm.com blk->status |= BlkValid | BlkReadable; 114612724Snikos.nikoleris@arm.com 114712724Snikos.nikoleris@arm.com // sanity check for whole-line writes, which should always be 114812724Snikos.nikoleris@arm.com // marked as writable as part of the fill, and then later marked 114912724Snikos.nikoleris@arm.com // dirty as part of satisfyRequest 115013350Snikos.nikoleris@arm.com if (pkt->cmd == MemCmd::InvalidateResp) { 115112724Snikos.nikoleris@arm.com assert(!pkt->hasSharers()); 115212724Snikos.nikoleris@arm.com } 115312724Snikos.nikoleris@arm.com 115412724Snikos.nikoleris@arm.com // here we deal with setting the appropriate state of the line, 115512724Snikos.nikoleris@arm.com // and we start by looking at the hasSharers flag, and ignore the 115612724Snikos.nikoleris@arm.com // cacheResponding flag (normally signalling dirty data) if the 115712724Snikos.nikoleris@arm.com // packet has sharers, thus the line is never allocated as Owned 115812724Snikos.nikoleris@arm.com // (dirty but not writable), and always ends up being either 115912724Snikos.nikoleris@arm.com // Shared, Exclusive or Modified, see Packet::setCacheResponding 116012724Snikos.nikoleris@arm.com // for more details 116112724Snikos.nikoleris@arm.com if (!pkt->hasSharers()) { 116212724Snikos.nikoleris@arm.com // we could get a writable line from memory (rather than a 116312724Snikos.nikoleris@arm.com // cache) even in a read-only cache, note that we set this bit 116412724Snikos.nikoleris@arm.com // even for a read-only cache, possibly revisit this decision 116512724Snikos.nikoleris@arm.com blk->status |= BlkWritable; 116612724Snikos.nikoleris@arm.com 116712724Snikos.nikoleris@arm.com // check if we got this via cache-to-cache transfer (i.e., from a 116812724Snikos.nikoleris@arm.com // cache that had the block in Modified or Owned state) 116912724Snikos.nikoleris@arm.com if (pkt->cacheResponding()) { 117012724Snikos.nikoleris@arm.com // we got the block in Modified state, and invalidated the 117112724Snikos.nikoleris@arm.com // owners copy 117212724Snikos.nikoleris@arm.com blk->status |= BlkDirty; 117312724Snikos.nikoleris@arm.com 117412724Snikos.nikoleris@arm.com chatty_assert(!isReadOnly, "Should never see dirty snoop response " 117512724Snikos.nikoleris@arm.com "in read-only cache %s\n", name()); 117612724Snikos.nikoleris@arm.com } 117712724Snikos.nikoleris@arm.com } 117812724Snikos.nikoleris@arm.com 117912724Snikos.nikoleris@arm.com DPRINTF(Cache, "Block addr %#llx (%s) moving from state %x to %s\n", 118012724Snikos.nikoleris@arm.com addr, is_secure ? "s" : "ns", old_state, blk->print()); 118112724Snikos.nikoleris@arm.com 118212724Snikos.nikoleris@arm.com // if we got new data, copy it in (checking for a read response 118312724Snikos.nikoleris@arm.com // and a response that has data is the same in the end) 118412724Snikos.nikoleris@arm.com if (pkt->isRead()) { 118512724Snikos.nikoleris@arm.com // sanity checks 118612724Snikos.nikoleris@arm.com assert(pkt->hasData()); 118712724Snikos.nikoleris@arm.com assert(pkt->getSize() == blkSize); 118812724Snikos.nikoleris@arm.com 118912724Snikos.nikoleris@arm.com pkt->writeDataToBlock(blk->data, blkSize); 119012724Snikos.nikoleris@arm.com } 119112724Snikos.nikoleris@arm.com // We pay for fillLatency here. 119212724Snikos.nikoleris@arm.com blk->whenReady = clockEdge() + fillLatency * clockPeriod() + 119312724Snikos.nikoleris@arm.com pkt->payloadDelay; 119412724Snikos.nikoleris@arm.com 119512724Snikos.nikoleris@arm.com return blk; 119612724Snikos.nikoleris@arm.com} 119712724Snikos.nikoleris@arm.com 119812724Snikos.nikoleris@arm.comCacheBlk* 119912754Sodanrc@yahoo.com.brBaseCache::allocateBlock(const PacketPtr pkt, PacketList &writebacks) 120012724Snikos.nikoleris@arm.com{ 120112754Sodanrc@yahoo.com.br // Get address 120212754Sodanrc@yahoo.com.br const Addr addr = pkt->getAddr(); 120312754Sodanrc@yahoo.com.br 120412754Sodanrc@yahoo.com.br // Get secure bit 120512754Sodanrc@yahoo.com.br const bool is_secure = pkt->isSecure(); 120612754Sodanrc@yahoo.com.br 120712724Snikos.nikoleris@arm.com // Find replacement victim 120812744Sodanrc@yahoo.com.br std::vector<CacheBlk*> evict_blks; 120912746Sodanrc@yahoo.com.br CacheBlk *victim = tags->findVictim(addr, is_secure, evict_blks); 121012724Snikos.nikoleris@arm.com 121112724Snikos.nikoleris@arm.com // It is valid to return nullptr if there is no victim 121212744Sodanrc@yahoo.com.br if (!victim) 121312724Snikos.nikoleris@arm.com return nullptr; 121412724Snikos.nikoleris@arm.com 121513222Sodanrc@yahoo.com.br // Print victim block's information 121613222Sodanrc@yahoo.com.br DPRINTF(CacheRepl, "Replacement victim: %s\n", victim->print()); 121713222Sodanrc@yahoo.com.br 121812744Sodanrc@yahoo.com.br // Check for transient state allocations. If any of the entries listed 121912744Sodanrc@yahoo.com.br // for eviction has a transient state, the allocation fails 122012744Sodanrc@yahoo.com.br for (const auto& blk : evict_blks) { 122112744Sodanrc@yahoo.com.br if (blk->isValid()) { 122212744Sodanrc@yahoo.com.br Addr repl_addr = regenerateBlkAddr(blk); 122312744Sodanrc@yahoo.com.br MSHR *repl_mshr = mshrQueue.findMatch(repl_addr, blk->isSecure()); 122412744Sodanrc@yahoo.com.br if (repl_mshr) { 122512744Sodanrc@yahoo.com.br // must be an outstanding upgrade or clean request 122612744Sodanrc@yahoo.com.br // on a block we're about to replace... 122712744Sodanrc@yahoo.com.br assert((!blk->isWritable() && repl_mshr->needsWritable()) || 122812744Sodanrc@yahoo.com.br repl_mshr->isCleaning()); 122912724Snikos.nikoleris@arm.com 123012744Sodanrc@yahoo.com.br // too hard to replace block with transient state 123112744Sodanrc@yahoo.com.br // allocation failed, block not inserted 123212744Sodanrc@yahoo.com.br return nullptr; 123312744Sodanrc@yahoo.com.br } 123412744Sodanrc@yahoo.com.br } 123512744Sodanrc@yahoo.com.br } 123612744Sodanrc@yahoo.com.br 123712744Sodanrc@yahoo.com.br // The victim will be replaced by a new entry, so increase the replacement 123812744Sodanrc@yahoo.com.br // counter if a valid block is being replaced 123912744Sodanrc@yahoo.com.br if (victim->isValid()) { 124012744Sodanrc@yahoo.com.br DPRINTF(Cache, "replacement: replacing %#llx (%s) with %#llx " 124112744Sodanrc@yahoo.com.br "(%s): %s\n", regenerateBlkAddr(victim), 124212744Sodanrc@yahoo.com.br victim->isSecure() ? "s" : "ns", 124312744Sodanrc@yahoo.com.br addr, is_secure ? "s" : "ns", 124412744Sodanrc@yahoo.com.br victim->isDirty() ? "writeback" : "clean"); 124512744Sodanrc@yahoo.com.br 124612744Sodanrc@yahoo.com.br replacements++; 124712744Sodanrc@yahoo.com.br } 124812744Sodanrc@yahoo.com.br 124912744Sodanrc@yahoo.com.br // Evict valid blocks associated to this victim block 125012744Sodanrc@yahoo.com.br for (const auto& blk : evict_blks) { 125112744Sodanrc@yahoo.com.br if (blk->isValid()) { 125212724Snikos.nikoleris@arm.com if (blk->wasPrefetched()) { 125312724Snikos.nikoleris@arm.com unusedPrefetches++; 125412724Snikos.nikoleris@arm.com } 125512744Sodanrc@yahoo.com.br 125612724Snikos.nikoleris@arm.com evictBlock(blk, writebacks); 125712724Snikos.nikoleris@arm.com } 125812724Snikos.nikoleris@arm.com } 125912724Snikos.nikoleris@arm.com 126012754Sodanrc@yahoo.com.br // Insert new block at victimized entry 126113215Sodanrc@yahoo.com.br tags->insertBlock(addr, is_secure, pkt->req->masterId(), 126213215Sodanrc@yahoo.com.br pkt->req->taskId(), victim); 126312754Sodanrc@yahoo.com.br 126412744Sodanrc@yahoo.com.br return victim; 126512724Snikos.nikoleris@arm.com} 126612724Snikos.nikoleris@arm.com 126712724Snikos.nikoleris@arm.comvoid 126812724Snikos.nikoleris@arm.comBaseCache::invalidateBlock(CacheBlk *blk) 126912724Snikos.nikoleris@arm.com{ 127013376Sodanrc@yahoo.com.br // If handling a block present in the Tags, let it do its invalidation 127113376Sodanrc@yahoo.com.br // process, which will update stats and invalidate the block itself 127213376Sodanrc@yahoo.com.br if (blk != tempBlock) { 127312724Snikos.nikoleris@arm.com tags->invalidate(blk); 127413376Sodanrc@yahoo.com.br } else { 127513376Sodanrc@yahoo.com.br tempBlock->invalidate(); 127613376Sodanrc@yahoo.com.br } 127712724Snikos.nikoleris@arm.com} 127812724Snikos.nikoleris@arm.com 127913358Sodanrc@yahoo.com.brvoid 128013358Sodanrc@yahoo.com.brBaseCache::evictBlock(CacheBlk *blk, PacketList &writebacks) 128113358Sodanrc@yahoo.com.br{ 128213358Sodanrc@yahoo.com.br PacketPtr pkt = evictBlock(blk); 128313358Sodanrc@yahoo.com.br if (pkt) { 128413358Sodanrc@yahoo.com.br writebacks.push_back(pkt); 128513358Sodanrc@yahoo.com.br } 128613358Sodanrc@yahoo.com.br} 128713358Sodanrc@yahoo.com.br 128812724Snikos.nikoleris@arm.comPacketPtr 128912724Snikos.nikoleris@arm.comBaseCache::writebackBlk(CacheBlk *blk) 129012724Snikos.nikoleris@arm.com{ 129112724Snikos.nikoleris@arm.com chatty_assert(!isReadOnly || writebackClean, 129212724Snikos.nikoleris@arm.com "Writeback from read-only cache"); 129312724Snikos.nikoleris@arm.com assert(blk && blk->isValid() && (blk->isDirty() || writebackClean)); 129412724Snikos.nikoleris@arm.com 129512724Snikos.nikoleris@arm.com writebacks[Request::wbMasterId]++; 129612724Snikos.nikoleris@arm.com 129712749Sgiacomo.travaglini@arm.com RequestPtr req = std::make_shared<Request>( 129812749Sgiacomo.travaglini@arm.com regenerateBlkAddr(blk), blkSize, 0, Request::wbMasterId); 129912749Sgiacomo.travaglini@arm.com 130012724Snikos.nikoleris@arm.com if (blk->isSecure()) 130112724Snikos.nikoleris@arm.com req->setFlags(Request::SECURE); 130212724Snikos.nikoleris@arm.com 130312724Snikos.nikoleris@arm.com req->taskId(blk->task_id); 130412724Snikos.nikoleris@arm.com 130512724Snikos.nikoleris@arm.com PacketPtr pkt = 130612724Snikos.nikoleris@arm.com new Packet(req, blk->isDirty() ? 130712724Snikos.nikoleris@arm.com MemCmd::WritebackDirty : MemCmd::WritebackClean); 130812724Snikos.nikoleris@arm.com 130912724Snikos.nikoleris@arm.com DPRINTF(Cache, "Create Writeback %s writable: %d, dirty: %d\n", 131012724Snikos.nikoleris@arm.com pkt->print(), blk->isWritable(), blk->isDirty()); 131112724Snikos.nikoleris@arm.com 131212724Snikos.nikoleris@arm.com if (blk->isWritable()) { 131312724Snikos.nikoleris@arm.com // not asserting shared means we pass the block in modified 131412724Snikos.nikoleris@arm.com // state, mark our own block non-writeable 131512724Snikos.nikoleris@arm.com blk->status &= ~BlkWritable; 131612724Snikos.nikoleris@arm.com } else { 131712724Snikos.nikoleris@arm.com // we are in the Owned state, tell the receiver 131812724Snikos.nikoleris@arm.com pkt->setHasSharers(); 131912724Snikos.nikoleris@arm.com } 132012724Snikos.nikoleris@arm.com 132112724Snikos.nikoleris@arm.com // make sure the block is not marked dirty 132212724Snikos.nikoleris@arm.com blk->status &= ~BlkDirty; 132312724Snikos.nikoleris@arm.com 132412724Snikos.nikoleris@arm.com pkt->allocate(); 132512724Snikos.nikoleris@arm.com pkt->setDataFromBlock(blk->data, blkSize); 132612724Snikos.nikoleris@arm.com 132712724Snikos.nikoleris@arm.com return pkt; 132812724Snikos.nikoleris@arm.com} 132912724Snikos.nikoleris@arm.com 133012724Snikos.nikoleris@arm.comPacketPtr 133112724Snikos.nikoleris@arm.comBaseCache::writecleanBlk(CacheBlk *blk, Request::Flags dest, PacketId id) 133212724Snikos.nikoleris@arm.com{ 133312749Sgiacomo.travaglini@arm.com RequestPtr req = std::make_shared<Request>( 133412749Sgiacomo.travaglini@arm.com regenerateBlkAddr(blk), blkSize, 0, Request::wbMasterId); 133512749Sgiacomo.travaglini@arm.com 133612724Snikos.nikoleris@arm.com if (blk->isSecure()) { 133712724Snikos.nikoleris@arm.com req->setFlags(Request::SECURE); 133812724Snikos.nikoleris@arm.com } 133912724Snikos.nikoleris@arm.com req->taskId(blk->task_id); 134012724Snikos.nikoleris@arm.com 134112724Snikos.nikoleris@arm.com PacketPtr pkt = new Packet(req, MemCmd::WriteClean, blkSize, id); 134212724Snikos.nikoleris@arm.com 134312724Snikos.nikoleris@arm.com if (dest) { 134412724Snikos.nikoleris@arm.com req->setFlags(dest); 134512724Snikos.nikoleris@arm.com pkt->setWriteThrough(); 134612724Snikos.nikoleris@arm.com } 134712724Snikos.nikoleris@arm.com 134812724Snikos.nikoleris@arm.com DPRINTF(Cache, "Create %s writable: %d, dirty: %d\n", pkt->print(), 134912724Snikos.nikoleris@arm.com blk->isWritable(), blk->isDirty()); 135012724Snikos.nikoleris@arm.com 135112724Snikos.nikoleris@arm.com if (blk->isWritable()) { 135212724Snikos.nikoleris@arm.com // not asserting shared means we pass the block in modified 135312724Snikos.nikoleris@arm.com // state, mark our own block non-writeable 135412724Snikos.nikoleris@arm.com blk->status &= ~BlkWritable; 135512724Snikos.nikoleris@arm.com } else { 135612724Snikos.nikoleris@arm.com // we are in the Owned state, tell the receiver 135712724Snikos.nikoleris@arm.com pkt->setHasSharers(); 135812724Snikos.nikoleris@arm.com } 135912724Snikos.nikoleris@arm.com 136012724Snikos.nikoleris@arm.com // make sure the block is not marked dirty 136112724Snikos.nikoleris@arm.com blk->status &= ~BlkDirty; 136212724Snikos.nikoleris@arm.com 136312724Snikos.nikoleris@arm.com pkt->allocate(); 136412724Snikos.nikoleris@arm.com pkt->setDataFromBlock(blk->data, blkSize); 136512724Snikos.nikoleris@arm.com 136612724Snikos.nikoleris@arm.com return pkt; 136712724Snikos.nikoleris@arm.com} 136812724Snikos.nikoleris@arm.com 136912724Snikos.nikoleris@arm.com 137012724Snikos.nikoleris@arm.comvoid 137112724Snikos.nikoleris@arm.comBaseCache::memWriteback() 137212724Snikos.nikoleris@arm.com{ 137312728Snikos.nikoleris@arm.com tags->forEachBlk([this](CacheBlk &blk) { writebackVisitor(blk); }); 137412724Snikos.nikoleris@arm.com} 137512724Snikos.nikoleris@arm.com 137612724Snikos.nikoleris@arm.comvoid 137712724Snikos.nikoleris@arm.comBaseCache::memInvalidate() 137812724Snikos.nikoleris@arm.com{ 137912728Snikos.nikoleris@arm.com tags->forEachBlk([this](CacheBlk &blk) { invalidateVisitor(blk); }); 138012724Snikos.nikoleris@arm.com} 138112724Snikos.nikoleris@arm.com 138212724Snikos.nikoleris@arm.combool 138312724Snikos.nikoleris@arm.comBaseCache::isDirty() const 138412724Snikos.nikoleris@arm.com{ 138512728Snikos.nikoleris@arm.com return tags->anyBlk([](CacheBlk &blk) { return blk.isDirty(); }); 138612724Snikos.nikoleris@arm.com} 138712724Snikos.nikoleris@arm.com 138813416Sjavier.bueno@metempsy.combool 138913416Sjavier.bueno@metempsy.comBaseCache::coalesce() const 139013416Sjavier.bueno@metempsy.com{ 139113416Sjavier.bueno@metempsy.com return writeAllocator && writeAllocator->coalesce(); 139213416Sjavier.bueno@metempsy.com} 139313416Sjavier.bueno@metempsy.com 139412728Snikos.nikoleris@arm.comvoid 139512724Snikos.nikoleris@arm.comBaseCache::writebackVisitor(CacheBlk &blk) 139612724Snikos.nikoleris@arm.com{ 139712724Snikos.nikoleris@arm.com if (blk.isDirty()) { 139812724Snikos.nikoleris@arm.com assert(blk.isValid()); 139912724Snikos.nikoleris@arm.com 140012749Sgiacomo.travaglini@arm.com RequestPtr request = std::make_shared<Request>( 140112749Sgiacomo.travaglini@arm.com regenerateBlkAddr(&blk), blkSize, 0, Request::funcMasterId); 140212749Sgiacomo.travaglini@arm.com 140312749Sgiacomo.travaglini@arm.com request->taskId(blk.task_id); 140412724Snikos.nikoleris@arm.com if (blk.isSecure()) { 140512749Sgiacomo.travaglini@arm.com request->setFlags(Request::SECURE); 140612724Snikos.nikoleris@arm.com } 140712724Snikos.nikoleris@arm.com 140812749Sgiacomo.travaglini@arm.com Packet packet(request, MemCmd::WriteReq); 140912724Snikos.nikoleris@arm.com packet.dataStatic(blk.data); 141012724Snikos.nikoleris@arm.com 141112724Snikos.nikoleris@arm.com memSidePort.sendFunctional(&packet); 141212724Snikos.nikoleris@arm.com 141312724Snikos.nikoleris@arm.com blk.status &= ~BlkDirty; 141412724Snikos.nikoleris@arm.com } 141512724Snikos.nikoleris@arm.com} 141612724Snikos.nikoleris@arm.com 141712728Snikos.nikoleris@arm.comvoid 141812724Snikos.nikoleris@arm.comBaseCache::invalidateVisitor(CacheBlk &blk) 141912724Snikos.nikoleris@arm.com{ 142012724Snikos.nikoleris@arm.com if (blk.isDirty()) 142112724Snikos.nikoleris@arm.com warn_once("Invalidating dirty cache lines. " \ 142212724Snikos.nikoleris@arm.com "Expect things to break.\n"); 142312724Snikos.nikoleris@arm.com 142412724Snikos.nikoleris@arm.com if (blk.isValid()) { 142512724Snikos.nikoleris@arm.com assert(!blk.isDirty()); 142612724Snikos.nikoleris@arm.com invalidateBlock(&blk); 142712724Snikos.nikoleris@arm.com } 142812724Snikos.nikoleris@arm.com} 142912724Snikos.nikoleris@arm.com 143012724Snikos.nikoleris@arm.comTick 143112724Snikos.nikoleris@arm.comBaseCache::nextQueueReadyTime() const 143212724Snikos.nikoleris@arm.com{ 143312724Snikos.nikoleris@arm.com Tick nextReady = std::min(mshrQueue.nextReadyTime(), 143412724Snikos.nikoleris@arm.com writeBuffer.nextReadyTime()); 143512724Snikos.nikoleris@arm.com 143612724Snikos.nikoleris@arm.com // Don't signal prefetch ready time if no MSHRs available 143712724Snikos.nikoleris@arm.com // Will signal once enoguh MSHRs are deallocated 143812724Snikos.nikoleris@arm.com if (prefetcher && mshrQueue.canPrefetch()) { 143912724Snikos.nikoleris@arm.com nextReady = std::min(nextReady, 144012724Snikos.nikoleris@arm.com prefetcher->nextPrefetchReadyTime()); 144112724Snikos.nikoleris@arm.com } 144212724Snikos.nikoleris@arm.com 144312724Snikos.nikoleris@arm.com return nextReady; 144412724Snikos.nikoleris@arm.com} 144512724Snikos.nikoleris@arm.com 144612724Snikos.nikoleris@arm.com 144712724Snikos.nikoleris@arm.combool 144812724Snikos.nikoleris@arm.comBaseCache::sendMSHRQueuePacket(MSHR* mshr) 144912724Snikos.nikoleris@arm.com{ 145012724Snikos.nikoleris@arm.com assert(mshr); 145112724Snikos.nikoleris@arm.com 145212724Snikos.nikoleris@arm.com // use request from 1st target 145312724Snikos.nikoleris@arm.com PacketPtr tgt_pkt = mshr->getTarget()->pkt; 145412724Snikos.nikoleris@arm.com 145512724Snikos.nikoleris@arm.com DPRINTF(Cache, "%s: MSHR %s\n", __func__, tgt_pkt->print()); 145612724Snikos.nikoleris@arm.com 145713352Snikos.nikoleris@arm.com // if the cache is in write coalescing mode or (additionally) in 145813352Snikos.nikoleris@arm.com // no allocation mode, and we have a write packet with an MSHR 145913352Snikos.nikoleris@arm.com // that is not a whole-line write (due to incompatible flags etc), 146013352Snikos.nikoleris@arm.com // then reset the write mode 146113352Snikos.nikoleris@arm.com if (writeAllocator && writeAllocator->coalesce() && tgt_pkt->isWrite()) { 146213352Snikos.nikoleris@arm.com if (!mshr->isWholeLineWrite()) { 146313352Snikos.nikoleris@arm.com // if we are currently write coalescing, hold on the 146413352Snikos.nikoleris@arm.com // MSHR as many cycles extra as we need to completely 146513352Snikos.nikoleris@arm.com // write a cache line 146613352Snikos.nikoleris@arm.com if (writeAllocator->delay(mshr->blkAddr)) { 146713352Snikos.nikoleris@arm.com Tick delay = blkSize / tgt_pkt->getSize() * clockPeriod(); 146813352Snikos.nikoleris@arm.com DPRINTF(CacheVerbose, "Delaying pkt %s %llu ticks to allow " 146913352Snikos.nikoleris@arm.com "for write coalescing\n", tgt_pkt->print(), delay); 147013352Snikos.nikoleris@arm.com mshrQueue.delay(mshr, delay); 147113352Snikos.nikoleris@arm.com return false; 147213352Snikos.nikoleris@arm.com } else { 147313352Snikos.nikoleris@arm.com writeAllocator->reset(); 147413352Snikos.nikoleris@arm.com } 147513352Snikos.nikoleris@arm.com } else { 147613352Snikos.nikoleris@arm.com writeAllocator->resetDelay(mshr->blkAddr); 147713352Snikos.nikoleris@arm.com } 147813352Snikos.nikoleris@arm.com } 147913352Snikos.nikoleris@arm.com 148012724Snikos.nikoleris@arm.com CacheBlk *blk = tags->findBlock(mshr->blkAddr, mshr->isSecure); 148112724Snikos.nikoleris@arm.com 148212724Snikos.nikoleris@arm.com // either a prefetch that is not present upstream, or a normal 148312724Snikos.nikoleris@arm.com // MSHR request, proceed to get the packet to send downstream 148413350Snikos.nikoleris@arm.com PacketPtr pkt = createMissPacket(tgt_pkt, blk, mshr->needsWritable(), 148513350Snikos.nikoleris@arm.com mshr->isWholeLineWrite()); 148612724Snikos.nikoleris@arm.com 148712724Snikos.nikoleris@arm.com mshr->isForward = (pkt == nullptr); 148812724Snikos.nikoleris@arm.com 148912724Snikos.nikoleris@arm.com if (mshr->isForward) { 149012724Snikos.nikoleris@arm.com // not a cache block request, but a response is expected 149112724Snikos.nikoleris@arm.com // make copy of current packet to forward, keep current 149212724Snikos.nikoleris@arm.com // copy for response handling 149312724Snikos.nikoleris@arm.com pkt = new Packet(tgt_pkt, false, true); 149412724Snikos.nikoleris@arm.com assert(!pkt->isWrite()); 149512724Snikos.nikoleris@arm.com } 149612724Snikos.nikoleris@arm.com 149712724Snikos.nikoleris@arm.com // play it safe and append (rather than set) the sender state, 149812724Snikos.nikoleris@arm.com // as forwarded packets may already have existing state 149912724Snikos.nikoleris@arm.com pkt->pushSenderState(mshr); 150012724Snikos.nikoleris@arm.com 150112724Snikos.nikoleris@arm.com if (pkt->isClean() && blk && blk->isDirty()) { 150212724Snikos.nikoleris@arm.com // A cache clean opearation is looking for a dirty block. Mark 150312724Snikos.nikoleris@arm.com // the packet so that the destination xbar can determine that 150412724Snikos.nikoleris@arm.com // there will be a follow-up write packet as well. 150512724Snikos.nikoleris@arm.com pkt->setSatisfied(); 150612724Snikos.nikoleris@arm.com } 150712724Snikos.nikoleris@arm.com 150812724Snikos.nikoleris@arm.com if (!memSidePort.sendTimingReq(pkt)) { 150912724Snikos.nikoleris@arm.com // we are awaiting a retry, but we 151012724Snikos.nikoleris@arm.com // delete the packet and will be creating a new packet 151112724Snikos.nikoleris@arm.com // when we get the opportunity 151212724Snikos.nikoleris@arm.com delete pkt; 151312724Snikos.nikoleris@arm.com 151412724Snikos.nikoleris@arm.com // note that we have now masked any requestBus and 151512724Snikos.nikoleris@arm.com // schedSendEvent (we will wait for a retry before 151612724Snikos.nikoleris@arm.com // doing anything), and this is so even if we do not 151712724Snikos.nikoleris@arm.com // care about this packet and might override it before 151812724Snikos.nikoleris@arm.com // it gets retried 151912724Snikos.nikoleris@arm.com return true; 152012724Snikos.nikoleris@arm.com } else { 152112724Snikos.nikoleris@arm.com // As part of the call to sendTimingReq the packet is 152212724Snikos.nikoleris@arm.com // forwarded to all neighbouring caches (and any caches 152312724Snikos.nikoleris@arm.com // above them) as a snoop. Thus at this point we know if 152412724Snikos.nikoleris@arm.com // any of the neighbouring caches are responding, and if 152512724Snikos.nikoleris@arm.com // so, we know it is dirty, and we can determine if it is 152612724Snikos.nikoleris@arm.com // being passed as Modified, making our MSHR the ordering 152712724Snikos.nikoleris@arm.com // point 152812724Snikos.nikoleris@arm.com bool pending_modified_resp = !pkt->hasSharers() && 152912724Snikos.nikoleris@arm.com pkt->cacheResponding(); 153012724Snikos.nikoleris@arm.com markInService(mshr, pending_modified_resp); 153112724Snikos.nikoleris@arm.com 153212724Snikos.nikoleris@arm.com if (pkt->isClean() && blk && blk->isDirty()) { 153312724Snikos.nikoleris@arm.com // A cache clean opearation is looking for a dirty 153412724Snikos.nikoleris@arm.com // block. If a dirty block is encountered a WriteClean 153512724Snikos.nikoleris@arm.com // will update any copies to the path to the memory 153612724Snikos.nikoleris@arm.com // until the point of reference. 153712724Snikos.nikoleris@arm.com DPRINTF(CacheVerbose, "%s: packet %s found block: %s\n", 153812724Snikos.nikoleris@arm.com __func__, pkt->print(), blk->print()); 153912724Snikos.nikoleris@arm.com PacketPtr wb_pkt = writecleanBlk(blk, pkt->req->getDest(), 154012724Snikos.nikoleris@arm.com pkt->id); 154112724Snikos.nikoleris@arm.com PacketList writebacks; 154212724Snikos.nikoleris@arm.com writebacks.push_back(wb_pkt); 154312724Snikos.nikoleris@arm.com doWritebacks(writebacks, 0); 154412724Snikos.nikoleris@arm.com } 154512724Snikos.nikoleris@arm.com 154612724Snikos.nikoleris@arm.com return false; 154712724Snikos.nikoleris@arm.com } 154812724Snikos.nikoleris@arm.com} 154912724Snikos.nikoleris@arm.com 155012724Snikos.nikoleris@arm.combool 155112724Snikos.nikoleris@arm.comBaseCache::sendWriteQueuePacket(WriteQueueEntry* wq_entry) 155212724Snikos.nikoleris@arm.com{ 155312724Snikos.nikoleris@arm.com assert(wq_entry); 155412724Snikos.nikoleris@arm.com 155512724Snikos.nikoleris@arm.com // always a single target for write queue entries 155612724Snikos.nikoleris@arm.com PacketPtr tgt_pkt = wq_entry->getTarget()->pkt; 155712724Snikos.nikoleris@arm.com 155812724Snikos.nikoleris@arm.com DPRINTF(Cache, "%s: write %s\n", __func__, tgt_pkt->print()); 155912724Snikos.nikoleris@arm.com 156012724Snikos.nikoleris@arm.com // forward as is, both for evictions and uncacheable writes 156112724Snikos.nikoleris@arm.com if (!memSidePort.sendTimingReq(tgt_pkt)) { 156212724Snikos.nikoleris@arm.com // note that we have now masked any requestBus and 156312724Snikos.nikoleris@arm.com // schedSendEvent (we will wait for a retry before 156412724Snikos.nikoleris@arm.com // doing anything), and this is so even if we do not 156512724Snikos.nikoleris@arm.com // care about this packet and might override it before 156612724Snikos.nikoleris@arm.com // it gets retried 156712724Snikos.nikoleris@arm.com return true; 156812724Snikos.nikoleris@arm.com } else { 156912724Snikos.nikoleris@arm.com markInService(wq_entry); 157012724Snikos.nikoleris@arm.com return false; 157112724Snikos.nikoleris@arm.com } 157212724Snikos.nikoleris@arm.com} 157312724Snikos.nikoleris@arm.com 157412724Snikos.nikoleris@arm.comvoid 157512724Snikos.nikoleris@arm.comBaseCache::serialize(CheckpointOut &cp) const 157612724Snikos.nikoleris@arm.com{ 157712724Snikos.nikoleris@arm.com bool dirty(isDirty()); 157812724Snikos.nikoleris@arm.com 157912724Snikos.nikoleris@arm.com if (dirty) { 158012724Snikos.nikoleris@arm.com warn("*** The cache still contains dirty data. ***\n"); 158112724Snikos.nikoleris@arm.com warn(" Make sure to drain the system using the correct flags.\n"); 158212724Snikos.nikoleris@arm.com warn(" This checkpoint will not restore correctly " \ 158312724Snikos.nikoleris@arm.com "and dirty data in the cache will be lost!\n"); 158412724Snikos.nikoleris@arm.com } 158512724Snikos.nikoleris@arm.com 158612724Snikos.nikoleris@arm.com // Since we don't checkpoint the data in the cache, any dirty data 158712724Snikos.nikoleris@arm.com // will be lost when restoring from a checkpoint of a system that 158812724Snikos.nikoleris@arm.com // wasn't drained properly. Flag the checkpoint as invalid if the 158912724Snikos.nikoleris@arm.com // cache contains dirty data. 159012724Snikos.nikoleris@arm.com bool bad_checkpoint(dirty); 159112724Snikos.nikoleris@arm.com SERIALIZE_SCALAR(bad_checkpoint); 159212724Snikos.nikoleris@arm.com} 159312724Snikos.nikoleris@arm.com 159412724Snikos.nikoleris@arm.comvoid 159512724Snikos.nikoleris@arm.comBaseCache::unserialize(CheckpointIn &cp) 159612724Snikos.nikoleris@arm.com{ 159712724Snikos.nikoleris@arm.com bool bad_checkpoint; 159812724Snikos.nikoleris@arm.com UNSERIALIZE_SCALAR(bad_checkpoint); 159912724Snikos.nikoleris@arm.com if (bad_checkpoint) { 160012724Snikos.nikoleris@arm.com fatal("Restoring from checkpoints with dirty caches is not " 160112724Snikos.nikoleris@arm.com "supported in the classic memory system. Please remove any " 160212724Snikos.nikoleris@arm.com "caches or drain them properly before taking checkpoints.\n"); 160312724Snikos.nikoleris@arm.com } 160412724Snikos.nikoleris@arm.com} 160512724Snikos.nikoleris@arm.com 160612724Snikos.nikoleris@arm.comvoid 16072810SN/ABaseCache::regStats() 16082810SN/A{ 160911522Sstephan.diestelhorst@arm.com MemObject::regStats(); 161011522Sstephan.diestelhorst@arm.com 16112810SN/A using namespace Stats; 16122810SN/A 16132810SN/A // Hit statistics 16144022SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 16154022SN/A MemCmd cmd(access_idx); 16164022SN/A const string &cstr = cmd.toString(); 16172810SN/A 16182810SN/A hits[access_idx] 16198833Sdam.sunwoo@arm.com .init(system->maxMasters()) 16202810SN/A .name(name() + "." + cstr + "_hits") 16212810SN/A .desc("number of " + cstr + " hits") 16222810SN/A .flags(total | nozero | nonan) 16232810SN/A ; 16248833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 16258833Sdam.sunwoo@arm.com hits[access_idx].subname(i, system->getMasterName(i)); 16268833Sdam.sunwoo@arm.com } 16272810SN/A } 16282810SN/A 16294871SN/A// These macros make it easier to sum the right subset of commands and 16304871SN/A// to change the subset of commands that are considered "demand" vs 16314871SN/A// "non-demand" 16324871SN/A#define SUM_DEMAND(s) \ 163311455Sandreas.hansson@arm.com (s[MemCmd::ReadReq] + s[MemCmd::WriteReq] + s[MemCmd::WriteLineReq] + \ 163410885Sandreas.hansson@arm.com s[MemCmd::ReadExReq] + s[MemCmd::ReadCleanReq] + s[MemCmd::ReadSharedReq]) 16354871SN/A 16364871SN/A// should writebacks be included here? prior code was inconsistent... 16374871SN/A#define SUM_NON_DEMAND(s) \ 163813367Syuetsu.kodama@riken.jp (s[MemCmd::SoftPFReq] + s[MemCmd::HardPFReq] + s[MemCmd::SoftPFExReq]) 16394871SN/A 16402810SN/A demandHits 16412810SN/A .name(name() + ".demand_hits") 16422810SN/A .desc("number of demand (read+write) hits") 16438833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 16442810SN/A ; 16454871SN/A demandHits = SUM_DEMAND(hits); 16468833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 16478833Sdam.sunwoo@arm.com demandHits.subname(i, system->getMasterName(i)); 16488833Sdam.sunwoo@arm.com } 16492810SN/A 16502810SN/A overallHits 16512810SN/A .name(name() + ".overall_hits") 16522810SN/A .desc("number of overall hits") 16538833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 16542810SN/A ; 16554871SN/A overallHits = demandHits + SUM_NON_DEMAND(hits); 16568833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 16578833Sdam.sunwoo@arm.com overallHits.subname(i, system->getMasterName(i)); 16588833Sdam.sunwoo@arm.com } 16592810SN/A 16602810SN/A // Miss statistics 16614022SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 16624022SN/A MemCmd cmd(access_idx); 16634022SN/A const string &cstr = cmd.toString(); 16642810SN/A 16652810SN/A misses[access_idx] 16668833Sdam.sunwoo@arm.com .init(system->maxMasters()) 16672810SN/A .name(name() + "." + cstr + "_misses") 16682810SN/A .desc("number of " + cstr + " misses") 16692810SN/A .flags(total | nozero | nonan) 16702810SN/A ; 16718833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 16728833Sdam.sunwoo@arm.com misses[access_idx].subname(i, system->getMasterName(i)); 16738833Sdam.sunwoo@arm.com } 16742810SN/A } 16752810SN/A 16762810SN/A demandMisses 16772810SN/A .name(name() + ".demand_misses") 16782810SN/A .desc("number of demand (read+write) misses") 16798833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 16802810SN/A ; 16814871SN/A demandMisses = SUM_DEMAND(misses); 16828833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 16838833Sdam.sunwoo@arm.com demandMisses.subname(i, system->getMasterName(i)); 16848833Sdam.sunwoo@arm.com } 16852810SN/A 16862810SN/A overallMisses 16872810SN/A .name(name() + ".overall_misses") 16882810SN/A .desc("number of overall misses") 16898833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 16902810SN/A ; 16914871SN/A overallMisses = demandMisses + SUM_NON_DEMAND(misses); 16928833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 16938833Sdam.sunwoo@arm.com overallMisses.subname(i, system->getMasterName(i)); 16948833Sdam.sunwoo@arm.com } 16952810SN/A 16962810SN/A // Miss latency statistics 16974022SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 16984022SN/A MemCmd cmd(access_idx); 16994022SN/A const string &cstr = cmd.toString(); 17002810SN/A 17012810SN/A missLatency[access_idx] 17028833Sdam.sunwoo@arm.com .init(system->maxMasters()) 17032810SN/A .name(name() + "." + cstr + "_miss_latency") 17042810SN/A .desc("number of " + cstr + " miss cycles") 17052810SN/A .flags(total | nozero | nonan) 17062810SN/A ; 17078833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 17088833Sdam.sunwoo@arm.com missLatency[access_idx].subname(i, system->getMasterName(i)); 17098833Sdam.sunwoo@arm.com } 17102810SN/A } 17112810SN/A 17122810SN/A demandMissLatency 17132810SN/A .name(name() + ".demand_miss_latency") 17142810SN/A .desc("number of demand (read+write) miss cycles") 17158833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 17162810SN/A ; 17174871SN/A demandMissLatency = SUM_DEMAND(missLatency); 17188833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 17198833Sdam.sunwoo@arm.com demandMissLatency.subname(i, system->getMasterName(i)); 17208833Sdam.sunwoo@arm.com } 17212810SN/A 17222810SN/A overallMissLatency 17232810SN/A .name(name() + ".overall_miss_latency") 17242810SN/A .desc("number of overall miss cycles") 17258833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 17262810SN/A ; 17274871SN/A overallMissLatency = demandMissLatency + SUM_NON_DEMAND(missLatency); 17288833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 17298833Sdam.sunwoo@arm.com overallMissLatency.subname(i, system->getMasterName(i)); 17308833Sdam.sunwoo@arm.com } 17312810SN/A 17322810SN/A // access formulas 17334022SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 17344022SN/A MemCmd cmd(access_idx); 17354022SN/A const string &cstr = cmd.toString(); 17362810SN/A 17372810SN/A accesses[access_idx] 17382810SN/A .name(name() + "." + cstr + "_accesses") 17392810SN/A .desc("number of " + cstr + " accesses(hits+misses)") 17402810SN/A .flags(total | nozero | nonan) 17412810SN/A ; 17428833Sdam.sunwoo@arm.com accesses[access_idx] = hits[access_idx] + misses[access_idx]; 17432810SN/A 17448833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 17458833Sdam.sunwoo@arm.com accesses[access_idx].subname(i, system->getMasterName(i)); 17468833Sdam.sunwoo@arm.com } 17472810SN/A } 17482810SN/A 17492810SN/A demandAccesses 17502810SN/A .name(name() + ".demand_accesses") 17512810SN/A .desc("number of demand (read+write) accesses") 17528833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 17532810SN/A ; 17542810SN/A demandAccesses = demandHits + demandMisses; 17558833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 17568833Sdam.sunwoo@arm.com demandAccesses.subname(i, system->getMasterName(i)); 17578833Sdam.sunwoo@arm.com } 17582810SN/A 17592810SN/A overallAccesses 17602810SN/A .name(name() + ".overall_accesses") 17612810SN/A .desc("number of overall (read+write) accesses") 17628833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 17632810SN/A ; 17642810SN/A overallAccesses = overallHits + overallMisses; 17658833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 17668833Sdam.sunwoo@arm.com overallAccesses.subname(i, system->getMasterName(i)); 17678833Sdam.sunwoo@arm.com } 17682810SN/A 17692810SN/A // miss rate formulas 17704022SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 17714022SN/A MemCmd cmd(access_idx); 17724022SN/A const string &cstr = cmd.toString(); 17732810SN/A 17742810SN/A missRate[access_idx] 17752810SN/A .name(name() + "." + cstr + "_miss_rate") 17762810SN/A .desc("miss rate for " + cstr + " accesses") 17772810SN/A .flags(total | nozero | nonan) 17782810SN/A ; 17798833Sdam.sunwoo@arm.com missRate[access_idx] = misses[access_idx] / accesses[access_idx]; 17802810SN/A 17818833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 17828833Sdam.sunwoo@arm.com missRate[access_idx].subname(i, system->getMasterName(i)); 17838833Sdam.sunwoo@arm.com } 17842810SN/A } 17852810SN/A 17862810SN/A demandMissRate 17872810SN/A .name(name() + ".demand_miss_rate") 17882810SN/A .desc("miss rate for demand accesses") 17898833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 17902810SN/A ; 17912810SN/A demandMissRate = demandMisses / demandAccesses; 17928833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 17938833Sdam.sunwoo@arm.com demandMissRate.subname(i, system->getMasterName(i)); 17948833Sdam.sunwoo@arm.com } 17952810SN/A 17962810SN/A overallMissRate 17972810SN/A .name(name() + ".overall_miss_rate") 17982810SN/A .desc("miss rate for overall accesses") 17998833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 18002810SN/A ; 18012810SN/A overallMissRate = overallMisses / overallAccesses; 18028833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 18038833Sdam.sunwoo@arm.com overallMissRate.subname(i, system->getMasterName(i)); 18048833Sdam.sunwoo@arm.com } 18052810SN/A 18062810SN/A // miss latency formulas 18074022SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 18084022SN/A MemCmd cmd(access_idx); 18094022SN/A const string &cstr = cmd.toString(); 18102810SN/A 18112810SN/A avgMissLatency[access_idx] 18122810SN/A .name(name() + "." + cstr + "_avg_miss_latency") 18132810SN/A .desc("average " + cstr + " miss latency") 18142810SN/A .flags(total | nozero | nonan) 18152810SN/A ; 18162810SN/A avgMissLatency[access_idx] = 18172810SN/A missLatency[access_idx] / misses[access_idx]; 18188833Sdam.sunwoo@arm.com 18198833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 18208833Sdam.sunwoo@arm.com avgMissLatency[access_idx].subname(i, system->getMasterName(i)); 18218833Sdam.sunwoo@arm.com } 18222810SN/A } 18232810SN/A 18242810SN/A demandAvgMissLatency 18252810SN/A .name(name() + ".demand_avg_miss_latency") 18262810SN/A .desc("average overall miss latency") 18278833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 18282810SN/A ; 18292810SN/A demandAvgMissLatency = demandMissLatency / demandMisses; 18308833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 18318833Sdam.sunwoo@arm.com demandAvgMissLatency.subname(i, system->getMasterName(i)); 18328833Sdam.sunwoo@arm.com } 18332810SN/A 18342810SN/A overallAvgMissLatency 18352810SN/A .name(name() + ".overall_avg_miss_latency") 18362810SN/A .desc("average overall miss latency") 18378833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 18382810SN/A ; 18392810SN/A overallAvgMissLatency = overallMissLatency / overallMisses; 18408833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 18418833Sdam.sunwoo@arm.com overallAvgMissLatency.subname(i, system->getMasterName(i)); 18428833Sdam.sunwoo@arm.com } 18432810SN/A 18442810SN/A blocked_cycles.init(NUM_BLOCKED_CAUSES); 18452810SN/A blocked_cycles 18462810SN/A .name(name() + ".blocked_cycles") 18472810SN/A .desc("number of cycles access was blocked") 18482810SN/A .subname(Blocked_NoMSHRs, "no_mshrs") 18492810SN/A .subname(Blocked_NoTargets, "no_targets") 18502810SN/A ; 18512810SN/A 18522810SN/A 18532810SN/A blocked_causes.init(NUM_BLOCKED_CAUSES); 18542810SN/A blocked_causes 18552810SN/A .name(name() + ".blocked") 18562810SN/A .desc("number of cycles access was blocked") 18572810SN/A .subname(Blocked_NoMSHRs, "no_mshrs") 18582810SN/A .subname(Blocked_NoTargets, "no_targets") 18592810SN/A ; 18602810SN/A 18612810SN/A avg_blocked 18622810SN/A .name(name() + ".avg_blocked_cycles") 18632810SN/A .desc("average number of cycles each access was blocked") 18642810SN/A .subname(Blocked_NoMSHRs, "no_mshrs") 18652810SN/A .subname(Blocked_NoTargets, "no_targets") 18662810SN/A ; 18672810SN/A 18682810SN/A avg_blocked = blocked_cycles / blocked_causes; 18692810SN/A 187011436SRekai.GonzalezAlberquilla@arm.com unusedPrefetches 187111436SRekai.GonzalezAlberquilla@arm.com .name(name() + ".unused_prefetches") 187211436SRekai.GonzalezAlberquilla@arm.com .desc("number of HardPF blocks evicted w/o reference") 187311436SRekai.GonzalezAlberquilla@arm.com .flags(nozero) 187411436SRekai.GonzalezAlberquilla@arm.com ; 187511436SRekai.GonzalezAlberquilla@arm.com 18764626SN/A writebacks 18778833Sdam.sunwoo@arm.com .init(system->maxMasters()) 18784626SN/A .name(name() + ".writebacks") 18794626SN/A .desc("number of writebacks") 18808833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 18814626SN/A ; 18828833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 18838833Sdam.sunwoo@arm.com writebacks.subname(i, system->getMasterName(i)); 18848833Sdam.sunwoo@arm.com } 18854626SN/A 18864626SN/A // MSHR statistics 18874626SN/A // MSHR hit statistics 18884626SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 18894626SN/A MemCmd cmd(access_idx); 18904626SN/A const string &cstr = cmd.toString(); 18914626SN/A 18924626SN/A mshr_hits[access_idx] 18938833Sdam.sunwoo@arm.com .init(system->maxMasters()) 18944626SN/A .name(name() + "." + cstr + "_mshr_hits") 18954626SN/A .desc("number of " + cstr + " MSHR hits") 18964626SN/A .flags(total | nozero | nonan) 18974626SN/A ; 18988833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 18998833Sdam.sunwoo@arm.com mshr_hits[access_idx].subname(i, system->getMasterName(i)); 19008833Sdam.sunwoo@arm.com } 19014626SN/A } 19024626SN/A 19034626SN/A demandMshrHits 19044626SN/A .name(name() + ".demand_mshr_hits") 19054626SN/A .desc("number of demand (read+write) MSHR hits") 19068833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 19074626SN/A ; 19084871SN/A demandMshrHits = SUM_DEMAND(mshr_hits); 19098833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 19108833Sdam.sunwoo@arm.com demandMshrHits.subname(i, system->getMasterName(i)); 19118833Sdam.sunwoo@arm.com } 19124626SN/A 19134626SN/A overallMshrHits 19144626SN/A .name(name() + ".overall_mshr_hits") 19154626SN/A .desc("number of overall MSHR hits") 19168833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 19174626SN/A ; 19184871SN/A overallMshrHits = demandMshrHits + SUM_NON_DEMAND(mshr_hits); 19198833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 19208833Sdam.sunwoo@arm.com overallMshrHits.subname(i, system->getMasterName(i)); 19218833Sdam.sunwoo@arm.com } 19224626SN/A 19234626SN/A // MSHR miss statistics 19244626SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 19254626SN/A MemCmd cmd(access_idx); 19264626SN/A const string &cstr = cmd.toString(); 19274626SN/A 19284626SN/A mshr_misses[access_idx] 19298833Sdam.sunwoo@arm.com .init(system->maxMasters()) 19304626SN/A .name(name() + "." + cstr + "_mshr_misses") 19314626SN/A .desc("number of " + cstr + " MSHR misses") 19324626SN/A .flags(total | nozero | nonan) 19334626SN/A ; 19348833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 19358833Sdam.sunwoo@arm.com mshr_misses[access_idx].subname(i, system->getMasterName(i)); 19368833Sdam.sunwoo@arm.com } 19374626SN/A } 19384626SN/A 19394626SN/A demandMshrMisses 19404626SN/A .name(name() + ".demand_mshr_misses") 19414626SN/A .desc("number of demand (read+write) MSHR misses") 19428833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 19434626SN/A ; 19444871SN/A demandMshrMisses = SUM_DEMAND(mshr_misses); 19458833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 19468833Sdam.sunwoo@arm.com demandMshrMisses.subname(i, system->getMasterName(i)); 19478833Sdam.sunwoo@arm.com } 19484626SN/A 19494626SN/A overallMshrMisses 19504626SN/A .name(name() + ".overall_mshr_misses") 19514626SN/A .desc("number of overall MSHR misses") 19528833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 19534626SN/A ; 19544871SN/A overallMshrMisses = demandMshrMisses + SUM_NON_DEMAND(mshr_misses); 19558833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 19568833Sdam.sunwoo@arm.com overallMshrMisses.subname(i, system->getMasterName(i)); 19578833Sdam.sunwoo@arm.com } 19584626SN/A 19594626SN/A // MSHR miss latency statistics 19604626SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 19614626SN/A MemCmd cmd(access_idx); 19624626SN/A const string &cstr = cmd.toString(); 19634626SN/A 19644626SN/A mshr_miss_latency[access_idx] 19658833Sdam.sunwoo@arm.com .init(system->maxMasters()) 19664626SN/A .name(name() + "." + cstr + "_mshr_miss_latency") 19674626SN/A .desc("number of " + cstr + " MSHR miss cycles") 19684626SN/A .flags(total | nozero | nonan) 19694626SN/A ; 19708833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 19718833Sdam.sunwoo@arm.com mshr_miss_latency[access_idx].subname(i, system->getMasterName(i)); 19728833Sdam.sunwoo@arm.com } 19734626SN/A } 19744626SN/A 19754626SN/A demandMshrMissLatency 19764626SN/A .name(name() + ".demand_mshr_miss_latency") 19774626SN/A .desc("number of demand (read+write) MSHR miss cycles") 19788833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 19794626SN/A ; 19804871SN/A demandMshrMissLatency = SUM_DEMAND(mshr_miss_latency); 19818833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 19828833Sdam.sunwoo@arm.com demandMshrMissLatency.subname(i, system->getMasterName(i)); 19838833Sdam.sunwoo@arm.com } 19844626SN/A 19854626SN/A overallMshrMissLatency 19864626SN/A .name(name() + ".overall_mshr_miss_latency") 19874626SN/A .desc("number of overall MSHR miss cycles") 19888833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 19894626SN/A ; 19904871SN/A overallMshrMissLatency = 19914871SN/A demandMshrMissLatency + SUM_NON_DEMAND(mshr_miss_latency); 19928833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 19938833Sdam.sunwoo@arm.com overallMshrMissLatency.subname(i, system->getMasterName(i)); 19948833Sdam.sunwoo@arm.com } 19954626SN/A 19964626SN/A // MSHR uncacheable statistics 19974626SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 19984626SN/A MemCmd cmd(access_idx); 19994626SN/A const string &cstr = cmd.toString(); 20004626SN/A 20014626SN/A mshr_uncacheable[access_idx] 20028833Sdam.sunwoo@arm.com .init(system->maxMasters()) 20034626SN/A .name(name() + "." + cstr + "_mshr_uncacheable") 20044626SN/A .desc("number of " + cstr + " MSHR uncacheable") 20054626SN/A .flags(total | nozero | nonan) 20064626SN/A ; 20078833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 20088833Sdam.sunwoo@arm.com mshr_uncacheable[access_idx].subname(i, system->getMasterName(i)); 20098833Sdam.sunwoo@arm.com } 20104626SN/A } 20114626SN/A 20124626SN/A overallMshrUncacheable 20134626SN/A .name(name() + ".overall_mshr_uncacheable_misses") 20144626SN/A .desc("number of overall MSHR uncacheable misses") 20158833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 20164626SN/A ; 20174871SN/A overallMshrUncacheable = 20184871SN/A SUM_DEMAND(mshr_uncacheable) + SUM_NON_DEMAND(mshr_uncacheable); 20198833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 20208833Sdam.sunwoo@arm.com overallMshrUncacheable.subname(i, system->getMasterName(i)); 20218833Sdam.sunwoo@arm.com } 20224626SN/A 20234626SN/A // MSHR miss latency statistics 20244626SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 20254626SN/A MemCmd cmd(access_idx); 20264626SN/A const string &cstr = cmd.toString(); 20274626SN/A 20284626SN/A mshr_uncacheable_lat[access_idx] 20298833Sdam.sunwoo@arm.com .init(system->maxMasters()) 20304626SN/A .name(name() + "." + cstr + "_mshr_uncacheable_latency") 20314626SN/A .desc("number of " + cstr + " MSHR uncacheable cycles") 20324626SN/A .flags(total | nozero | nonan) 20334626SN/A ; 20348833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 203511483Snikos.nikoleris@arm.com mshr_uncacheable_lat[access_idx].subname( 203611483Snikos.nikoleris@arm.com i, system->getMasterName(i)); 20378833Sdam.sunwoo@arm.com } 20384626SN/A } 20394626SN/A 20404626SN/A overallMshrUncacheableLatency 20414626SN/A .name(name() + ".overall_mshr_uncacheable_latency") 20424626SN/A .desc("number of overall MSHR uncacheable cycles") 20438833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 20444626SN/A ; 20454871SN/A overallMshrUncacheableLatency = 20464871SN/A SUM_DEMAND(mshr_uncacheable_lat) + 20474871SN/A SUM_NON_DEMAND(mshr_uncacheable_lat); 20488833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 20498833Sdam.sunwoo@arm.com overallMshrUncacheableLatency.subname(i, system->getMasterName(i)); 20508833Sdam.sunwoo@arm.com } 20514626SN/A 20524626SN/A#if 0 20534626SN/A // MSHR access formulas 20544626SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 20554626SN/A MemCmd cmd(access_idx); 20564626SN/A const string &cstr = cmd.toString(); 20574626SN/A 20584626SN/A mshrAccesses[access_idx] 20594626SN/A .name(name() + "." + cstr + "_mshr_accesses") 20604626SN/A .desc("number of " + cstr + " mshr accesses(hits+misses)") 20614626SN/A .flags(total | nozero | nonan) 20624626SN/A ; 20634626SN/A mshrAccesses[access_idx] = 20644626SN/A mshr_hits[access_idx] + mshr_misses[access_idx] 20654626SN/A + mshr_uncacheable[access_idx]; 20664626SN/A } 20674626SN/A 20684626SN/A demandMshrAccesses 20694626SN/A .name(name() + ".demand_mshr_accesses") 20704626SN/A .desc("number of demand (read+write) mshr accesses") 20714626SN/A .flags(total | nozero | nonan) 20724626SN/A ; 20734626SN/A demandMshrAccesses = demandMshrHits + demandMshrMisses; 20744626SN/A 20754626SN/A overallMshrAccesses 20764626SN/A .name(name() + ".overall_mshr_accesses") 20774626SN/A .desc("number of overall (read+write) mshr accesses") 20784626SN/A .flags(total | nozero | nonan) 20794626SN/A ; 20804626SN/A overallMshrAccesses = overallMshrHits + overallMshrMisses 20814626SN/A + overallMshrUncacheable; 20824626SN/A#endif 20834626SN/A 20844626SN/A // MSHR miss rate formulas 20854626SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 20864626SN/A MemCmd cmd(access_idx); 20874626SN/A const string &cstr = cmd.toString(); 20884626SN/A 20894626SN/A mshrMissRate[access_idx] 20904626SN/A .name(name() + "." + cstr + "_mshr_miss_rate") 20914626SN/A .desc("mshr miss rate for " + cstr + " accesses") 20924626SN/A .flags(total | nozero | nonan) 20934626SN/A ; 20944626SN/A mshrMissRate[access_idx] = 20954626SN/A mshr_misses[access_idx] / accesses[access_idx]; 20968833Sdam.sunwoo@arm.com 20978833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 20988833Sdam.sunwoo@arm.com mshrMissRate[access_idx].subname(i, system->getMasterName(i)); 20998833Sdam.sunwoo@arm.com } 21004626SN/A } 21014626SN/A 21024626SN/A demandMshrMissRate 21034626SN/A .name(name() + ".demand_mshr_miss_rate") 21044626SN/A .desc("mshr miss rate for demand accesses") 21058833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 21064626SN/A ; 21074626SN/A demandMshrMissRate = demandMshrMisses / demandAccesses; 21088833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 21098833Sdam.sunwoo@arm.com demandMshrMissRate.subname(i, system->getMasterName(i)); 21108833Sdam.sunwoo@arm.com } 21114626SN/A 21124626SN/A overallMshrMissRate 21134626SN/A .name(name() + ".overall_mshr_miss_rate") 21144626SN/A .desc("mshr miss rate for overall accesses") 21158833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 21164626SN/A ; 21174626SN/A overallMshrMissRate = overallMshrMisses / overallAccesses; 21188833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 21198833Sdam.sunwoo@arm.com overallMshrMissRate.subname(i, system->getMasterName(i)); 21208833Sdam.sunwoo@arm.com } 21214626SN/A 21224626SN/A // mshrMiss latency formulas 21234626SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 21244626SN/A MemCmd cmd(access_idx); 21254626SN/A const string &cstr = cmd.toString(); 21264626SN/A 21274626SN/A avgMshrMissLatency[access_idx] 21284626SN/A .name(name() + "." + cstr + "_avg_mshr_miss_latency") 21294626SN/A .desc("average " + cstr + " mshr miss latency") 21304626SN/A .flags(total | nozero | nonan) 21314626SN/A ; 21324626SN/A avgMshrMissLatency[access_idx] = 21334626SN/A mshr_miss_latency[access_idx] / mshr_misses[access_idx]; 21348833Sdam.sunwoo@arm.com 21358833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 213611483Snikos.nikoleris@arm.com avgMshrMissLatency[access_idx].subname( 213711483Snikos.nikoleris@arm.com i, system->getMasterName(i)); 21388833Sdam.sunwoo@arm.com } 21394626SN/A } 21404626SN/A 21414626SN/A demandAvgMshrMissLatency 21424626SN/A .name(name() + ".demand_avg_mshr_miss_latency") 21434626SN/A .desc("average overall mshr miss latency") 21448833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 21454626SN/A ; 21464626SN/A demandAvgMshrMissLatency = demandMshrMissLatency / demandMshrMisses; 21478833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 21488833Sdam.sunwoo@arm.com demandAvgMshrMissLatency.subname(i, system->getMasterName(i)); 21498833Sdam.sunwoo@arm.com } 21504626SN/A 21514626SN/A overallAvgMshrMissLatency 21524626SN/A .name(name() + ".overall_avg_mshr_miss_latency") 21534626SN/A .desc("average overall mshr miss latency") 21548833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 21554626SN/A ; 21564626SN/A overallAvgMshrMissLatency = overallMshrMissLatency / overallMshrMisses; 21578833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 21588833Sdam.sunwoo@arm.com overallAvgMshrMissLatency.subname(i, system->getMasterName(i)); 21598833Sdam.sunwoo@arm.com } 21604626SN/A 21614626SN/A // mshrUncacheable latency formulas 21624626SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 21634626SN/A MemCmd cmd(access_idx); 21644626SN/A const string &cstr = cmd.toString(); 21654626SN/A 21664626SN/A avgMshrUncacheableLatency[access_idx] 21674626SN/A .name(name() + "." + cstr + "_avg_mshr_uncacheable_latency") 21684626SN/A .desc("average " + cstr + " mshr uncacheable latency") 21694626SN/A .flags(total | nozero | nonan) 21704626SN/A ; 21714626SN/A avgMshrUncacheableLatency[access_idx] = 21724626SN/A mshr_uncacheable_lat[access_idx] / mshr_uncacheable[access_idx]; 21738833Sdam.sunwoo@arm.com 21748833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 217511483Snikos.nikoleris@arm.com avgMshrUncacheableLatency[access_idx].subname( 217611483Snikos.nikoleris@arm.com i, system->getMasterName(i)); 21778833Sdam.sunwoo@arm.com } 21784626SN/A } 21794626SN/A 21804626SN/A overallAvgMshrUncacheableLatency 21814626SN/A .name(name() + ".overall_avg_mshr_uncacheable_latency") 21824626SN/A .desc("average overall mshr uncacheable latency") 21838833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 21844626SN/A ; 218511483Snikos.nikoleris@arm.com overallAvgMshrUncacheableLatency = 218611483Snikos.nikoleris@arm.com overallMshrUncacheableLatency / overallMshrUncacheable; 21878833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 21888833Sdam.sunwoo@arm.com overallAvgMshrUncacheableLatency.subname(i, system->getMasterName(i)); 21898833Sdam.sunwoo@arm.com } 21904626SN/A 219112702Snikos.nikoleris@arm.com replacements 219212702Snikos.nikoleris@arm.com .name(name() + ".replacements") 219312702Snikos.nikoleris@arm.com .desc("number of replacements") 219412702Snikos.nikoleris@arm.com ; 21952810SN/A} 219612724Snikos.nikoleris@arm.com 219713416Sjavier.bueno@metempsy.comvoid 219813416Sjavier.bueno@metempsy.comBaseCache::regProbePoints() 219913416Sjavier.bueno@metempsy.com{ 220013416Sjavier.bueno@metempsy.com ppHit = new ProbePointArg<PacketPtr>(this->getProbeManager(), "Hit"); 220113416Sjavier.bueno@metempsy.com ppMiss = new ProbePointArg<PacketPtr>(this->getProbeManager(), "Miss"); 220213416Sjavier.bueno@metempsy.com} 220313416Sjavier.bueno@metempsy.com 220412724Snikos.nikoleris@arm.com/////////////// 220512724Snikos.nikoleris@arm.com// 220612724Snikos.nikoleris@arm.com// CpuSidePort 220712724Snikos.nikoleris@arm.com// 220812724Snikos.nikoleris@arm.com/////////////// 220912724Snikos.nikoleris@arm.combool 221012724Snikos.nikoleris@arm.comBaseCache::CpuSidePort::recvTimingSnoopResp(PacketPtr pkt) 221112724Snikos.nikoleris@arm.com{ 221212725Snikos.nikoleris@arm.com // Snoops shouldn't happen when bypassing caches 221312725Snikos.nikoleris@arm.com assert(!cache->system->bypassCaches()); 221412725Snikos.nikoleris@arm.com 221512725Snikos.nikoleris@arm.com assert(pkt->isResponse()); 221612725Snikos.nikoleris@arm.com 221712724Snikos.nikoleris@arm.com // Express snoop responses from master to slave, e.g., from L1 to L2 221812724Snikos.nikoleris@arm.com cache->recvTimingSnoopResp(pkt); 221912724Snikos.nikoleris@arm.com return true; 222012724Snikos.nikoleris@arm.com} 222112724Snikos.nikoleris@arm.com 222212724Snikos.nikoleris@arm.com 222312724Snikos.nikoleris@arm.combool 222412724Snikos.nikoleris@arm.comBaseCache::CpuSidePort::tryTiming(PacketPtr pkt) 222512724Snikos.nikoleris@arm.com{ 222612725Snikos.nikoleris@arm.com if (cache->system->bypassCaches() || pkt->isExpressSnoop()) { 222712724Snikos.nikoleris@arm.com // always let express snoop packets through even if blocked 222812724Snikos.nikoleris@arm.com return true; 222912724Snikos.nikoleris@arm.com } else if (blocked || mustSendRetry) { 223012724Snikos.nikoleris@arm.com // either already committed to send a retry, or blocked 223112724Snikos.nikoleris@arm.com mustSendRetry = true; 223212724Snikos.nikoleris@arm.com return false; 223312724Snikos.nikoleris@arm.com } 223412724Snikos.nikoleris@arm.com mustSendRetry = false; 223512724Snikos.nikoleris@arm.com return true; 223612724Snikos.nikoleris@arm.com} 223712724Snikos.nikoleris@arm.com 223812724Snikos.nikoleris@arm.combool 223912724Snikos.nikoleris@arm.comBaseCache::CpuSidePort::recvTimingReq(PacketPtr pkt) 224012724Snikos.nikoleris@arm.com{ 224112725Snikos.nikoleris@arm.com assert(pkt->isRequest()); 224212725Snikos.nikoleris@arm.com 224312725Snikos.nikoleris@arm.com if (cache->system->bypassCaches()) { 224412725Snikos.nikoleris@arm.com // Just forward the packet if caches are disabled. 224512725Snikos.nikoleris@arm.com // @todo This should really enqueue the packet rather 224612725Snikos.nikoleris@arm.com bool M5_VAR_USED success = cache->memSidePort.sendTimingReq(pkt); 224712725Snikos.nikoleris@arm.com assert(success); 224812725Snikos.nikoleris@arm.com return true; 224912725Snikos.nikoleris@arm.com } else if (tryTiming(pkt)) { 225012724Snikos.nikoleris@arm.com cache->recvTimingReq(pkt); 225112724Snikos.nikoleris@arm.com return true; 225212724Snikos.nikoleris@arm.com } 225312724Snikos.nikoleris@arm.com return false; 225412724Snikos.nikoleris@arm.com} 225512724Snikos.nikoleris@arm.com 225612724Snikos.nikoleris@arm.comTick 225712724Snikos.nikoleris@arm.comBaseCache::CpuSidePort::recvAtomic(PacketPtr pkt) 225812724Snikos.nikoleris@arm.com{ 225912725Snikos.nikoleris@arm.com if (cache->system->bypassCaches()) { 226012725Snikos.nikoleris@arm.com // Forward the request if the system is in cache bypass mode. 226112725Snikos.nikoleris@arm.com return cache->memSidePort.sendAtomic(pkt); 226212725Snikos.nikoleris@arm.com } else { 226312725Snikos.nikoleris@arm.com return cache->recvAtomic(pkt); 226412725Snikos.nikoleris@arm.com } 226512724Snikos.nikoleris@arm.com} 226612724Snikos.nikoleris@arm.com 226712724Snikos.nikoleris@arm.comvoid 226812724Snikos.nikoleris@arm.comBaseCache::CpuSidePort::recvFunctional(PacketPtr pkt) 226912724Snikos.nikoleris@arm.com{ 227012725Snikos.nikoleris@arm.com if (cache->system->bypassCaches()) { 227112725Snikos.nikoleris@arm.com // The cache should be flushed if we are in cache bypass mode, 227212725Snikos.nikoleris@arm.com // so we don't need to check if we need to update anything. 227312725Snikos.nikoleris@arm.com cache->memSidePort.sendFunctional(pkt); 227412725Snikos.nikoleris@arm.com return; 227512725Snikos.nikoleris@arm.com } 227612725Snikos.nikoleris@arm.com 227712724Snikos.nikoleris@arm.com // functional request 227812724Snikos.nikoleris@arm.com cache->functionalAccess(pkt, true); 227912724Snikos.nikoleris@arm.com} 228012724Snikos.nikoleris@arm.com 228112724Snikos.nikoleris@arm.comAddrRangeList 228212724Snikos.nikoleris@arm.comBaseCache::CpuSidePort::getAddrRanges() const 228312724Snikos.nikoleris@arm.com{ 228412724Snikos.nikoleris@arm.com return cache->getAddrRanges(); 228512724Snikos.nikoleris@arm.com} 228612724Snikos.nikoleris@arm.com 228712724Snikos.nikoleris@arm.com 228812724Snikos.nikoleris@arm.comBaseCache:: 228912724Snikos.nikoleris@arm.comCpuSidePort::CpuSidePort(const std::string &_name, BaseCache *_cache, 229012724Snikos.nikoleris@arm.com const std::string &_label) 229112724Snikos.nikoleris@arm.com : CacheSlavePort(_name, _cache, _label), cache(_cache) 229212724Snikos.nikoleris@arm.com{ 229312724Snikos.nikoleris@arm.com} 229412724Snikos.nikoleris@arm.com 229512724Snikos.nikoleris@arm.com/////////////// 229612724Snikos.nikoleris@arm.com// 229712724Snikos.nikoleris@arm.com// MemSidePort 229812724Snikos.nikoleris@arm.com// 229912724Snikos.nikoleris@arm.com/////////////// 230012724Snikos.nikoleris@arm.combool 230112724Snikos.nikoleris@arm.comBaseCache::MemSidePort::recvTimingResp(PacketPtr pkt) 230212724Snikos.nikoleris@arm.com{ 230312724Snikos.nikoleris@arm.com cache->recvTimingResp(pkt); 230412724Snikos.nikoleris@arm.com return true; 230512724Snikos.nikoleris@arm.com} 230612724Snikos.nikoleris@arm.com 230712724Snikos.nikoleris@arm.com// Express snooping requests to memside port 230812724Snikos.nikoleris@arm.comvoid 230912724Snikos.nikoleris@arm.comBaseCache::MemSidePort::recvTimingSnoopReq(PacketPtr pkt) 231012724Snikos.nikoleris@arm.com{ 231112725Snikos.nikoleris@arm.com // Snoops shouldn't happen when bypassing caches 231212725Snikos.nikoleris@arm.com assert(!cache->system->bypassCaches()); 231312725Snikos.nikoleris@arm.com 231412724Snikos.nikoleris@arm.com // handle snooping requests 231512724Snikos.nikoleris@arm.com cache->recvTimingSnoopReq(pkt); 231612724Snikos.nikoleris@arm.com} 231712724Snikos.nikoleris@arm.com 231812724Snikos.nikoleris@arm.comTick 231912724Snikos.nikoleris@arm.comBaseCache::MemSidePort::recvAtomicSnoop(PacketPtr pkt) 232012724Snikos.nikoleris@arm.com{ 232112725Snikos.nikoleris@arm.com // Snoops shouldn't happen when bypassing caches 232212725Snikos.nikoleris@arm.com assert(!cache->system->bypassCaches()); 232312725Snikos.nikoleris@arm.com 232412724Snikos.nikoleris@arm.com return cache->recvAtomicSnoop(pkt); 232512724Snikos.nikoleris@arm.com} 232612724Snikos.nikoleris@arm.com 232712724Snikos.nikoleris@arm.comvoid 232812724Snikos.nikoleris@arm.comBaseCache::MemSidePort::recvFunctionalSnoop(PacketPtr pkt) 232912724Snikos.nikoleris@arm.com{ 233012725Snikos.nikoleris@arm.com // Snoops shouldn't happen when bypassing caches 233112725Snikos.nikoleris@arm.com assert(!cache->system->bypassCaches()); 233212725Snikos.nikoleris@arm.com 233312724Snikos.nikoleris@arm.com // functional snoop (note that in contrast to atomic we don't have 233412724Snikos.nikoleris@arm.com // a specific functionalSnoop method, as they have the same 233512724Snikos.nikoleris@arm.com // behaviour regardless) 233612724Snikos.nikoleris@arm.com cache->functionalAccess(pkt, false); 233712724Snikos.nikoleris@arm.com} 233812724Snikos.nikoleris@arm.com 233912724Snikos.nikoleris@arm.comvoid 234012724Snikos.nikoleris@arm.comBaseCache::CacheReqPacketQueue::sendDeferredPacket() 234112724Snikos.nikoleris@arm.com{ 234212724Snikos.nikoleris@arm.com // sanity check 234312724Snikos.nikoleris@arm.com assert(!waitingOnRetry); 234412724Snikos.nikoleris@arm.com 234512724Snikos.nikoleris@arm.com // there should never be any deferred request packets in the 234612724Snikos.nikoleris@arm.com // queue, instead we resly on the cache to provide the packets 234712724Snikos.nikoleris@arm.com // from the MSHR queue or write queue 234812724Snikos.nikoleris@arm.com assert(deferredPacketReadyTime() == MaxTick); 234912724Snikos.nikoleris@arm.com 235012724Snikos.nikoleris@arm.com // check for request packets (requests & writebacks) 235112724Snikos.nikoleris@arm.com QueueEntry* entry = cache.getNextQueueEntry(); 235212724Snikos.nikoleris@arm.com 235312724Snikos.nikoleris@arm.com if (!entry) { 235412724Snikos.nikoleris@arm.com // can happen if e.g. we attempt a writeback and fail, but 235512724Snikos.nikoleris@arm.com // before the retry, the writeback is eliminated because 235612724Snikos.nikoleris@arm.com // we snoop another cache's ReadEx. 235712724Snikos.nikoleris@arm.com } else { 235812724Snikos.nikoleris@arm.com // let our snoop responses go first if there are responses to 235912724Snikos.nikoleris@arm.com // the same addresses 236012724Snikos.nikoleris@arm.com if (checkConflictingSnoop(entry->blkAddr)) { 236112724Snikos.nikoleris@arm.com return; 236212724Snikos.nikoleris@arm.com } 236312724Snikos.nikoleris@arm.com waitingOnRetry = entry->sendPacket(cache); 236412724Snikos.nikoleris@arm.com } 236512724Snikos.nikoleris@arm.com 236612724Snikos.nikoleris@arm.com // if we succeeded and are not waiting for a retry, schedule the 236712724Snikos.nikoleris@arm.com // next send considering when the next queue is ready, note that 236812724Snikos.nikoleris@arm.com // snoop responses have their own packet queue and thus schedule 236912724Snikos.nikoleris@arm.com // their own events 237012724Snikos.nikoleris@arm.com if (!waitingOnRetry) { 237112724Snikos.nikoleris@arm.com schedSendEvent(cache.nextQueueReadyTime()); 237212724Snikos.nikoleris@arm.com } 237312724Snikos.nikoleris@arm.com} 237412724Snikos.nikoleris@arm.com 237512724Snikos.nikoleris@arm.comBaseCache::MemSidePort::MemSidePort(const std::string &_name, 237612724Snikos.nikoleris@arm.com BaseCache *_cache, 237712724Snikos.nikoleris@arm.com const std::string &_label) 237812724Snikos.nikoleris@arm.com : CacheMasterPort(_name, _cache, _reqQueue, _snoopRespQueue), 237912724Snikos.nikoleris@arm.com _reqQueue(*_cache, *this, _snoopRespQueue, _label), 238012724Snikos.nikoleris@arm.com _snoopRespQueue(*_cache, *this, _label), cache(_cache) 238112724Snikos.nikoleris@arm.com{ 238212724Snikos.nikoleris@arm.com} 238313352Snikos.nikoleris@arm.com 238413352Snikos.nikoleris@arm.comvoid 238513352Snikos.nikoleris@arm.comWriteAllocator::updateMode(Addr write_addr, unsigned write_size, 238613352Snikos.nikoleris@arm.com Addr blk_addr) 238713352Snikos.nikoleris@arm.com{ 238813352Snikos.nikoleris@arm.com // check if we are continuing where the last write ended 238913352Snikos.nikoleris@arm.com if (nextAddr == write_addr) { 239013352Snikos.nikoleris@arm.com delayCtr[blk_addr] = delayThreshold; 239113352Snikos.nikoleris@arm.com // stop if we have already saturated 239213352Snikos.nikoleris@arm.com if (mode != WriteMode::NO_ALLOCATE) { 239313352Snikos.nikoleris@arm.com byteCount += write_size; 239413352Snikos.nikoleris@arm.com // switch to streaming mode if we have passed the lower 239513352Snikos.nikoleris@arm.com // threshold 239613352Snikos.nikoleris@arm.com if (mode == WriteMode::ALLOCATE && 239713352Snikos.nikoleris@arm.com byteCount > coalesceLimit) { 239813352Snikos.nikoleris@arm.com mode = WriteMode::COALESCE; 239913352Snikos.nikoleris@arm.com DPRINTF(Cache, "Switched to write coalescing\n"); 240013352Snikos.nikoleris@arm.com } else if (mode == WriteMode::COALESCE && 240113352Snikos.nikoleris@arm.com byteCount > noAllocateLimit) { 240213352Snikos.nikoleris@arm.com // and continue and switch to non-allocating mode if we 240313352Snikos.nikoleris@arm.com // pass the upper threshold 240413352Snikos.nikoleris@arm.com mode = WriteMode::NO_ALLOCATE; 240513352Snikos.nikoleris@arm.com DPRINTF(Cache, "Switched to write-no-allocate\n"); 240613352Snikos.nikoleris@arm.com } 240713352Snikos.nikoleris@arm.com } 240813352Snikos.nikoleris@arm.com } else { 240913352Snikos.nikoleris@arm.com // we did not see a write matching the previous one, start 241013352Snikos.nikoleris@arm.com // over again 241113352Snikos.nikoleris@arm.com byteCount = write_size; 241213352Snikos.nikoleris@arm.com mode = WriteMode::ALLOCATE; 241313352Snikos.nikoleris@arm.com resetDelay(blk_addr); 241413352Snikos.nikoleris@arm.com } 241513352Snikos.nikoleris@arm.com nextAddr = write_addr + write_size; 241613352Snikos.nikoleris@arm.com} 241713352Snikos.nikoleris@arm.com 241813352Snikos.nikoleris@arm.comWriteAllocator* 241913352Snikos.nikoleris@arm.comWriteAllocatorParams::create() 242013352Snikos.nikoleris@arm.com{ 242113352Snikos.nikoleris@arm.com return new WriteAllocator(this); 242213352Snikos.nikoleris@arm.com} 2423