Cache.py revision 13352
14486Sbinkertn@umich.edu# Copyright (c) 2012-2013, 2015, 2018 ARM Limited 27897Shestness@cs.utexas.edu# All rights reserved. 34486Sbinkertn@umich.edu# 44486Sbinkertn@umich.edu# The license below extends only to copyright in the software and shall 54486Sbinkertn@umich.edu# not be construed as granting a license to any other intellectual 64486Sbinkertn@umich.edu# property including but not limited to intellectual property relating 74486Sbinkertn@umich.edu# to a hardware implementation of the functionality of the software 84486Sbinkertn@umich.edu# licensed hereunder. You may use the software subject to the license 94486Sbinkertn@umich.edu# terms below provided that you ensure that this notice is replicated 104486Sbinkertn@umich.edu# unmodified and in its entirety in all distributions of the software, 114486Sbinkertn@umich.edu# modified or unmodified, in source code or in binary form. 124486Sbinkertn@umich.edu# 134486Sbinkertn@umich.edu# Copyright (c) 2005-2007 The Regents of The University of Michigan 144486Sbinkertn@umich.edu# All rights reserved. 154486Sbinkertn@umich.edu# 164486Sbinkertn@umich.edu# Redistribution and use in source and binary forms, with or without 174486Sbinkertn@umich.edu# modification, are permitted provided that the following conditions are 184486Sbinkertn@umich.edu# met: redistributions of source code must retain the above copyright 194486Sbinkertn@umich.edu# notice, this list of conditions and the following disclaimer; 204486Sbinkertn@umich.edu# redistributions in binary form must reproduce the above copyright 214486Sbinkertn@umich.edu# notice, this list of conditions and the following disclaimer in the 224486Sbinkertn@umich.edu# documentation and/or other materials provided with the distribution; 234486Sbinkertn@umich.edu# neither the name of the copyright holders nor the names of its 244486Sbinkertn@umich.edu# contributors may be used to endorse or promote products derived from 254486Sbinkertn@umich.edu# this software without specific prior written permission. 264486Sbinkertn@umich.edu# 274486Sbinkertn@umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 284486Sbinkertn@umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 297897Shestness@cs.utexas.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 304486Sbinkertn@umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 313102SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 326654Snate@binkert.org# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 333102SN/A# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 343102SN/A# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 356654Snate@binkert.org# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 368931Sandreas.hansson@arm.com# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 372212SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 389524SAndreas.Sandberg@ARM.com# 399524SAndreas.Sandberg@ARM.com# Authors: Nathan Binkert 402902SN/A# Andreas Hansson 418703Sandreas.hansson@arm.com 421783SN/Afrom m5.params import * 439338SAndreas.Sandberg@arm.comfrom m5.proxy import * 448839Sandreas.hansson@arm.comfrom m5.SimObject import SimObject 457673Snate@binkert.orgfrom MemObject import MemObject 467673Snate@binkert.orgfrom Prefetcher import BasePrefetcher 478597Ssteve.reinhardt@amd.comfrom ReplacementPolicies import * 488597Ssteve.reinhardt@amd.comfrom Tags import * 498597Ssteve.reinhardt@amd.com 508597Ssteve.reinhardt@amd.com 518597Ssteve.reinhardt@amd.com# Enum for cache clusivity, currently mostly inclusive or mostly 528597Ssteve.reinhardt@amd.com# exclusive. 539524SAndreas.Sandberg@ARM.comclass Clusivity(Enum): vals = ['mostly_incl', 'mostly_excl'] 548597Ssteve.reinhardt@amd.com 558597Ssteve.reinhardt@amd.comclass WriteAllocator(SimObject): 564859Snate@binkert.org type = 'WriteAllocator' 578931Sandreas.hansson@arm.com cxx_header = "mem/cache/cache.hh" 588931Sandreas.hansson@arm.com 592902SN/A # Control the limits for when the cache introduces extra delays to 609408Sandreas.hansson@arm.com # allow whole-line write coalescing, and eventually switches to a 619408Sandreas.hansson@arm.com # write-no-allocate policy. 629408Sandreas.hansson@arm.com coalesce_limit = Param.Unsigned(2, "Consecutive lines written before " 639408Sandreas.hansson@arm.com "delaying for coalescing") 649408Sandreas.hansson@arm.com no_allocate_limit = Param.Unsigned(12, "Consecutive lines written before" 659408Sandreas.hansson@arm.com " skipping allocation") 669814Sandreas.hansson@arm.com 679814Sandreas.hansson@arm.com delay_threshold = Param.Unsigned(8, "Number of delay quanta imposed on an " 687914SBrad.Beckmann@amd.com "MSHR with write requests to allow for " 698666SPrakash.Ramrakhyani@arm.com "write coalescing") 707914SBrad.Beckmann@amd.com 717914SBrad.Beckmann@amd.com block_size = Param.Int(Parent.cache_line_size, "block size in bytes") 727914SBrad.Beckmann@amd.com 737914SBrad.Beckmann@amd.com 747914SBrad.Beckmann@amd.comclass BaseCache(MemObject): 757914SBrad.Beckmann@amd.com type = 'BaseCache' 767914SBrad.Beckmann@amd.com abstract = True 777914SBrad.Beckmann@amd.com cxx_header = "mem/cache/base.hh" 787914SBrad.Beckmann@amd.com 797914SBrad.Beckmann@amd.com size = Param.MemorySize("Capacity") 807914SBrad.Beckmann@amd.com assoc = Param.Unsigned("Associativity") 817914SBrad.Beckmann@amd.com 827914SBrad.Beckmann@amd.com tag_latency = Param.Cycles("Tag lookup latency") 838769Sgblack@eecs.umich.edu data_latency = Param.Cycles("Data access latency") 848769Sgblack@eecs.umich.edu response_latency = Param.Cycles("Latency for the return path on a miss"); 858769Sgblack@eecs.umich.edu 868769Sgblack@eecs.umich.edu warmup_percentage = Param.Percent(0, 878769Sgblack@eecs.umich.edu "Percentage of tags to be touched to warm up the cache") 888769Sgblack@eecs.umich.edu 898769Sgblack@eecs.umich.edu max_miss_count = Param.Counter(0, 90 "Number of misses to handle before calling exit") 91 92 mshrs = Param.Unsigned("Number of MSHRs (max outstanding requests)") 93 demand_mshr_reserve = Param.Unsigned(1, "MSHRs reserved for demand access") 94 tgts_per_mshr = Param.Unsigned("Max number of accesses per MSHR") 95 write_buffers = Param.Unsigned(8, "Number of write buffers") 96 97 is_read_only = Param.Bool(False, "Is this cache read only (e.g. inst)") 98 99 prefetcher = Param.BasePrefetcher(NULL,"Prefetcher attached to cache") 100 prefetch_on_access = Param.Bool(False, 101 "Notify the hardware prefetcher on every access (not just misses)") 102 103 tags = Param.BaseTags(BaseSetAssoc(), "Tag store") 104 replacement_policy = Param.BaseReplacementPolicy(LRURP(), 105 "Replacement policy") 106 107 sequential_access = Param.Bool(False, 108 "Whether to access tags and data sequentially") 109 110 cpu_side = SlavePort("Upstream port closer to the CPU and/or device") 111 mem_side = MasterPort("Downstream port closer to memory") 112 113 addr_ranges = VectorParam.AddrRange([AllMemory], 114 "Address range for the CPU-side port (to allow striping)") 115 116 system = Param.System(Parent.any, "System we belong to") 117 118 # Determine if this cache sends out writebacks for clean lines, or 119 # simply clean evicts. In cases where a downstream cache is mostly 120 # exclusive with respect to this cache (acting as a victim cache), 121 # the clean writebacks are essential for performance. In general 122 # this should be set to True for anything but the last-level 123 # cache. 124 writeback_clean = Param.Bool(False, "Writeback clean lines") 125 126 # Control whether this cache should be mostly inclusive or mostly 127 # exclusive with respect to upstream caches. The behaviour on a 128 # fill is determined accordingly. For a mostly inclusive cache, 129 # blocks are allocated on all fill operations. Thus, L1 caches 130 # should be set as mostly inclusive even if they have no upstream 131 # caches. In the case of a mostly exclusive cache, fills are not 132 # allocating unless they came directly from a non-caching source, 133 # e.g. a table walker. Additionally, on a hit from an upstream 134 # cache a line is dropped for a mostly exclusive cache. 135 clusivity = Param.Clusivity('mostly_incl', 136 "Clusivity with upstream cache") 137 138 # The write allocator enables optimizations for streaming write 139 # accesses by first coalescing writes and then avoiding allocation 140 # in the current cache. Typically, this would be enabled in the 141 # data cache. 142 write_allocator = Param.WriteAllocator(NULL, "Write allocator") 143 144class Cache(BaseCache): 145 type = 'Cache' 146 cxx_header = 'mem/cache/cache.hh' 147 148 149class NoncoherentCache(BaseCache): 150 type = 'NoncoherentCache' 151 cxx_header = 'mem/cache/noncoherent_cache.hh' 152 153 # This is typically a last level cache and any clean 154 # writebacks would be unnecessary traffic to the main memory. 155 writeback_clean = False 156 157