Cache.py revision 13352
1# Copyright (c) 2012-2013, 2015, 2018 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license 9# terms below provided that you ensure that this notice is replicated 10# unmodified and in its entirety in all distributions of the software, 11# modified or unmodified, in source code or in binary form. 12# 13# Copyright (c) 2005-2007 The Regents of The University of Michigan 14# All rights reserved. 15# 16# Redistribution and use in source and binary forms, with or without 17# modification, are permitted provided that the following conditions are 18# met: redistributions of source code must retain the above copyright 19# notice, this list of conditions and the following disclaimer; 20# redistributions in binary form must reproduce the above copyright 21# notice, this list of conditions and the following disclaimer in the 22# documentation and/or other materials provided with the distribution; 23# neither the name of the copyright holders nor the names of its 24# contributors may be used to endorse or promote products derived from 25# this software without specific prior written permission. 26# 27# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 28# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 29# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 30# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 31# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 32# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 33# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 34# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 35# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 36# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 37# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 38# 39# Authors: Nathan Binkert 40# Andreas Hansson 41 42from m5.params import * 43from m5.proxy import * 44from m5.SimObject import SimObject 45from MemObject import MemObject 46from Prefetcher import BasePrefetcher 47from ReplacementPolicies import * 48from Tags import * 49 50 51# Enum for cache clusivity, currently mostly inclusive or mostly 52# exclusive. 53class Clusivity(Enum): vals = ['mostly_incl', 'mostly_excl'] 54 55class WriteAllocator(SimObject): 56 type = 'WriteAllocator' 57 cxx_header = "mem/cache/cache.hh" 58 59 # Control the limits for when the cache introduces extra delays to 60 # allow whole-line write coalescing, and eventually switches to a 61 # write-no-allocate policy. 62 coalesce_limit = Param.Unsigned(2, "Consecutive lines written before " 63 "delaying for coalescing") 64 no_allocate_limit = Param.Unsigned(12, "Consecutive lines written before" 65 " skipping allocation") 66 67 delay_threshold = Param.Unsigned(8, "Number of delay quanta imposed on an " 68 "MSHR with write requests to allow for " 69 "write coalescing") 70 71 block_size = Param.Int(Parent.cache_line_size, "block size in bytes") 72 73 74class BaseCache(MemObject): 75 type = 'BaseCache' 76 abstract = True 77 cxx_header = "mem/cache/base.hh" 78 79 size = Param.MemorySize("Capacity") 80 assoc = Param.Unsigned("Associativity") 81 82 tag_latency = Param.Cycles("Tag lookup latency") 83 data_latency = Param.Cycles("Data access latency") 84 response_latency = Param.Cycles("Latency for the return path on a miss"); 85 86 warmup_percentage = Param.Percent(0, 87 "Percentage of tags to be touched to warm up the cache") 88 89 max_miss_count = Param.Counter(0, 90 "Number of misses to handle before calling exit") 91 92 mshrs = Param.Unsigned("Number of MSHRs (max outstanding requests)") 93 demand_mshr_reserve = Param.Unsigned(1, "MSHRs reserved for demand access") 94 tgts_per_mshr = Param.Unsigned("Max number of accesses per MSHR") 95 write_buffers = Param.Unsigned(8, "Number of write buffers") 96 97 is_read_only = Param.Bool(False, "Is this cache read only (e.g. inst)") 98 99 prefetcher = Param.BasePrefetcher(NULL,"Prefetcher attached to cache") 100 prefetch_on_access = Param.Bool(False, 101 "Notify the hardware prefetcher on every access (not just misses)") 102 103 tags = Param.BaseTags(BaseSetAssoc(), "Tag store") 104 replacement_policy = Param.BaseReplacementPolicy(LRURP(), 105 "Replacement policy") 106 107 sequential_access = Param.Bool(False, 108 "Whether to access tags and data sequentially") 109 110 cpu_side = SlavePort("Upstream port closer to the CPU and/or device") 111 mem_side = MasterPort("Downstream port closer to memory") 112 113 addr_ranges = VectorParam.AddrRange([AllMemory], 114 "Address range for the CPU-side port (to allow striping)") 115 116 system = Param.System(Parent.any, "System we belong to") 117 118 # Determine if this cache sends out writebacks for clean lines, or 119 # simply clean evicts. In cases where a downstream cache is mostly 120 # exclusive with respect to this cache (acting as a victim cache), 121 # the clean writebacks are essential for performance. In general 122 # this should be set to True for anything but the last-level 123 # cache. 124 writeback_clean = Param.Bool(False, "Writeback clean lines") 125 126 # Control whether this cache should be mostly inclusive or mostly 127 # exclusive with respect to upstream caches. The behaviour on a 128 # fill is determined accordingly. For a mostly inclusive cache, 129 # blocks are allocated on all fill operations. Thus, L1 caches 130 # should be set as mostly inclusive even if they have no upstream 131 # caches. In the case of a mostly exclusive cache, fills are not 132 # allocating unless they came directly from a non-caching source, 133 # e.g. a table walker. Additionally, on a hit from an upstream 134 # cache a line is dropped for a mostly exclusive cache. 135 clusivity = Param.Clusivity('mostly_incl', 136 "Clusivity with upstream cache") 137 138 # The write allocator enables optimizations for streaming write 139 # accesses by first coalescing writes and then avoiding allocation 140 # in the current cache. Typically, this would be enabled in the 141 # data cache. 142 write_allocator = Param.WriteAllocator(NULL, "Write allocator") 143 144class Cache(BaseCache): 145 type = 'Cache' 146 cxx_header = 'mem/cache/cache.hh' 147 148 149class NoncoherentCache(BaseCache): 150 type = 'NoncoherentCache' 151 cxx_header = 'mem/cache/noncoherent_cache.hh' 152 153 # This is typically a last level cache and any clean 154 # writebacks would be unnecessary traffic to the main memory. 155 writeback_clean = False 156 157