Cache.py revision 10884
11736SN/A# Copyright (c) 2012-2013, 2015 ARM Limited 27778Sgblack@eecs.umich.edu# All rights reserved. 31736SN/A# 41736SN/A# The license below extends only to copyright in the software and shall 51736SN/A# not be construed as granting a license to any other intellectual 61736SN/A# property including but not limited to intellectual property relating 71736SN/A# to a hardware implementation of the functionality of the software 81736SN/A# licensed hereunder. You may use the software subject to the license 91736SN/A# terms below provided that you ensure that this notice is replicated 101736SN/A# unmodified and in its entirety in all distributions of the software, 111736SN/A# modified or unmodified, in source code or in binary form. 121736SN/A# 131736SN/A# Copyright (c) 2005-2007 The Regents of The University of Michigan 141736SN/A# All rights reserved. 151736SN/A# 161736SN/A# Redistribution and use in source and binary forms, with or without 171736SN/A# modification, are permitted provided that the following conditions are 181736SN/A# met: redistributions of source code must retain the above copyright 191736SN/A# notice, this list of conditions and the following disclaimer; 201736SN/A# redistributions in binary form must reproduce the above copyright 211736SN/A# notice, this list of conditions and the following disclaimer in the 221736SN/A# documentation and/or other materials provided with the distribution; 231736SN/A# neither the name of the copyright holders nor the names of its 241736SN/A# contributors may be used to endorse or promote products derived from 251736SN/A# this software without specific prior written permission. 261736SN/A# 272665SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 282665SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 297778Sgblack@eecs.umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 301736SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 311519SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 321519SN/A# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 331519SN/A# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 341519SN/A# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 351519SN/A# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 361519SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 371519SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 381519SN/A# 391519SN/A# Authors: Nathan Binkert 401519SN/A 411519SN/Afrom m5.params import * 421519SN/Afrom m5.proxy import * 431519SN/Afrom MemObject import MemObject 441519SN/Afrom Prefetcher import BasePrefetcher 451519SN/Afrom Tags import * 461519SN/A 471519SN/Aclass BaseCache(MemObject): 481519SN/A type = 'BaseCache' 491519SN/A cxx_header = "mem/cache/base.hh" 501519SN/A 511519SN/A size = Param.MemorySize("Capacity") 521519SN/A assoc = Param.Unsigned("Associativity") 531519SN/A 541519SN/A hit_latency = Param.Cycles("Hit latency") 551606SN/A response_latency = Param.Cycles("Latency for the return path on a miss"); 561519SN/A 571606SN/A max_miss_count = Param.Counter(0, 581606SN/A "Number of misses to handle before calling exit") 591606SN/A 601606SN/A mshrs = Param.Unsigned("Number of MSHRs (max outstanding requests)") 611519SN/A demand_mshr_reserve = Param.Unsigned(1, "MSHRs reserved for demand access") 621606SN/A tgts_per_mshr = Param.Unsigned("Max number of accesses per MSHR") 631519SN/A write_buffers = Param.Unsigned(8, "Number of write buffers") 641606SN/A 651519SN/A forward_snoops = Param.Bool(True, 661606SN/A "Forward snoops from mem side to cpu side") 671519SN/A is_top_level = Param.Bool(False, "Is this cache at the top level (e.g. L1)") 681606SN/A is_read_only = Param.Bool(False, "Is this cache read only (e.g. inst)") 691519SN/A 701606SN/A prefetcher = Param.BasePrefetcher(NULL,"Prefetcher attached to cache") 711519SN/A prefetch_on_access = Param.Bool(False, 721606SN/A "Notify the hardware prefetcher on every access (not just misses)") 731519SN/A 741606SN/A tags = Param.BaseTags(LRU(), "Tag store (replacement policy)") 751519SN/A sequential_access = Param.Bool(False, 761606SN/A "Whether to access tags and data sequentially") 771519SN/A 781606SN/A cpu_side = SlavePort("Upstream port closer to the CPU and/or device") 791519SN/A mem_side = MasterPort("Downstream port closer to memory") 801606SN/A 811519SN/A addr_ranges = VectorParam.AddrRange([AllMemory], 821606SN/A "Address range for the CPU-side port (to allow striping)") 831519SN/A 841606SN/A system = Param.System(Parent.any, "System we belong to") 851519SN/A