Cache.py revision 10884
1# Copyright (c) 2012-2013, 2015 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license 9# terms below provided that you ensure that this notice is replicated 10# unmodified and in its entirety in all distributions of the software, 11# modified or unmodified, in source code or in binary form. 12# 13# Copyright (c) 2005-2007 The Regents of The University of Michigan 14# All rights reserved. 15# 16# Redistribution and use in source and binary forms, with or without 17# modification, are permitted provided that the following conditions are 18# met: redistributions of source code must retain the above copyright 19# notice, this list of conditions and the following disclaimer; 20# redistributions in binary form must reproduce the above copyright 21# notice, this list of conditions and the following disclaimer in the 22# documentation and/or other materials provided with the distribution; 23# neither the name of the copyright holders nor the names of its 24# contributors may be used to endorse or promote products derived from 25# this software without specific prior written permission. 26# 27# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 28# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 29# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 30# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 31# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 32# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 33# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 34# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 35# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 36# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 37# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 38# 39# Authors: Nathan Binkert 40 41from m5.params import * 42from m5.proxy import * 43from MemObject import MemObject 44from Prefetcher import BasePrefetcher 45from Tags import * 46 47class BaseCache(MemObject): 48 type = 'BaseCache' 49 cxx_header = "mem/cache/base.hh" 50 51 size = Param.MemorySize("Capacity") 52 assoc = Param.Unsigned("Associativity") 53 54 hit_latency = Param.Cycles("Hit latency") 55 response_latency = Param.Cycles("Latency for the return path on a miss"); 56 57 max_miss_count = Param.Counter(0, 58 "Number of misses to handle before calling exit") 59 60 mshrs = Param.Unsigned("Number of MSHRs (max outstanding requests)") 61 demand_mshr_reserve = Param.Unsigned(1, "MSHRs reserved for demand access") 62 tgts_per_mshr = Param.Unsigned("Max number of accesses per MSHR") 63 write_buffers = Param.Unsigned(8, "Number of write buffers") 64 65 forward_snoops = Param.Bool(True, 66 "Forward snoops from mem side to cpu side") 67 is_top_level = Param.Bool(False, "Is this cache at the top level (e.g. L1)") 68 is_read_only = Param.Bool(False, "Is this cache read only (e.g. inst)") 69 70 prefetcher = Param.BasePrefetcher(NULL,"Prefetcher attached to cache") 71 prefetch_on_access = Param.Bool(False, 72 "Notify the hardware prefetcher on every access (not just misses)") 73 74 tags = Param.BaseTags(LRU(), "Tag store (replacement policy)") 75 sequential_access = Param.Bool(False, 76 "Whether to access tags and data sequentially") 77 78 cpu_side = SlavePort("Upstream port closer to the CPU and/or device") 79 mem_side = MasterPort("Downstream port closer to memory") 80 81 addr_ranges = VectorParam.AddrRange([AllMemory], 82 "Address range for the CPU-side port (to allow striping)") 83 84 system = Param.System(Parent.any, "System we belong to") 85